* [RFA] Add sh4a to sh-sim (2nd iteration)
@ 2004-01-07 21:56 Michael Snyder
2004-01-07 22:04 ` [RFA] Add sh4a tests to sim/testsuite/sim/sh Michael Snyder
2004-01-08 16:15 ` [RFA] Add sh4a to sh-sim (2nd iteration) Joern Rennecke
0 siblings, 2 replies; 14+ messages in thread
From: Michael Snyder @ 2004-01-07 21:56 UTC (permalink / raw)
To: joern.rennecke; +Cc: amylaar, andrew.stubbs, gdb-patches
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OK, following up on the last round of changes, here is a resubmit
of the simulator port for sh4a. Also changed 'Hitachi' to 'Renesas'
in the comments.
Testsuite updates to follow.
Michael
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2004-01-07 Michael Snyder <msnyder@redhat.com>
* gencode.c: Replace 'Hitachi' with 'Renesas'.
(op tab): Add new instructions for sh4a, DBR, SBR.
(expand_opcode): Add handling for new movxy combinations.
(gensym_caselist): Ditto.
(expand_ppi_movxy): Remove movx/movy expansions,
now handled in expand_opcode.
(gensym): Add some helpful macros.
(expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit
instead of 8-bit table (some insns are ambiguous to 8 bits).
(ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table.
* interp.c: Replace 'Hitachi' with 'Renesas'.
(union saved_state_type): Add dbr, sgr, ldst.
(get_loop_bounds_ext): New function.
(init_dsp): Add bfd_mach_sh4al_dsp.
(sim_resume): Handle extended loop bounds.
Index: gencode.c
===================================================================
RCS file: /cvs/src/src/sim/sh/gencode.c,v
retrieving revision 1.22
diff -p -r1.22 gencode.c
*** gencode.c 6 Jan 2004 01:05:02 -0000 1.22
--- gencode.c 7 Jan 2004 21:38:26 -0000
***************
*** 1,4 ****
! /* Simulator/Opcode generator for the Hitachi Super-H architecture.
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
--- 1,5 ----
! /* Simulator/Opcode generator for the Renesas
! (formerly Hitachi) Super-H architecture.
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
*************** op tab[] =
*** 151,156 ****
--- 152,162 ----
"SET_SR_T (0);",
},
+ /* sh4a */
+ { "", "", "clrdmxy", "0000000010001000",
+ "saved_state.asregs.cregs.named.sr &= ~(SR_MASK_DMX | SR_MASK_DMY);"
+ },
+
{ "", "0", "cmp/eq #<imm>,R0", "10001000i8*1....",
"SET_SR_T (R0 == SEXT (i));",
},
*************** op tab[] =
*** 195,201 ****
"SET_SR_T (0);",
},
! { "", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100", /* ? MVS */
"div1 (R, m, n/*, T*/);",
},
--- 201,207 ----
"SET_SR_T (0);",
},
! { "", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100",
"div1 (R, m, n/*, T*/);",
},
*************** op tab[] =
*** 285,294 ****
},
/* sh4 */
! { "", "", "fipr <FV_M>,<FV_N>", "1111nnmm11101101",
! "/* FIXME: not implemented */",
! "RAISE_EXCEPTION (SIGILL);",
! "/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh2e */
--- 291,309 ----
},
/* sh4 */
! { "", "", "fipr <FV_M>,<FV_N>", "1111vvVV11101101",
! "if (FPSCR_PR)",
! " RAISE_EXCEPTION (SIGILL);",
! "else",
! "{",
! " double fsum = 0;",
! " /* FIXME: check for nans and infinities. */",
! " fsum += FR (v1+0) * FR (v2+0);",
! " fsum += FR (v1+1) * FR (v2+1);",
! " fsum += FR (v1+2) * FR (v2+2);",
! " fsum += FR (v1+3) * FR (v2+3);",
! " SET_FR (v1+3, fsum);",
! "}",
},
/* sh2e */
*************** op tab[] =
*** 440,445 ****
--- 455,465 ----
"FP_UNARY(n, -);",
},
+ /* sh4a */
+ { "", "", "fpchg", "1111011111111101",
+ "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_PR);",
+ },
+
/* sh4 */
{ "", "", "frchg", "1111101111111101",
"if (FPSCR_PR)",
*************** op tab[] =
*** 498,503 ****
--- 518,534 ----
" FPUL = (int)FR(n);",
},
+ /* sh4a */
+ { "", "", "ftrv <FV_N>", "1111vv0111111101",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ "{",
+ " /* FIXME not implemented. */",
+ " printf (\"ftrv xmtrx, FV%d\\n\", v1);",
+ "}",
+ },
+
/* sh2e */
{ "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101",
" union",
*************** op tab[] =
*** 535,546 ****
{ "", "n", "ldc <REG_N>,MOD", "0100nnnn01011110",
"SET_MOD (R[n]);",
},
- #if 0
{ "", "n", "ldc <REG_N>,DBR", "0100nnnn11111010",
! "DBR = R[n];",
! "/* FIXME: user mode */",
},
- #endif
{ "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
"MA (1);",
"CREG (m) = RLAT (R[n]);",
--- 566,583 ----
{ "", "n", "ldc <REG_N>,MOD", "0100nnnn01011110",
"SET_MOD (R[n]);",
},
{ "", "n", "ldc <REG_N>,DBR", "0100nnnn11111010",
! "if (SR_MD)",
! " DBR = R[n]; /* priv mode */",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
! },
! { "", "n", "ldc <REG_N>,SGR", "0100nnnn00111010",
! "if (SR_MD)",
! " SGR = R[n]; /* priv mode */",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
"MA (1);",
"CREG (m) = RLAT (R[n]);",
*************** op tab[] =
*** 558,571 ****
"SET_MOD (RLAT (R[n]));",
"R[n] += 4;",
},
- #if 0
{ "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
"MA (1);",
"DBR = RLAT (R[n]);",
"R[n] += 4;",
"/* FIXME: user mode */",
},
! #endif
/* sh-dsp */
{ "", "", "ldre @(<disp>,PC)", "10001110i8p1....",
--- 595,626 ----
"SET_MOD (RLAT (R[n]));",
"R[n] += 4;",
},
{ "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
"MA (1);",
"DBR = RLAT (R[n]);",
"R[n] += 4;",
"/* FIXME: user mode */",
},
! { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
! "if (SR_MD)",
! "{ /* priv mode */",
! " MA (1);",
! " DBR = RLAT (R[n]);",
! " R[n] += 4;",
! "}",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
! },
! { "n", "n", "ldc.l @<REG_N>+,SGR", "0100nnnn00110110",
! "if (SR_MD)",
! "{ /* priv mode */",
! " MA (1);",
! " SGR = RLAT (R[n]);",
! " R[n] += 4;",
! "}",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
! },
/* sh-dsp */
{ "", "", "ldre @(<disp>,PC)", "10001110i8p1....",
*************** op tab[] =
*** 575,580 ****
--- 630,649 ----
"RS = SEXT (i) * 2 + 4 + PH2T (PC);",
},
+ /* sh4a */
+ { "", "n", "ldrc <REG_N>", "0100nnnn00110100",
+ "SET_RC (R[n]);",
+ "loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);",
+ "CHECK_INSN_PTR (insn_ptr);",
+ "RE |= 1;",
+ },
+ { "", "", "ldrc #<imm>", "10001010i8*1....",
+ "SET_RC (i);",
+ "loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);",
+ "CHECK_INSN_PTR (insn_ptr);",
+ "RE |= 1;",
+ },
+
{ "", "n", "lds <REG_N>,<SREG_M>", "0100nnnnssss1010",
"SREG (m) = R[n];",
},
*************** op tab[] =
*** 777,794 ****
"WLAT (R[n], R[0]);",
},
{ "n", "", "movt <REG_N>", "0000nnnn00101001",
"R[n] = T;",
},
! { "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
! "MACL = ((int)R[n]) * ((int)R[m]);",
},
! #if 0
! { "", "nm", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
! "MACL = R[n] * R[m];",
},
- #endif
/* muls.w - see muls */
{ "", "mn", "muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
--- 846,892 ----
"WLAT (R[n], R[0]);",
},
+ { "n", "0", "movco.l R0, @<REG_N>", "0000nnnn01110011",
+ "/* LDST -> T */",
+ "SET_SR_T (LDST);",
+ "/* if (T) R0 -> (Rn) */",
+ "if (T)",
+ " WLAT (R[n], R[0]);",
+ "/* 0 -> LDST */",
+ "SET_LDST (0);",
+ },
+
+ { "0", "n", "movli.l @<REG_N>, R0", "0000nnnn01100011",
+ "/* 1 -> LDST */",
+ "SET_LDST (1);",
+ "/* (Rn) -> R0 */",
+ "R[0] = RLAT (R[n]);",
+ "/* if (interrupt/exception) 0 -> LDST */",
+ "/* (we don't simulate asynchronous interrupts/exceptions) */",
+ },
+
{ "n", "", "movt <REG_N>", "0000nnnn00101001",
"R[n] = T;",
},
! { "0", "n", "movua.l @<REG_N>,R0", "0100nnnn10101001",
! "int regn = R[n];",
! "MA (1);",
! "R[0] = (RBAT (regn) << 24) + (RBAT (regn + 1) << 16) + ",
! " (RBAT (regn + 2) << 8) + RBAT (regn + 3);",
! "L (n);",
},
! { "0n", "n", "movua.l @<REG_N>+,R0", "0100nnnn11101001",
! "int regn = R[n];",
! "MA (1);",
! "R[0] = (RBAT (regn) << 24) + (RBAT (regn + 1) << 16) + ",
! " (RBAT (regn + 2) << 8) + RBAT (regn + 3);",
! "R[n] += 4;",
! "L (n);",
! },
! { "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
! "MACL = ((int) R[n]) * ((int) R[m]);",
},
/* muls.w - see muls */
{ "", "mn", "muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
*************** op tab[] =
*** 820,825 ****
--- 918,929 ----
"R[n] = ~R[m];",
},
+ /* sh4a */
+ { "", "n", "icbi @<REG_N>", "0000nnnn11100011",
+ "/* Except for the effect on the cache - which is not simulated -",
+ " this is like a nop. */",
+ },
+
{ "", "n", "ocbi @<REG_N>", "0000nnnn10010011",
"RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */",
"/* FIXME: Cache not implemented */",
*************** op tab[] =
*** 851,856 ****
--- 955,972 ----
" this is like a nop. */",
},
+ /* sh4a */
+ { "", "n", "prefi @<REG_N>", "0000nnnn11010011",
+ "/* Except for the effect on the cache - which is not simulated -",
+ " this is like a nop. */",
+ },
+
+ /* sh4a */
+ { "", "", "synco", "0000000010101011",
+ "/* Except for the effect on the pipeline - which is not simulated -",
+ " this is like a nop. */",
+ },
+
{ "n", "n", "rotcl <REG_N>", "0100nnnn00100100",
"ult = R[n] < 0;",
"R[n] = (R[n] << 1) | T;",
*************** op tab[] =
*** 898,903 ****
--- 1014,1031 ----
"Delay_Slot (PC + 2);",
},
+ /* sh4a */
+ { "", "", "setdmx", "0000000010011000",
+ "saved_state.asregs.cregs.named.sr |= SR_MASK_DMX;"
+ "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMY;"
+ },
+
+ /* sh4a */
+ { "", "", "setdmy", "0000000011001000",
+ "saved_state.asregs.cregs.named.sr |= SR_MASK_DMY;"
+ "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMX;"
+ },
+
/* sh-dsp */
{ "", "n", "setrc <REG_N>", "0100nnnn00010100",
"SET_RC (R[n]);",
*************** op tab[] =
*** 980,1010 ****
"R[n] = CREG (m);",
},
- #if 0
{ "n", "", "stc SGR,<REG_N>", "0000nnnn00111010",
! "R[n] = SGR;",
},
{ "n", "", "stc DBR,<REG_N>", "0000nnnn11111010",
! "R[n] = DBR;",
},
- #endif
{ "n", "n", "stc.l <CREG_M>,@-<REG_N>", "0100nnnnmmmm0011",
"MA (1);",
"R[n] -= 4;",
"WLAT (R[n], CREG (m));",
},
- #if 0
{ "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010",
! "MA (1);",
! "R[n] -= 4;",
! "WLAT (R[n], SGR);",
},
{ "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010",
! "MA (1);",
! "R[n] -= 4;",
! "WLAT (R[n], DBR);",
},
- #endif
{ "n", "", "sts <SREG_M>,<REG_N>", "0000nnnnssss1010",
"R[n] = SREG (m);",
--- 1108,1150 ----
"R[n] = CREG (m);",
},
{ "n", "", "stc SGR,<REG_N>", "0000nnnn00111010",
! "if (SR_MD)",
! " R[n] = SGR; /* priv mode */",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "", "stc DBR,<REG_N>", "0000nnnn11111010",
! "if (SR_MD)",
! " R[n] = DBR; /* priv mode */",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "n", "stc.l <CREG_M>,@-<REG_N>", "0100nnnnmmmm0011",
"MA (1);",
"R[n] -= 4;",
"WLAT (R[n], CREG (m));",
},
{ "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010",
! "if (SR_MD)",
! "{ /* priv mode */",
! " MA (1);",
! " R[n] -= 4;",
! " WLAT (R[n], SGR);",
! "}",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010",
! "if (SR_MD)",
! "{ /* priv mode */",
! " MA (1);",
! " R[n] -= 4;",
! " WLAT (R[n], DBR);",
! "}",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "", "sts <SREG_M>,<REG_N>", "0000nnnnssss1010",
"R[n] = SREG (m);",
*************** op movsxy_tab[] =
*** 1258,1313 ****
"WLAT (R[n], SEXT (DSP_R (m)));",
"R[n] += R[8];",
},
! { "", "n", "movx.w @<REG_x>,<DSP_XX>", "111100xxXX000100",
"DSP_R (m) = RSWAT (R[n]) << 16;",
! "iword &= 0xfd53; goto top;",
},
! { "n", "n", "movx.w @<REG_x>+,<DSP_XX>", "111100xxXX001000",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
! "iword &= 0xfd53; goto top;",
},
! { "n", "n8","movx.w @<REG_x>+REG_8,<DSP_XX>", "111100xxXX001100",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
! "iword &= 0xfd53; goto top;",
},
! { "", "n", "movx.w <DSP_Aa>,@<REG_x>", "111100xxaa100100",
"WWAT (R[n], DSP_R (m) >> 16);",
! "iword &= 0xfd53; goto top;",
},
! { "n", "n", "movx.w <DSP_Aa>,@<REG_x>+", "111100xxaa101000",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
! "iword &= 0xfd53; goto top;",
},
! { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101100",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
! "iword &= 0xfd53; goto top;",
},
! { "", "n", "movy.w @<REG_y>,<DSP_YY>", "111100yyYY000001",
"DSP_R (m) = RSWAT (R[n]) << 16;",
},
! { "n", "n", "movy.w @<REG_y>+,<DSP_YY>", "111100yyYY000010",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
! { "n", "n9","movy.w @<REG_y>+REG_9,<DSP_YY>", "111100yyYY000011",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
! { "", "n", "movy.w <DSP_Aa>,@<REG_y>", "111100yyAA010001",
"WWAT (R[n], DSP_R (m) >> 16);",
},
! { "n", "n", "movy.w <DSP_Aa>,@<REG_y>+", "111100yyAA010010",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
! { "n", "n9", "movy.w <DSP_Aa>,@<REG_y>+REG_9", "111100yyAA010011",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
{ "", "", "nopx nopy", "1111000000000000",
"/* nop */",
},
--- 1398,1515 ----
"WLAT (R[n], SEXT (DSP_R (m)));",
"R[n] += R[8];",
},
! { "", "n", "movx.w @<REG_xy>,<DSP_XY>", "111100xyXY0001??",
"DSP_R (m) = RSWAT (R[n]) << 16;",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "", "n", "movx.l @<REG_xy>,<DSP_XY>", "111100xyXY010100",
! "DSP_R (m) = RLAT (R[n]);",
},
! { "n", "n", "movx.w @<REG_xy>+,<DSP_XY>", "111100xyXY0010??",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "n", "n", "movx.l @<REG_xy>+,<DSP_XY>", "111100xyXY011000",
! "DSP_R (m) = RLAT (R[n]);",
! "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 4;",
},
! { "n", "n8","movx.w @<REG_xy>+REG_8,<DSP_XY>", "111100xyXY0011??",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "n", "n8","movx.l @<REG_xy>+REG_8,<DSP_XY>", "111100xyXY011100",
! "DSP_R (m) = RLAT (R[n]);",
! "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
},
! { "", "n", "movx.w <DSP_Ax>,@<REG_xy>", "111100xyax1001??",
"WWAT (R[n], DSP_R (m) >> 16);",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "", "n", "movx.l <DSP_Ax>,@<REG_xy>", "111100xyax110100",
! "WLAT (R[n], DSP_R (m));",
},
! { "n", "n", "movx.w <DSP_Ax>,@<REG_xy>+", "111100xyax1010??",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
},
! { "n", "n", "movx.l <DSP_Ax>,@<REG_xy>+", "111100xyax111000",
! "WLAT (R[n], DSP_R (m));",
! "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 4;",
! },
! { "n", "n8","movx.w <DSP_Ax>,@<REG_xy>+REG_8","111100xyax1011??",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "n", "n8","movx.l <DSP_Ax>,@<REG_xy>+REG_8","111100xyax111100",
! "WLAT (R[n], DSP_R (m));",
! "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
},
! { "", "n", "movy.w @<REG_yx>,<DSP_YX>", "111100yxYX000001",
"DSP_R (m) = RSWAT (R[n]) << 16;",
},
! { "n", "n", "movy.w @<REG_yx>+,<DSP_YX>", "111100yxYX000010",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
! { "n", "n9","movy.w @<REG_yx>+REG_9,<DSP_YX>", "111100yxYX000011",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
! { "", "n", "movy.w <DSP_Ay>,@<REG_yx>", "111100yxAY010001",
"WWAT (R[n], DSP_R (m) >> 16);",
},
! { "n", "n", "movy.w <DSP_Ay>,@<REG_yx>+", "111100yxAY010010",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
! { "n", "n9", "movy.w <DSP_Ay>,@<REG_yx>+REG_9", "111100yxAY010011",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
+ { "", "n", "movy.l @<REG_yx>,<DSP_YX>", "111100yxYX100001",
+ "DSP_R (m) = RLAT (R[n]);",
+ },
+ { "n", "n", "movy.l @<REG_yx>+,<DSP_YX>", "111100yxYX100010",
+ "DSP_R (m) = RLAT (R[n]);",
+ "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 4;",
+ },
+ { "n", "n9","movy.l @<REG_yx>+REG_9,<DSP_YX>", "111100yxYX100011",
+ "DSP_R (m) = RLAT (R[n]);",
+ "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
+ },
+ { "", "n", "movy.l <DSP_Ay>,@<REG_yx>", "111100yxAY110001",
+ "WLAT (R[n], DSP_R (m));",
+ },
+ { "n", "n", "movy.l <DSP_Ay>,@<REG_yx>+", "111100yxAY110010",
+ "WLAT (R[n], DSP_R (m));",
+ "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 4;",
+ },
+ { "n", "n9", "movy.l <DSP_Ay>,@<REG_yx>+REG_9", "111100yxAY110011",
+ "WLAT (R[n], DSP_R (m));",
+ "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
+ },
{ "", "", "nopx nopy", "1111000000000000",
"/* nop */",
},
*************** op ppi_tab[] =
*** 1379,1385 ****
"COMPUTE_OVERFLOW;",
"greater_equal = 0;",
},
! { "","", "pmuls Se,Sf,Dg", "0100eeffxxyygguu",
"res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
"if (res == 0x80000000)",
" res = 0x7fffffff;",
--- 1581,1587 ----
"COMPUTE_OVERFLOW;",
"greater_equal = 0;",
},
! { "","", "pmuls Se,Sf,Dg", "0100eeff0000gguu",
"res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
"if (res == 0x80000000)",
" res = 0x7fffffff;",
*************** op ppi_tab[] =
*** 1462,1468 ****
"DSR |= carry;\n",
"goto assign_z;\n",
},
! { "","", "pcmp Sx,Sy", "10000100xxyy....",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
"int Sy = DSP_R (y);",
--- 1664,1670 ----
"DSR |= carry;\n",
"goto assign_z;\n",
},
! { "","", "pcmp Sx,Sy", "10000100xxyyzzzz",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
"int Sy = DSP_R (y);",
*************** op ppi_tab[] =
*** 1479,1484 ****
--- 1681,1704 ----
},
{ "","", "pwad Sx,Sy,Dz", "10110100xxyyzzzz",
},
+ { "","", "(if cc) pabs Sx,Dz", "100010ccxx01zzzz",
+ "/* FIXME: duplicate code pabs. */",
+ "res = DSP_R (x);",
+ "res_grd = GET_DSP_GRD (x);",
+ "if (res >= 0)",
+ " carry = 0;",
+ "else",
+ " {",
+ " res = -res;",
+ " carry = (res != 0); /* The manual has a bug here. */",
+ " res_grd = -res_grd - carry;",
+ " }",
+ "COMPUTE_OVERFLOW;",
+ "/* ??? The re-computing of overflow after",
+ " saturation processing is specific to pabs. */",
+ "overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0;",
+ "ADD_SUB_GE;",
+ },
{ "","", "pabs Sx,Dz", "10001000xx..zzzz",
"res = DSP_R (x);",
"res_grd = GET_DSP_GRD (x);",
*************** op ppi_tab[] =
*** 1496,1501 ****
--- 1716,1733 ----
"overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0;",
"ADD_SUB_GE;",
},
+
+ { "","", "(if cc) prnd Sx,Dz", "100110ccxx01zzzz",
+ "/* FIXME: duplicate code prnd. */",
+ "int Sx = DSP_R (x);",
+ "int Sx_grd = GET_DSP_GRD (x);",
+ "",
+ "res = (Sx + 0x8000) & 0xffff0000;",
+ "carry = (unsigned) res < (unsigned) Sx;",
+ "res_grd = Sx_grd + carry;",
+ "COMPUTE_OVERFLOW;",
+ "ADD_SUB_GE;",
+ },
{ "","", "prnd Sx,Dz", "10011000xx..zzzz",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
*************** op ppi_tab[] =
*** 1506,1511 ****
--- 1738,1768 ----
"COMPUTE_OVERFLOW;",
"ADD_SUB_GE;",
},
+
+ { "","", "(if cc) pabs Sy,Dz", "101010cc01yyzzzz",
+ "/* FIXME: duplicate code pabs. */",
+ "res = DSP_R (y);",
+ "res_grd = 0;",
+ "overflow = 0;",
+ "greater_equal = DSR_MASK_G;",
+ "if (res >= 0)",
+ " carry = 0;",
+ "else",
+ " {",
+ " res = -res;",
+ " carry = 1;",
+ " if (res < 0)",
+ " {",
+ " if (S)",
+ " res = 0x7fffffff;",
+ " else",
+ " {",
+ " overflow = DSR_MASK_V;",
+ " greater_equal = 0;",
+ " }",
+ " }",
+ " }",
+ },
{ "","", "pabs Sy,Dz", "10101000..yyzzzz",
"res = DSP_R (y);",
"res_grd = 0;",
*************** op ppi_tab[] =
*** 1529,1534 ****
--- 1786,1802 ----
" }",
" }",
},
+ { "","", "(if cc) prnd Sy,Dz", "101110cc01yyzzzz",
+ "/* FIXME: duplicate code prnd. */",
+ "int Sy = DSP_R (y);",
+ "int Sy_grd = SIGN32 (Sy);",
+ "",
+ "res = (Sy + 0x8000) & 0xffff0000;",
+ "carry = (unsigned) res < (unsigned) Sy;",
+ "res_grd = Sy_grd + carry;",
+ "COMPUTE_OVERFLOW;",
+ "ADD_SUB_GE;",
+ },
{ "","", "prnd Sy,Dz", "10111000..yyzzzz",
"int Sy = DSP_R (y);",
"int Sy_grd = SIGN32 (Sy);",
*************** op ppi_tab[] =
*** 1609,1614 ****
--- 1877,1894 ----
"COMPUTE_OVERFLOW;",
"ADD_SUB_GE;",
},
+ { "","", "(if cc) psub Sy,Sx,Dz", "100001ccxxyyzzzz",
+ "int Sx = DSP_R (x);",
+ "int Sx_grd = GET_DSP_GRD (x);",
+ "int Sy = DSP_R (y);",
+ "int Sy_grd = SIGN32 (Sy);",
+ "",
+ "res = Sy - Sx;",
+ "carry = (unsigned) res > (unsigned) Sy;",
+ "res_grd = Sy_grd - Sx_grd - carry;",
+ "COMPUTE_OVERFLOW;",
+ "ADD_SUB_GE;",
+ },
{ "","", "(if cc) padd Sx,Sy,Dz", "101100ccxxyyzzzz",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
*************** op ppi_tab[] =
*** 1698,1703 ****
--- 1978,1998 ----
"overflow = 0;",
"greater_equal = 1;",
},
+ { "","", "pclr Du pmuls Se,Sf,Dg", "0100eeff0001gguu",
+ "/* Do multiply. */",
+ "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
+ "if (res == 0x80000000)",
+ " res = 0x7fffffff;",
+ "DSP_R (g) = res;",
+ "DSP_GRD (g) = SIGN32 (res);",
+ "/* FIXME: update DSR based on results of multiply! */",
+ "",
+ "/* Do clr. */",
+ "z = u;",
+ "res = 0;",
+ "res_grd = 0;",
+ "goto assign_z;",
+ },
{ "","", "(if cc) pdmsb Sx,Dz", "100111ccxx..zzzz",
"unsigned Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
*************** op ppi_tab[] =
*** 1813,1818 ****
--- 2108,2134 ----
" MACL = DSP_R (z) = res;",
"return;",
},
+ /* sh4a */
+ { "","", "(if cc) pswap Sx,Dz", "100111ccxx01zzzz",
+ "int Sx = DSP_R (x);",
+ "",
+ "res = ((Sx & 0xffff) * 65536) + ((Sx >> 16) & 0xffff);",
+ "res_grd = GET_DSP_GRD (x);",
+ "carry = 0;",
+ "overflow = 0;",
+ "greater_equal = res & 0x80000000 ? 0 : DSR_MASK_G;",
+ },
+ /* sh4a */
+ { "","", "(if cc) pswap Sy,Dz", "101111cc01yyzzzz",
+ "int Sy = DSP_R (y);",
+ "",
+ "res = ((Sy & 0xffff) * 65536) + ((Sy >> 16) & 0xffff);",
+ "res_grd = SIGN32 (Sy);",
+ "carry = 0;",
+ "overflow = 0;",
+ "greater_equal = res & 0x80000000 ? 0 : DSR_MASK_G;",
+ },
+
{0, 0}
};
*************** expand_opcode (val, i, s)
*** 1976,2001 ****
exit (1);
case '0':
case '1':
! /* Consume an arbitrary number of ones and zeros. */
! do {
! j = (j << 1) + (s[m++] - '0');
! } while (s[m] == '0' || s[m] == '1');
! expand_opcode ((val << m) | j, i, s + m);
! break;
!
case 'N': /* NN -- four-way fork */
for (j = 0; j < 4; j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
! case 'x': /* xx -- 2-way fork */
! /* Cross-breeding with movy moved to separate function. */
! for (j = 0; j < 4; j += 2)
expand_opcode ((val << 2) | j, i, s + 2);
break;
! case 'y': /* yy -- two-way fork */
! for (j = 0; j < 2; j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
case 'i': /* eg. "i8*1" */
case '.': /* "...." is a wildcard */
case 'n':
--- 2292,2323 ----
exit (1);
case '0':
case '1':
! /* Consume an arbitrary number of ones and zeros. */
! do {
! j = (j << 1) + (s[m++] - '0');
! } while (s[m] == '0' || s[m] == '1');
! expand_opcode ((val << m) | j, i, s + m);
! break;
case 'N': /* NN -- four-way fork */
for (j = 0; j < 4; j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
! case 'x': /* xx or xy -- two-way or four-way fork */
! for (j = 0; j < 4; j += (s[1] == 'x' ? 2 : 1))
expand_opcode ((val << 2) | j, i, s + 2);
break;
! case 'y': /* yy or yx -- two-way or four-way fork */
! for (j = 0; j < (s[1] == 'x' ? 4 : 2); j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
+ case '?': /* Seven-way "wildcard" fork for movxy */
+ expand_opcode ((val << 2), i, s + 2);
+ for (j = 1; j < 4; j++)
+ {
+ expand_opcode ((val << 2) | j, i, s + 2);
+ expand_opcode ((val << 2) | (j + 16), i, s + 2);
+ }
+ break;
case 'i': /* eg. "i8*1" */
case '.': /* "...." is a wildcard */
case 'n':
*************** expand_opcode (val, i, s)
*** 2033,2049 ****
expand_opcode ((val << 4) | j, i, s + 4);
break;
case 'X':
case 'a':
! /* XX, aa -- two-way fork */
! for (j = 0; j < 4; j += 2)
expand_opcode ((val << 2) | j, i, s + 2);
break;
case 'Y':
case 'A':
! /* YY, AA -- two-way fork */
! for (j = 0; j < 2; j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
}
}
}
--- 2355,2395 ----
expand_opcode ((val << 4) | j, i, s + 4);
break;
case 'X':
+ /* XX/XY -- 2/4 way fork. */
+ for (j = 0; j < 4; j += (s[1] == 'X' ? 2 : 1))
+ expand_opcode ((val << 2) | j, i, s + 2);
+ break;
case 'a':
! /* aa/ax -- 2/4 way fork. */
! for (j = 0; j < 4; j += (s[1] == 'a' ? 2 : 1))
expand_opcode ((val << 2) | j, i, s + 2);
break;
case 'Y':
+ /* YY/YX -- 2/4 way fork. */
+ for (j = 0; j < (s[1] == 'Y' ? 2 : 4); j += 1)
+ expand_opcode ((val << 2) | j, i, s + 2);
+ break;
case 'A':
! /* AA/AY: 2/4 way fork. */
! for (j = 0; j < (s[1] == 'A' ? 2 : 4); j += 1)
expand_opcode ((val << 2) | j, i, s + 2);
break;
+ case 'v':
+ /* vv(VV) -- 4(16) way fork. */
+ /* Vector register fv0/4/8/12. */
+ if (s[2] == 'V')
+ {
+ /* 2 vector registers. */
+ for (j = 0; j < 15; j++)
+ expand_opcode ((val << 4) | j, i, s + 4);
+ }
+ else
+ {
+ /* 1 vector register. */
+ for (j = 0; j < 4; j += 1)
+ expand_opcode ((val << 2) | j, i, s + 2);
+ }
+ break;
}
}
}
*************** expand_ppi_movxy ()
*** 2113,2136 ****
int i;
for (i = 0xf000; i < 0xf400; i++)
- if ((i & 3) == 0 && (i & 12) != 0 && table[i] != 0)
- {
- /* A movx insn, which needs to be filled out with the
- corresponding movy insns. This used to be done in
- expand_opcode. */
- int m, mv;
-
- for (m = 0; m < 32; m++)
- {
- /* Ignore illegal nopy */
- if ((m & 7) == 0 && m != 0)
- continue;
- mv = m & 3 | (m & 4) << 2 | (m & 8) << 3 | (m & 16) << 4;
- table [i | mv] = table [i];
- }
- }
-
- for (i = 0xf000; i < 0xf400; i++)
if (table[i])
table[i + 0x800] = table[0xf800];
}
--- 2459,2464 ----
*************** gensim_caselist (p)
*** 2161,2166 ****
--- 2489,2506 ----
*s);
exit (1);
break;
+ case '?':
+ /* Wildcard expansion, nothing to do here. */
+ s += 2;
+ break;
+ case 'v':
+ printf (" int v1 = ((iword >> 10) & 3) * 4;\n");
+ s += 2;
+ break;
+ case 'V':
+ printf (" int v2 = ((iword >> 8) & 3) * 4;\n");
+ s += 2;
+ break;
case '0':
case '1':
s += 2;
*************** gensim_caselist (p)
*** 2179,2190 ****
s += 2;
break;
case 'x':
! printf (" int n = ((iword >> 9) & 1) + 4;\n");
needn = 1;
s += 2;
break;
case 'y':
! printf (" int n = ((iword >> 8) & 1) + 6;\n");
needn = 1;
s += 2;
break;
--- 2519,2544 ----
s += 2;
break;
case 'x':
! if (s[1] == 'y') /* xy */
! {
! printf (" int n = (iword & 3) ? \n");
! printf (" ((iword >> 9) & 1) + 4 : \n");
! printf (" REG_xy ((iword >> 8) & 3);\n");
! }
! else
! printf (" int n = ((iword >> 9) & 1) + 4;\n");
needn = 1;
s += 2;
break;
case 'y':
! if (s[1] == 'x') /* yx */
! {
! printf (" int n = (iword & 0xc) ? \n");
! printf (" ((iword >> 8) & 1) + 6 : \n");
! printf (" REG_yx ((iword >> 8) & 3);\n");
! }
! else
! printf (" int n = ((iword >> 8) & 1) + 6;\n");
needn = 1;
s += 2;
break;
*************** gensim_caselist (p)
*** 2197,2215 ****
s += 4;
break;
case 'X':
! printf (" int m = ((iword >> 7) & 1) + 8;\n");
s += 2;
break;
case 'a':
! printf (" int m = 7 - ((iword >> 6) & 2);\n");
s += 2;
break;
case 'Y':
! printf (" int m = ((iword >> 6) & 1) + 10;\n");
s += 2;
break;
case 'A':
! printf (" int m = 7 - ((iword >> 5) & 2);\n");
s += 2;
break;
--- 2551,2597 ----
s += 4;
break;
case 'X':
! if (s[1] == 'Y') /* XY */
! {
! printf (" int m = (iword & 3) ? \n");
! printf (" ((iword >> 7) & 1) + 8 : \n");
! printf (" DSP_xy ((iword >> 6) & 3);\n");
! }
! else
! printf (" int m = ((iword >> 7) & 1) + 8;\n");
s += 2;
break;
case 'a':
! if (s[1] == 'x') /* ax */
! {
! printf (" int m = (iword & 3) ? \n");
! printf (" 7 - ((iword >> 6) & 2) : \n");
! printf (" DSP_ax ((iword >> 6) & 3);\n");
! }
! else
! printf (" int m = 7 - ((iword >> 6) & 2);\n");
s += 2;
break;
case 'Y':
! if (s[1] == 'X') /* YX */
! {
! printf (" int m = (iword & 0xc) ? \n");
! printf (" ((iword >> 6) & 1) + 10 : \n");
! printf (" DSP_yx ((iword >> 6) & 3);\n");
! }
! else
! printf (" int m = ((iword >> 6) & 1) + 10;\n");
s += 2;
break;
case 'A':
! if (s[1] == 'Y') /* AY */
! {
! printf (" int m = (iword & 0xc) ? \n");
! printf (" 7 - ((iword >> 5) & 2) : \n");
! printf (" DSP_ay ((iword >> 6) & 3);\n");
! }
! else
! printf (" int m = 7 - ((iword >> 5) & 2);\n");
s += 2;
break;
*************** static void
*** 2303,2308 ****
--- 2685,2702 ----
gensim ()
{
printf ("{\n");
+ printf ("/* REG_xy = [r4, r5, r0, r1]. */\n");
+ printf ("#define REG_xy(R) ((R)==0 ? 4 : (R)==2 ? 5 : (R)==1 ? 0 : 1)\n");
+ printf ("/* REG_yx = [r6, r7, r2, r3]. */\n");
+ printf ("#define REG_yx(R) ((R)==0 ? 6 : (R)==1 ? 7 : (R)==2 ? 2 : 3)\n");
+ printf ("/* DSP_ax = [a0, a1, x0, x1]. */\n");
+ printf ("#define DSP_ax(R) ((R)==0 ? 7 : (R)==2 ? 5 : (R)==1 ? 8 : 9)\n");
+ printf ("/* DSP_ay = [a0, a1, y0, y1]. */\n");
+ printf ("#define DSP_ay(R) ((R)==0 ? 7 : (R)==1 ? 5 : (R)==2 ? 10 : 11)\n");
+ printf ("/* DSP_xy = [x0, x1, y0, y1]. */\n");
+ printf ("#define DSP_xy(R) ((R)==0 ? 8 : (R)==2 ? 9 : (R)==1 ? 10 : 11)\n");
+ printf ("/* DSP_yx = [y0, y1, x0, x1]. */\n");
+ printf ("#define DSP_yx(R) ((R)==0 ? 10 : (R)==1 ? 11 : (R)==2 ? 8 : 9)\n");
printf (" switch (jump_table[iword]) {\n");
gensim_caselist (tab);
*************** gendefines ()
*** 2341,2347 ****
static int ppi_index;
/* Take a ppi code, expand all varying fields in it and fill all the
! right entries in 'table' with the opcode index. */
static void
expand_ppi_code (val, i, s)
--- 2735,2742 ----
static int ppi_index;
/* Take a ppi code, expand all varying fields in it and fill all the
! right entries in 'table' with the opcode index.
! NOTE: tail recursion optimization removed for simplicity. */
static void
expand_ppi_code (val, i, s)
*************** expand_ppi_code (val, i, s)
*** 2351,2396 ****
{
int j;
! for (;;)
{
! switch (s[0])
! {
! default:
! fprintf (stderr, "gencode/expand_ppi_code: Illegal char '%c'\n",
! s[0]);
! exit (2);
! break;
! /* The last eight bits are disregarded for the switch table. */
! case 'm':
! case 'x':
! case '.':
! table[val] = i;
! return;
! case '0':
! val += val;
! s++;
! break;
! case '1':
! val += val + 1;
! s++;
! break;
! case 'i':
! case 'e': case 'f':
! val += val;
! s++;
! expand_ppi_code (val, i, s);
! val++;
! break;
! case 'c':
! val <<= 2;
! s += 2;
! val++;
! expand_ppi_code (val, ppi_index++, s);
! val++;
! expand_ppi_code (val, i, s);
! val++;
! break;
! }
}
}
--- 2746,2785 ----
{
int j;
! switch (s[0])
{
! default:
! fprintf (stderr, "gencode/expand_ppi_code: Illegal char '%c'\n", s[0]);
! exit (2);
! break;
! case 'g':
! case 'z':
! /* The last four bits are disregarded for the switch table. */
! table[val] = i;
! return;
! case 'm':
! /* Four-bit expansion. */
! for (j = 0; j < 16; j++)
! expand_ppi_code ((val << 4) + j, i, s + 4);
! break;
! case '.':
! case '0':
! expand_ppi_code ((val << 1), i, s + 1);
! break;
! case '1':
! expand_ppi_code ((val << 1) + 1, i, s + 1);
! break;
! case 'i':
! case 'e': case 'f':
! case 'x': case 'y':
! expand_ppi_code ((val << 1), i, s + 1);
! expand_ppi_code ((val << 1) + 1, i, s + 1);
! break;
! case 'c':
! expand_ppi_code ((val << 2) + 1, ppi_index++, s + 2);
! expand_ppi_code ((val << 2) + 2, i, s + 2);
! expand_ppi_code ((val << 2) + 3, i, s + 2);
! break;
}
}
*************** ppi_gensim ()
*** 2442,2459 ****
printf ("ppi_insn (iword)\n");
printf (" int iword;\n");
printf ("{\n");
printf (" static char e_tab[] = { 8, 9, 10, 5};\n");
printf (" static char f_tab[] = {10, 11, 8, 5};\n");
printf (" static char x_tab[] = { 8, 9, 7, 5};\n");
printf (" static char y_tab[] = {10, 11, 12, 14};\n");
printf (" static char g_tab[] = {12, 14, 7, 5};\n");
printf (" static char u_tab[] = { 8, 10, 7, 5};\n");
printf ("\n");
printf (" int z;\n");
printf (" int res, res_grd;\n");
printf (" int carry, overflow, greater_equal;\n");
printf ("\n");
! printf (" switch (ppi_table[iword >> 8]) {\n");
for (; p->name; p++)
{
--- 2831,2854 ----
printf ("ppi_insn (iword)\n");
printf (" int iword;\n");
printf ("{\n");
+ printf (" /* 'ee' = [x0, x1, y0, a1] (FIXME [x0, x1, a1, m1]) */\n");
printf (" static char e_tab[] = { 8, 9, 10, 5};\n");
+ printf (" /* 'ff' = [y0, y1, x0, a1] (FIXME [y0, y1, a1, m1]) */\n");
printf (" static char f_tab[] = {10, 11, 8, 5};\n");
+ printf (" /* 'xx'(?) = [x0, x1, a0, a1] */\n");
printf (" static char x_tab[] = { 8, 9, 7, 5};\n");
+ printf (" /* 'yy'(?) = [y0, y1, m0, m1] */\n");
printf (" static char y_tab[] = {10, 11, 12, 14};\n");
+ printf (" /* 'gg' = [m0, m1, a0, a1] */\n");
printf (" static char g_tab[] = {12, 14, 7, 5};\n");
+ printf (" /* 'uu' = [x0, y0, a0, a1] (FIXME [m1, x1, a0, a1]) */\n");
printf (" static char u_tab[] = { 8, 10, 7, 5};\n");
printf ("\n");
printf (" int z;\n");
printf (" int res, res_grd;\n");
printf (" int carry, overflow, greater_equal;\n");
printf ("\n");
! printf (" switch (ppi_table[iword >> 4]) {\n");
for (; p->name; p++)
{
*************** main (ac, av)
*** 2614,2620 ****
memset (table, 0, sizeof table);
ppi_filltable ();
! dumptable ("ppi_table", 1 << 8, 0);
}
else if (strcmp (av[1], "-x") == 0)
{
--- 3009,3015 ----
memset (table, 0, sizeof table);
ppi_filltable ();
! dumptable ("ppi_table", 1 << 12, 0);
}
else if (strcmp (av[1], "-x") == 0)
{
Index: interp.c
===================================================================
RCS file: /cvs/src/src/sim/sh/interp.c,v
retrieving revision 1.12
diff -p -r1.12 interp.c
*** interp.c 3 Nov 2003 14:14:15 -0000 1.12
--- interp.c 7 Jan 2004 21:38:27 -0000
***************
*** 1,4 ****
! /* Simulator for the Hitachi SH architecture.
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
--- 1,4 ----
! /* Simulator for the Renesas (formerly Hitachi) SH architecture.
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
*************** typedef union
*** 120,125 ****
--- 120,128 ----
int re;
/* sh3 */
int bank[8];
+ int dbr; /* debug base register */
+ int sgr; /* saved gr15 */
+ int ldst; /* load/store flag (boolean) */
} named;
int i[16];
} cregs;
*************** static int target_dsp;
*** 167,176 ****
static int host_little_endian;
static char **prog_argv;
- #if 1
static int maskw = 0;
static int maskl = 0;
- #endif
static SIM_OPEN_KIND sim_kind;
static char *myname;
--- 170,177 ----
*************** static char *myname;
*** 189,196 ****
--- 190,199 ----
#define CREG(n) (saved_state.asregs.cregs.i[(n)])
#define GBR saved_state.asregs.cregs.named.gbr
#define VBR saved_state.asregs.cregs.named.vbr
+ #define DBR saved_state.asregs.cregs.named.dbr
#define SSR saved_state.asregs.cregs.named.ssr
#define SPC saved_state.asregs.cregs.named.spc
+ #define SGR saved_state.asregs.cregs.named.sgr
#define SREG(n) (saved_state.asregs.sregs.i[(n)])
#define MACH saved_state.asregs.sregs.named.mach
#define MACL saved_state.asregs.sregs.named.macl
*************** static char *myname;
*** 228,233 ****
--- 231,237 ----
#define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
#define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
#define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
+ #define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
#define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
#define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
*************** do { \
*** 249,254 ****
--- 253,259 ----
#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
#define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
+ #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
/* stc currently relies on being able to read SR without modifications. */
#define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
*************** macl (regs, memory, n, m)
*** 1411,1416 ****
--- 1416,1447 ----
MACH = mach;
}
+
+ /* GET_LOOP_BOUNDS {EXTENDED}
+ These two functions compute the actual starting and ending point
+ of the repeat loop, based on the RS and RE registers (repeat start,
+ repeat stop). The extended version is called for LDRC, and the
+ regular version is called for SETRC. The difference is that for
+ LDRC, the loop start and end instructions are literally the ones
+ pointed to by RS and RE -- for SETRC, they're not (see docs). */
+
+ static struct loop_bounds
+ get_loop_bounds_ext (rs, re, memory, mem_end, maskw, endianw)
+ int rs, re;
+ unsigned char *memory, *mem_end;
+ int maskw, endianw;
+ {
+ struct loop_bounds loop;
+
+ /* FIXME: should I verify RS < RE? */
+ loop.start = PT2H (RS); /* FIXME not using the params? */
+ loop.end = PT2H (RE & ~1); /* Ignore bit 0 of RE. */
+ SKIP_INSN (loop.end);
+ if (loop.end >= mem_end)
+ loop.end = PT2H (0);
+ return loop;
+ }
+
float
fsca_s (int in, double (*f) (double))
{
*************** init_dsp (abfd)
*** 1541,1547 ****
int was_dsp = target_dsp;
unsigned long mach = bfd_get_mach (abfd);
! if (mach == bfd_mach_sh_dsp || mach == bfd_mach_sh3_dsp)
{
int ram_area_size, xram_start, yram_start;
int new_select;
--- 1572,1580 ----
int was_dsp = target_dsp;
unsigned long mach = bfd_get_mach (abfd);
! if (mach == bfd_mach_sh_dsp ||
! mach == bfd_mach_sh4al_dsp ||
! mach == bfd_mach_sh3_dsp)
{
int ram_area_size, xram_start, yram_start;
int new_select;
*************** init_dsp (abfd)
*** 1556,1562 ****
xram_start = 0x0800f000;
ram_area_size = 0x1000;
}
! if (mach == bfd_mach_sh3_dsp)
{
/* SH7612:
8KB each for X & Y memory;
--- 1589,1595 ----
xram_start = 0x0800f000;
ram_area_size = 0x1000;
}
! if (mach == bfd_mach_sh3_dsp || mach == bfd_mach_sh4al_dsp)
{
/* SH7612:
8KB each for X & Y memory;
*************** sim_resume (sd, step, siggnal)
*** 1740,1746 ****
memory = saved_state.asregs.memory;
mem_end = memory + saved_state.asregs.msize;
! loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
insn_ptr = PT2H (saved_state.asregs.pc);
CHECK_INSN_PTR (insn_ptr);
--- 1773,1783 ----
memory = saved_state.asregs.memory;
mem_end = memory + saved_state.asregs.msize;
! if (RE & 1)
! loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);
! else
! loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
!
insn_ptr = PT2H (saved_state.asregs.pc);
CHECK_INSN_PTR (insn_ptr);
^ permalink raw reply [flat|nested] 14+ messages in thread
* [RFA] Add sh4a tests to sim/testsuite/sim/sh
2004-01-07 21:56 [RFA] Add sh4a to sh-sim (2nd iteration) Michael Snyder
@ 2004-01-07 22:04 ` Michael Snyder
2004-01-08 15:07 ` Joern Rennecke
2004-01-09 13:19 ` Joern Rennecke
2004-01-08 16:15 ` [RFA] Add sh4a to sh-sim (2nd iteration) Joern Rennecke
1 sibling, 2 replies; 14+ messages in thread
From: Michael Snyder @ 2004-01-07 22:04 UTC (permalink / raw)
To: joern.rennecke; +Cc: amylaar, andrew.stubbs, gdb-patches
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: newtests --]
[-- Type: text/plain, Size: 64714 bytes --]
2004-01-07 Michael Snyder <msnyder@redhat.com>
* dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s,
movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files.
* allinsn.exp: Add new tests.
* testutils.inc (set_sr_bit): Add argument.
(set_greg): Add .align directives.
Index: allinsn.exp
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/sh/allinsn.exp,v
retrieving revision 1.3
diff -p -r1.3 allinsn.exp
*** allinsn.exp 11 Aug 2003 19:36:23 -0000 1.3
--- allinsn.exp 7 Jan 2004 21:58:26 -0000
*************** set all "sh shdsp"
*** 4,9 ****
--- 4,10 ----
if [istarget sh-*elf] {
run_sim_test add.s $all
+ run_sim_test dmxy.s shdsp
run_sim_test fabs.s sh
run_sim_test fadd.s sh
run_sim_test fcmpeq.s sh
*************** if [istarget sh-*elf] {
*** 11,16 ****
--- 12,18 ----
run_sim_test fcnvds.s sh
run_sim_test fcnvsd.s sh
run_sim_test fdiv.s sh
+ run_sim_test fipr.s sh
run_sim_test fldi0.s sh
run_sim_test fldi1.s sh
run_sim_test flds.s sh
*************** if [istarget sh-*elf] {
*** 19,42 ****
--- 21,55 ----
run_sim_test fmov.s sh
run_sim_test fmul.s sh
run_sim_test fneg.s sh
+ run_sim_test fpchg.s sh
run_sim_test frchg.s sh
run_sim_test fschg.s sh
run_sim_test fsqrt.s sh
run_sim_test fsub.s sh
run_sim_test ftrc.s sh
+ run_sim_test ldrc.s shdsp
+ run_sim_test loop.s shdsp
run_sim_test macl.s sh
run_sim_test macw.s sh
+ run_sim_test movli.s $all
+ run_sim_test movua.s $all
+ run_sim_test movxy.s shdsp
+ run_sim_test pabs.s shdsp
run_sim_test paddc.s shdsp
run_sim_test padd.s shdsp
run_sim_test pand.s shdsp
+ run_sim_test pclr.s shdsp
run_sim_test pdec.s shdsp
run_sim_test pdmsb.s shdsp
run_sim_test pinc.s shdsp
run_sim_test pmuls.s shdsp
+ run_sim_test prnd.s shdsp
run_sim_test pshai.s shdsp
run_sim_test pshar.s shdsp
run_sim_test pshli.s shdsp
run_sim_test pshlr.s shdsp
+ run_sim_test psub.s shdsp
+ run_sim_test pswap.s shdsp
run_sim_test shll.s $all
run_sim_test shll2.s $all
run_sim_test shll8.s $all
Index: dmxy.s
===================================================================
RCS file: dmxy.s
diff -N dmxy.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- dmxy.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,21 ----
+ # sh testcase for setdmx, setdmy, clrdmxy
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ set_grs_a5a5
+ setdmx
+ test_sr_bit_set 0x400
+ test_sr_bit_clear 0x800
+ setdmy
+ test_sr_bit_clear 0x400
+ test_sr_bit_set 0x800
+ clrdmxy
+ test_sr_bit_clear 0x400
+ test_sr_bit_clear 0x800
+
+ test_grs_a5a5
+ pass
+ exit 0
Index: fipr.s
===================================================================
RCS file: fipr.s
diff -N fipr.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- fipr.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,138 ----
+ # sh testcase for fipr $fvm, $fvn
+ # mach: sh
+ # as(sh): -defsym sim_cpu=0
+
+ .include "testutils.inc"
+
+ start
+ initv0:
+ set_grs_a5a5
+ set_fprs_a5a5
+ # Load 1 into fr0.
+ fldi1 fr0
+ # Load 2 into fr1.
+ fldi1 fr1
+ fadd fr1, fr1
+ # Load 4 into fr2.
+ fldi1 fr2
+ fadd fr2, fr2
+ fadd fr2, fr2
+ # Load 8 into fr3.
+ fmov fr2, fr3
+ fadd fr2, fr3
+
+ initv8:
+ fldi1 fr8
+ fldi0 fr9
+ fldi1 fr10
+ fldi0 fr11
+
+ fipr fv0, fv8
+ test1:
+ # Result will be in fr11.
+ assert_fpreg_i 1, fr0
+ assert_fpreg_i 2, fr1
+ assert_fpreg_i 4, fr2
+ assert_fpreg_i 8, fr3
+ assert_fpreg_x 0xa5a5a5a5, fr4
+ assert_fpreg_x 0xa5a5a5a5, fr5
+ assert_fpreg_x 0xa5a5a5a5, fr6
+ assert_fpreg_x 0xa5a5a5a5, fr7
+ assert_fpreg_i 1, fr8
+ assert_fpreg_i 0, fr9
+ assert_fpreg_i 1, fr10
+ assert_fpreg_i 5, fr11
+ assert_fpreg_x 0xa5a5a5a5, fr12
+ assert_fpreg_x 0xa5a5a5a5, fr13
+ assert_fpreg_x 0xa5a5a5a5, fr14
+ assert_fpreg_x 0xa5a5a5a5, fr15
+
+ test_grs_a5a5
+ test_infp:
+ # Test positive infinity
+ fldi0 fr11
+ mov.l infp, r0
+ lds r0, fpul
+ fsts fpul, fr0
+ fipr fv0, fv8
+ # fr11 should be plus infinity
+ assert_fpreg_x 0x7f800000, fr11
+ test_infm:
+ # Test negitive infinity
+ fldi0 fr11
+ mov.l infm, r0
+ lds r0, fpul
+ fsts fpul, fr0
+ fipr fv0, fv8
+ # fr11 should be plus infinity
+ assert_fpreg_x 0xff800000, fr11
+ test_qnanp:
+ # Test positive qnan
+ fldi0 fr11
+ mov.l qnanp, r0
+ lds r0, fpul
+ fsts fpul, fr0
+ fipr fv0, fv8
+ # fr11 should be plus qnan (or greater)
+ flds fr11, fpul
+ sts fpul, r1
+ cmp/ge r0, r1
+ bt .L0
+ fail
+ .L0:
+ test_snanp:
+ # Test positive snan
+ fldi0 fr11
+ mov.l snanp, r0
+ lds r0, fpul
+ fsts fpul, fr0
+ fipr fv0, fv8
+ # fr11 should be plus snan (or greater)
+ flds fr11, fpul
+ sts fpul, r1
+ cmp/ge r0, r1
+ bt .L1
+ fail
+ .L1:
+ .if 0
+ # FIXME I'm not sure if cmp is signed or unsigned.
+ # This seems wrong.
+ test_qnanm:
+ # Test negantive qnan
+ fldi0 fr11
+ mov.l qnanm, r0
+ lds r0, fpul
+ fsts fpul, fr0
+ fipr fv0, fv8
+ # fr11 should be minus qnan (or less)
+ flds fr11, fpul
+ sts fpul, r1
+ cmp/ge r1, r0
+ bt .L2
+ fail
+ .L2:
+ test_snanm:
+ # Test negative snan
+ fldi0 fr11
+ mov.l snanm, r0
+ lds r0, fpul
+ fsts fpul, fr0
+ fipr fv0, fv8
+ # fr11 should be minus snan (or less)
+ flds fr11, fpul
+ sts fpul, r1
+ cmp/ge r1, r0
+ bt .L3
+ fail
+ .L3
+ .endif
+ pass
+ exit 0
+
+ .align 2
+ qnanp: .long 0x7f800001
+ qnanm: .long 0xff800001
+ snanp: .long 0x7fc00000
+ snanm: .long 0xffc00000
+ infp: .long 0x7f800000
+ infm: .long 0xff800000
Index: fpchg.s
===================================================================
RCS file: fpchg.s
diff -N fpchg.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- fpchg.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,30 ----
+ # sh testcase for fpchg
+ # mach: sh
+ # as(sh): -defsym sim_cpu=0
+
+ .include "testutils.inc"
+
+ start
+ set_grs_a5a5
+ set_fprs_a5a5
+ sts fpscr, r0
+ assertreg0 0
+ fpchg
+ sts fpscr, r0
+ assertreg0 0x80000
+ fpchg
+ sts fpscr, r0
+ assertreg0 0
+ fpchg
+ sts fpscr, r0
+ assertreg0 0x80000
+ fpchg
+ sts fpscr, r0
+ assertreg0 0
+
+ set_greg 0xa5a5a5a5, r0
+ test_grs_a5a5
+ test_fprs_a5a5
+
+ pass
+ exit 0
Index: ldrc.s
===================================================================
RCS file: ldrc.s
diff -N ldrc.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- ldrc.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,118 ----
+ # sh testcase for ldrc, strc
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+
+ setrc_imm:
+ set_grs_a5a5
+ # Test setrc
+ #
+ ldrs lstart
+ ldre lend
+ setrc #0xff
+ get_sr r1
+ shlr16 r1
+ set_greg 0xfff, r0
+ and r0, r1
+ assertreg 0xff, r1
+
+ stc rs, r0 ! rs unchanged
+ assertreg0 lstart
+ stc re, r0 ! re unchanged
+ assertreg0 lend
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+
+ test_grs_a5a5
+
+ setrc_reg:
+ set_grs_a5a5
+ # Test setrc
+ #
+ ldrs lstart
+ ldre lend
+ set_greg 0xfff, r0
+ setrc r0
+ get_sr r1
+ shlr16 r1
+ set_greg 0xfff, r0
+ and r0, r1
+ assertreg 0xfff, r1
+
+ stc rs, r0 ! rs unchanged
+ assertreg0 lstart
+ stc re, r0 ! re unchanged
+ assertreg0 lend
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+
+ test_grs_a5a5
+
+ bra ldrc_imm
+
+ .global lstart
+ .align 2
+ lstart: nop
+ nop
+ nop
+ nop
+ .global lend
+ .align 2
+ lend: nop
+ nop
+ nop
+ nop
+
+ ldrc_imm:
+ set_grs_a5a5
+ # Test ldrc
+ setrc #0x0 ! zero rc
+ ldrc #0xa5
+ get_sr r1
+ shlr16 r1
+ set_greg 0xfff, r0
+ and r0, r1
+ assertreg 0xa5, r1
+ stc rs, r0 ! rs unchanged
+ assertreg0 lstart
+ stc re, r0
+ assertreg0 lend+1 ! bit 0 set in re
+
+ # fix up re for next test
+ dt r0 ! Ugh! No DEC insn!
+ ldc r0, re
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+
+ test_grs_a5a5
+
+ ldrc_reg:
+ set_grs_a5a5
+ # Test ldrc
+ setrc #0x0 ! zero rc
+ set_greg 0xa5a, r0
+ ldrc r0
+ get_sr r1
+ shlr16 r1
+ set_greg 0xfff, r0
+ and r0, r1
+ assertreg 0xa5a, r1
+ stc rs, r0 ! rs unchanged
+ assertreg0 lstart
+ stc re, r0
+ assertreg0 lend+1 ! bit 0 set in re
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+
+ test_grs_a5a5
+
+ pass
+ exit 0
+
Index: loop.s
===================================================================
RCS file: loop.s
diff -N loop.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- loop.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,311 ----
+ # sh testcase for loop control
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ loop1:
+ set_grs_a5a5
+
+ ldrs Loop1_start0+8
+ ldre Loop1_start0+4
+ setrc #5
+ Loop1_start0:
+ add #1, r1 ! Before loop
+ # Loop should execute one instruction five times.
+ Loop1_begin:
+ add #1, r1 ! Within loop
+ Loop1_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
+ assertreg 0xa5a5a5a5+8, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop2:
+ set_grs_a5a5
+
+ ldrs Loop2_start0+6
+ ldre Loop2_start0+4
+ setrc #5
+ Loop2_start0:
+ add #1, r1 ! Before loop
+ # Loop should execute two instructions five times.
+ Loop2_begin:
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ Loop2_end:
+ add #3, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before)
+ assertreg 0xa5a5a5a5+14, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop3:
+ set_grs_a5a5
+
+ ldrs Loop3_start0+4
+ ldre Loop3_start0+4
+ setrc #5
+ Loop3_start0:
+ add #1, r1 ! Before loop
+ # Loop should execute three instructions five times.
+ Loop3_begin:
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ Loop3_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
+ assertreg 0xa5a5a5a5+18, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop4:
+ set_grs_a5a5
+
+ ldrs Loop4_begin
+ ldre Loop4_last3+4
+ setrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute four instructions five times.
+ Loop4_begin:
+ Loop4_last3:
+ add #1, r1 ! Within loop
+ Loop4_last2:
+ add #1, r1 ! Within loop
+ Loop4_last1:
+ add #1, r1 ! Within loop
+ Loop4_last:
+ add #1, r1 ! Within loop
+ Loop4_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before)
+ assertreg 0xa5a5a5a5+23, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop5:
+ set_grs_a5a5
+
+ ldrs Loop5_begin
+ ldre Loop5_last3+4
+ setrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute five instructions five times.
+ Loop5_begin:
+ add #1, r1 ! Within loop
+ Loop5_last3:
+ add #1, r1 ! Within loop
+ Loop5_last2:
+ add #1, r1 ! Within loop
+ Loop5_last1:
+ add #1, r1 ! Within loop
+ Loop5_last:
+ add #1, r1 ! Within loop
+ Loop5_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before)
+ assertreg 0xa5a5a5a5+28, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loopn:
+ set_grs_a5a5
+
+ ldrs Loopn_begin
+ ldre Loopn_last3+4
+ setrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute n instructions five times.
+ Loopn_begin:
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ Loopn_last3:
+ add #1, r1 ! Within loop
+ Loopn_last2:
+ add #1, r1 ! Within loop
+ Loopn_last1:
+ add #1, r1 ! Within loop
+ Loopn_last:
+ add #1, r1 ! Within loop
+ Loopn_end:
+ add #3, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before)
+ assertreg 0xa5a5a5a5+64, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop1e:
+ set_grs_a5a5
+
+ ldrs Loop1e_begin
+ ldre Loop1e_last
+ ldrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute one instruction five times.
+ Loop1e_begin:
+ Loop1e_last:
+ add #1, r1 ! Within loop
+ Loop1e_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
+ assertreg 0xa5a5a5a5+8, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop2e:
+ set_grs_a5a5
+
+ ldrs Loop2e_begin
+ ldre Loop2e_last
+ ldrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute two instructions five times.
+ Loop2e_begin:
+ add #1, r1 ! Within loop
+ Loop2e_last:
+ add #1, r1 ! Within loop
+ Loop2e_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before)
+ assertreg 0xa5a5a5a5+13, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop3e:
+ set_grs_a5a5
+
+ ldrs Loop3e_begin
+ ldre Loop3e_last
+ ldrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute three instructions five times.
+ Loop3e_begin:
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ Loop3e_last:
+ add #1, r1 ! Within loop
+ Loop3e_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
+ assertreg 0xa5a5a5a5+18, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop4e:
+ set_grs_a5a5
+
+ ldrs Loop4e_begin
+ ldre Loop4e_last
+ ldrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute four instructions five times.
+ Loop4e_begin:
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ Loop4e_last:
+ add #1, r1 ! Within loop
+ Loop4e_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before)
+ assertreg 0xa5a5a5a5+23, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop5e:
+ set_grs_a5a5
+
+ ldrs Loop5e_begin
+ ldre Loop5e_last
+ ldrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute five instructions five times.
+ Loop5e_begin:
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ Loop5e_last:
+ add #1, r1 ! Within loop
+ Loop5e_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before)
+ assertreg 0xa5a5a5a5+28, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ loop_n_e:
+ set_grs_a5a5
+
+ ldrs Loop_n_e_begin
+ ldre Loop_n_e_last
+ ldrc #5
+ add #1, r1 ! Before loop
+ # Loop should execute n instructions five times.
+ Loop_n_e_begin:
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ add #1, r1 ! Within loop
+ Loop_n_e_last:
+ add #1, r1 ! Within loop
+ Loop_n_e_end:
+ add #2, r1 ! After loop
+
+ # r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before)
+ assertreg 0xa5a5a5a5+48, r1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+
+ pass
+
+ exit 0
+
Index: movli.s
===================================================================
RCS file: movli.s
diff -N movli.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- movli.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,55 ----
+ # sh testcase for movli
+ # mach: all
+ # as(sh): -defsym sim_cpu=0
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ .align 2
+ x: .long 1
+ y: .long 2
+ z: .long 3
+
+ start
+ set_grs_a5a5
+ mov.l xptr, r1
+ mov.l yptr, r2
+ # Move linked/conditional, x to y
+ movli.l @r1, r0
+ movco.l r0, @r2
+
+ # Check result.
+ assertreg0 1
+ mov.l yptr, r1
+ mov.l @r1, r2
+ assertreg 1, r2
+
+ # Now attempt an unlinked move of r0 to z
+ mov.l zptr, r1
+ movco.l r0, @r1
+
+ # Check that z is unchanged.
+ mov.l zptr, r1
+ mov.l @r1, r2
+ assertreg 3, r2
+
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ pass
+ exit 0
+
+ .align 2
+ xptr: .long x
+ yptr: .long y
+ zptr: .long z
Index: movua.s
===================================================================
RCS file: movua.s
diff -N movua.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- movua.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,129 ----
+ # sh testcase for movua
+ # mach: all
+ # as(sh): -defsym sim_cpu=0
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ movua_1:
+ set_grs_a5a5
+ mov.l srcp, r1
+ movua.l @r1, r0
+ assertreg0 0x00010203
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x01020304
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x02030405
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x03040506
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x04050607
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x05060708
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x06070809
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x0708090a
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x08090a0b
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x090a0b0c
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x0a0b0c0d
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x0b0c0d0e
+
+ add #1, r1
+ movua.l @r1, r0
+ assertreg0 0x0c0d0e0f
+
+ assertreg src+12, r1
+ test_gr_a5a5 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ bra movua_4:
+ nop
+
+ .align 0
+ src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ .align 2
+ srcp: .long src
+
+ movua_4:
+ set_grs_a5a5
+ mov.l srcp2, r1
+ movua.l @r1+, r0
+ assertreg0 0x00010203
+ assertreg src+4, r1
+
+ mov.l srcp2, r1
+ add #1, r1
+ movua.l @r1+, r0
+ assertreg0 0x01020304
+ assertreg src+5, r1
+
+ mov.l srcp2, r1
+ add #2, r1
+ movua.l @r1+, r0
+ assertreg0 0x02030405
+ assertreg src+6, r1
+
+ mov.l srcp2, r1
+ add #3, r1
+ movua.l @r1+, r0
+ assertreg0 0x03040506
+ assertreg src+7, r1
+
+ test_gr_a5a5 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ pass
+ exit 0
+
+ srcp2: .long src
+
Index: movxy.s
===================================================================
RCS file: movxy.s
diff -N movxy.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- movxy.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,1186 ----
+ # sh testcase for movxy
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ .align 2
+ src1: .word 1
+ src2: .word 2
+ src3: .word 3
+ src4: .word 4
+ src5: .word 5
+ src6: .word 6
+ src7: .word 7
+ src8: .word 8
+ src9: .word 9
+ .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+
+ dst1: .word 0
+ dst2: .word 0
+ dst3: .word 0
+ dst4: .word 0
+ dst5: .word 0
+ dst6: .word 0
+ dst7: .word 0
+ dst8: .word 0
+ dst9: .word 0
+ .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+
+ start
+ movxw_nopy:
+ set_grs_a5a5
+ # load up pointers
+ mov.l srcp1, r4
+ mov.l dstp1, r5
+
+ # perform moves
+ movx.w @r4, x0
+ pcopy x0, a0
+ movx.w a0, @r5
+
+ # verify pointers unchanged
+ mov.l srcp1, r0
+ cmp/eq r0, r4
+ bt .L0
+ fail
+ .L0:
+ mov.l dstp1, r1
+ cmp/eq r1, r5
+ bt .L1
+ fail
+ .L1:
+ # verify copied values
+ mov.w @r0, r0
+ mov.w @r1, r1
+ cmp/eq r0, r1
+ bt .L2
+ fail
+ .L2:
+ test_gr_a5a5 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ movyw_nopx:
+ set_grs_a5a5
+ # load up pointers
+ mov.l srcp2, r6
+ mov.l dstp2, r7
+
+ # perform moves
+ movy.w @r6, y0
+ pcopy y0, a0
+ movy.w a0, @r7
+
+ # verify pointers unchanged
+ mov.l srcp2, r2
+ cmp/eq r2, r6
+ bt .L3
+ fail
+ .L3:
+ mov.l dstp2, r3
+ cmp/eq r3, r7
+ bt .L4
+ fail
+ .L4:
+ # verify copied values
+ mov.w @r2, r2
+ mov.w @r3, r3
+ cmp/eq r2, r3
+ bt .L5
+ fail
+ .L5:
+ test_gr_a5a5 r0
+ test_gr_a5a5 r1
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ movxw_movyw:
+ set_grs_a5a5
+ # load up pointers
+ mov.l srcp3, r4
+ mov.l dstp3, r5
+ mov.l srcp4, r6
+ mov.l dstp4, r7
+
+ # perform moves
+ movx.w @r4, x1 movy.w @r6, y1
+ pcopy x1, a0
+ pcopy y1, a1
+ movx.w a0, @r5 movy.w a1, @r7
+
+ # verify pointers unchanged
+ mov.l srcp3, r0
+ cmp/eq r0, r4
+ bt .L6
+ fail
+ .L6:
+ mov.l dstp3, r1
+ cmp/eq r1, r5
+ bt .L7
+ fail
+ .L7:
+ mov.l srcp4, r2
+ cmp/eq r2, r6
+ bt .L8
+ fail
+ .L8:
+ mov.l dstp4, r3
+ cmp/eq r3, r7
+ bt .L9
+ fail
+ .L9:
+ # verify copied values
+ mov.w @r0, r0
+ mov.w @r1, r1
+ cmp/eq r0, r1
+ bt .L10
+ fail
+ .L10:
+ mov.w @r2, r2
+ mov.w @r3, r3
+ cmp/eq r2, r3
+ bt .L11
+ fail
+ .L11:
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ bra movxw_movyw_new
+ nop
+
+ .align 2
+ srcp1: .long src1
+ srcp2: .long src2
+ srcp3: .long src3
+ srcp4: .long src4
+ srcp5: .long src5
+ srcp6: .long src6
+ srcp7: .long src7
+ srcp8: .long src8
+ srcp9: .long src9
+
+ dstp1: .long dst1
+ dstp2: .long dst2
+ dstp3: .long dst3
+ dstp4: .long dst4
+ dstp5: .long dst5
+ dstp6: .long dst6
+ dstp7: .long dst7
+ dstp8: .long dst8
+ dstp9: .long dst9
+
+ movxw_movyw_new:
+ set_grs_a5a5
+ # load up pointers
+ mov.l srcp5b, r0
+ mov.l dstp5b, r1
+ mov.l srcp6b, r2
+ mov.l dstp6b, r3
+
+ # perform moves
+ movx.w @r0, x1
+ movy.w @r2, y1
+ movx.w x1, @r1
+ movy.w y1, @r3
+
+ # verify pointers unchanged
+ mov.l srcp5b, r4
+ cmp/eq r0, r4
+ bt .L12
+ fail
+
+ .L12:
+ mov.l dstp5b, r5
+ cmp/eq r1, r5
+ bt .L13
+ fail
+ .L13:
+ mov.l srcp6b, r6
+ cmp/eq r2, r6
+ bt .L14
+ fail
+ .L14:
+ mov.l dstp6b, r7
+ cmp/eq r3, r7
+ bt .L15
+ fail
+ .L15:
+ # verify copied values
+ mov.w @r0, r0
+ mov.w @r1, r1
+ cmp/eq r0, r1
+ bt .L16
+ fail
+ .L16:
+ mov.w @r2, r2
+ mov.w @r3, r3
+ cmp/eq r2, r3
+ bt .L17
+ fail
+ .L17:
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ mov.l srcp1b, r0
+ mov.l dstp1b, r1
+ mov.l srcp2b, r2
+ mov.l dstp2b, r3
+ mov.l srcp1b, r4
+ mov.l dstp1b, r5
+ mov.l srcp2b, r6
+ mov.l dstp2b, r7
+ mov #4, r8
+ mov #4, r9
+ bra .L18
+ nop
+
+ .align 2
+ srcp1b: .long src1
+ srcp2b: .long src2
+ srcp3b: .long src3
+ srcp4b: .long src4
+ srcp5b: .long src5
+ srcp6b: .long src6
+ srcp7b: .long src7
+ srcp8b: .long src8
+ srcp9b: .long src9
+
+ dstp1b: .long dst1
+ dstp2b: .long dst2
+ dstp3b: .long dst3
+ dstp4b: .long dst4
+ dstp5b: .long dst5
+ dstp6b: .long dst6
+ dstp7b: .long dst7
+ dstp8b: .long dst8
+ dstp9b: .long dst9
+
+ .L18:
+
+ # movx.w @Ax{}, Dx | nopy
+ movxwaxdx_nopy:
+ movx.w @r4,x0 ! .word 0xf004
+ movx.w @r4,x1 ! .word 0xf084
+ movx.w @r5,x0 ! .word 0xf204
+ movx.w @r5,x1 ! .word 0xf284
+ movx.w @r4+,x0 ! .word 0xf008
+ movx.w @r4+,x1 ! .word 0xf088
+ movx.w @r5+,x0 ! .word 0xf208
+ movx.w @r5+,x1 ! .word 0xf288
+ movx.w @r4+r8,x0 ! .word 0xf00c
+ movx.w @r4+r8,x1 ! .word 0xf08c
+ movx.w @r5+r8,x0 ! .word 0xf20c
+ movx.w @r5+r8,x1 ! .word 0xf28c
+ # movx.w Da, @Ax{} | nopy
+ movxwdaax_nopy:
+ movx.w a0,@r4 ! .word 0xf024
+ movx.w a1,@r4 ! .word 0xf0a4
+ movx.w a0,@r5 ! .word 0xf224
+ movx.w a1,@r5 ! .word 0xf2a4
+ movx.w a0,@r4+ ! .word 0xf028
+ movx.w a1,@r4+ ! .word 0xf0a8
+ movx.w a0,@r5+ ! .word 0xf228
+ movx.w a1,@r5+ ! .word 0xf2a8
+ movx.w a0,@r4+r8 ! .word 0xf02c
+ movx.w a1,@r4+r8 ! .word 0xf0ac
+ movx.w a0,@r5+r8 ! .word 0xf22c
+ movx.w a1,@r5+r8 ! .word 0xf2ac
+ # movy.w @Ay{}, Dy | nopx
+ movywaydy_nopx:
+ movy.w @r6,y0 ! .word 0xf001
+ movy.w @r6,y1 ! .word 0xf041
+ movy.w @r7,y0 ! .word 0xf101
+ movy.w @r7,y1 ! .word 0xf141
+ movy.w @r6+,y0 ! .word 0xf002
+ movy.w @r6+,y1 ! .word 0xf042
+ movy.w @r7+,y0 ! .word 0xf102
+ movy.w @r7+,y1 ! .word 0xf142
+ movy.w @r6+r9,y0 ! .word 0xf003
+ movy.w @r6+r9,y1 ! .word 0xf043
+ movy.w @r7+r9,y0 ! .word 0xf103
+ movy.w @r7+r9,y1 ! .word 0xf143
+ # movy.w Da, @Ay{} | nopx
+ movywdaay_nopx:
+ movy.w a0,@r6 ! .word 0xf011
+ movy.w a1,@r6 ! .word 0xf051
+ movy.w a0,@r7 ! .word 0xf111
+ movy.w a1,@r7 ! .word 0xf151
+ movy.w a0,@r6+ ! .word 0xf012
+ movy.w a1,@r6+ ! .word 0xf052
+ movy.w a0,@r7+ ! .word 0xf112
+ movy.w a1,@r7+ ! .word 0xf152
+ movy.w a0,@r6+r9 ! .word 0xf013
+ movy.w a1,@r6+r9 ! .word 0xf053
+ movy.w a0,@r7+r9 ! .word 0xf113
+ movy.w a1,@r7+r9 ! .word 0xf153
+ # movx {} || movy {}
+ movx_movy:
+ movx.w @r4,x0 movy.w @r6,y0 ! .word 0xf005
+ movx.w @r4,x0 movy.w @r6,y1 ! .word 0xf045
+ movx.w @r4,x1 movy.w @r6,y0 ! .word 0xf085
+ movx.w @r4,x1 movy.w @r6,y1 ! .word 0xf0c5
+ movx.w @r4,x0 movy.w @r7,y0 ! .word 0xf105
+ movx.w @r4,x0 movy.w @r7,y1 ! .word 0xf145
+ movx.w @r4,x1 movy.w @r7,y0 ! .word 0xf185
+ movx.w @r4,x1 movy.w @r7,y1 ! .word 0xf1c5
+ movx.w @r5,x0 movy.w @r6,y0 ! .word 0xf205
+ movx.w @r5,x0 movy.w @r6,y1 ! .word 0xf245
+ movx.w @r5,x1 movy.w @r6,y0 ! .word 0xf285
+ movx.w @r5,x1 movy.w @r6,y1 ! .word 0xf2c5
+ movx.w @r5,x0 movy.w @r7,y0 ! .word 0xf305
+ movx.w @r5,x0 movy.w @r7,y1 ! .word 0xf345
+ movx.w @r5,x1 movy.w @r7,y0 ! .word 0xf385
+ movx.w @r5,x1 movy.w @r7,y1 ! .word 0xf3c5
+ movx.w @r4,x0 movy.w @r6+,y0 ! .word 0xf006
+ movx.w @r4,x0 movy.w @r6+,y1 ! .word 0xf046
+ movx.w @r4,x1 movy.w @r6+,y0 ! .word 0xf086
+ movx.w @r4,x1 movy.w @r6+,y1 ! .word 0xf0c6
+ movx.w @r4,x0 movy.w @r7+,y0 ! .word 0xf106
+ movx.w @r4,x0 movy.w @r7+,y1 ! .word 0xf146
+ movx.w @r4,x1 movy.w @r7+,y0 ! .word 0xf186
+ movx.w @r4,x1 movy.w @r7+,y1 ! .word 0xf1c6
+ movx.w @r5,x0 movy.w @r6+,y0 ! .word 0xf206
+ movx.w @r5,x0 movy.w @r6+,y1 ! .word 0xf246
+ movx.w @r5,x1 movy.w @r6+,y0 ! .word 0xf286
+ movx.w @r5,x1 movy.w @r6+,y1 ! .word 0xf2c6
+ movx.w @r5,x0 movy.w @r7+,y0 ! .word 0xf306
+ movx.w @r5,x0 movy.w @r7+,y1 ! .word 0xf346
+ movx.w @r5,x1 movy.w @r7+,y0 ! .word 0xf386
+ movx.w @r5,x1 movy.w @r7+,y1 ! .word 0xf3c6
+ movx.w @r4,x0 movy.w @r6+r9,y0 ! .word 0xf007
+ movx.w @r4,x0 movy.w @r6+r9,y1 ! .word 0xf047
+ movx.w @r4,x1 movy.w @r6+r9,y0 ! .word 0xf087
+ movx.w @r4,x1 movy.w @r6+r9,y1 ! .word 0xf0c7
+ movx.w @r4,x0 movy.w @r7+r9,y0 ! .word 0xf107
+ movx.w @r4,x0 movy.w @r7+r9,y1 ! .word 0xf147
+ movx.w @r4,x1 movy.w @r7+r9,y0 ! .word 0xf187
+ movx.w @r4,x1 movy.w @r7+r9,y1 ! .word 0xf1c7
+ movx.w @r5,x0 movy.w @r6+r9,y0 ! .word 0xf207
+ movx.w @r5,x0 movy.w @r6+r9,y1 ! .word 0xf247
+ movx.w @r5,x1 movy.w @r6+r9,y0 ! .word 0xf287
+ movx.w @r5,x1 movy.w @r6+r9,y1 ! .word 0xf2c7
+ movx.w @r5,x0 movy.w @r7+r9,y0 ! .word 0xf307
+ movx.w @r5,x0 movy.w @r7+r9,y1 ! .word 0xf347
+ movx.w @r5,x1 movy.w @r7+r9,y0 ! .word 0xf387
+ movx.w @r5,x1 movy.w @r7+r9,y1 ! .word 0xf3c7
+ movx.w @r4+,x0 movy.w @r6,y0 ! .word 0xf009
+ movx.w @r4+,x0 movy.w @r6,y1 ! .word 0xf049
+ movx.w @r4+,x1 movy.w @r6,y0 ! .word 0xf089
+ movx.w @r4+,x1 movy.w @r6,y1 ! .word 0xf0c9
+ movx.w @r4+,x0 movy.w @r7,y0 ! .word 0xf109
+ movx.w @r4+,x0 movy.w @r7,y1 ! .word 0xf149
+ movx.w @r4+,x1 movy.w @r7,y0 ! .word 0xf189
+ movx.w @r4+,x1 movy.w @r7,y1 ! .word 0xf1c9
+ movx.w @r5+,x0 movy.w @r6,y0 ! .word 0xf209
+ movx.w @r5+,x0 movy.w @r6,y1 ! .word 0xf249
+ movx.w @r5+,x1 movy.w @r6,y0 ! .word 0xf289
+ movx.w @r5+,x1 movy.w @r6,y1 ! .word 0xf2c9
+ movx.w @r5+,x0 movy.w @r7,y0 ! .word 0xf309
+ movx.w @r5+,x0 movy.w @r7,y1 ! .word 0xf349
+ movx.w @r5+,x1 movy.w @r7,y0 ! .word 0xf389
+ movx.w @r5+,x1 movy.w @r7,y1 ! .word 0xf3c9
+ movx.w @r4+,x0 movy.w @r6+,y0 ! .word 0xf00a
+ movx.w @r4+,x0 movy.w @r6+,y1 ! .word 0xf04a
+ movx.w @r4+,x1 movy.w @r6+,y0 ! .word 0xf08a
+ movx.w @r4+,x1 movy.w @r6+,y1 ! .word 0xf0ca
+ movx.w @r4+,x0 movy.w @r7+,y0 ! .word 0xf10a
+ movx.w @r4+,x0 movy.w @r7+,y1 ! .word 0xf14a
+ movx.w @r4+,x1 movy.w @r7+,y0 ! .word 0xf18a
+ movx.w @r4+,x1 movy.w @r7+,y1 ! .word 0xf1ca
+ movx.w @r5+,x0 movy.w @r6+,y0 ! .word 0xf20a
+ movx.w @r5+,x0 movy.w @r6+,y1 ! .word 0xf24a
+ movx.w @r5+,x1 movy.w @r6+,y0 ! .word 0xf28a
+ movx.w @r5+,x1 movy.w @r6+,y1 ! .word 0xf2ca
+ movx.w @r5+,x0 movy.w @r7+,y0 ! .word 0xf30a
+ movx.w @r5+,x0 movy.w @r7+,y1 ! .word 0xf34a
+ movx.w @r5+,x1 movy.w @r7+,y0 ! .word 0xf38a
+ movx.w @r5+,x1 movy.w @r7+,y1 ! .word 0xf3ca
+ movx.w @r4+,x0 movy.w @r6+r9,y0 ! .word 0xf00b
+ movx.w @r4+,x0 movy.w @r6+r9,y1 ! .word 0xf04b
+ movx.w @r4+,x1 movy.w @r6+r9,y0 ! .word 0xf08b
+ movx.w @r4+,x1 movy.w @r6+r9,y1 ! .word 0xf0cb
+ movx.w @r4+,x0 movy.w @r7+r9,y0 ! .word 0xf10b
+ movx.w @r4+,x0 movy.w @r7+r9,y1 ! .word 0xf14b
+ movx.w @r4+,x1 movy.w @r7+r9,y0 ! .word 0xf18b
+ movx.w @r4+,x1 movy.w @r7+r9,y1 ! .word 0xf1cb
+ movx.w @r5+,x0 movy.w @r6+r9,y0 ! .word 0xf20b
+ movx.w @r5+,x0 movy.w @r6+r9,y1 ! .word 0xf24b
+ movx.w @r5+,x1 movy.w @r6+r9,y0 ! .word 0xf28b
+ movx.w @r5+,x1 movy.w @r6+r9,y1 ! .word 0xf2cb
+ movx.w @r5+,x0 movy.w @r7+r9,y0 ! .word 0xf30b
+ movx.w @r5+,x0 movy.w @r7+r9,y1 ! .word 0xf34b
+ movx.w @r5+,x1 movy.w @r7+r9,y0 ! .word 0xf38b
+ movx.w @r5+,x1 movy.w @r7+r9,y1 ! .word 0xf3cb
+ movx.w @r4+r8,x0 movy.w @r6,y0 ! .word 0xf00d
+ movx.w @r4+r8,x0 movy.w @r6,y1 ! .word 0xf04d
+ movx.w @r4+r8,x1 movy.w @r6,y0 ! .word 0xf08d
+ movx.w @r4+r8,x1 movy.w @r6,y1 ! .word 0xf0cd
+ movx.w @r4+r8,x0 movy.w @r7,y0 ! .word 0xf10d
+ movx.w @r4+r8,x0 movy.w @r7,y1 ! .word 0xf14d
+ movx.w @r4+r8,x1 movy.w @r7,y0 ! .word 0xf18d
+ movx.w @r4+r8,x1 movy.w @r7,y1 ! .word 0xf1cd
+ movx.w @r5+r8,x0 movy.w @r6,y0 ! .word 0xf20d
+ movx.w @r5+r8,x0 movy.w @r6,y1 ! .word 0xf24d
+ movx.w @r5+r8,x1 movy.w @r6,y0 ! .word 0xf28d
+ movx.w @r5+r8,x1 movy.w @r6,y1 ! .word 0xf2cd
+ movx.w @r5+r8,x0 movy.w @r7,y0 ! .word 0xf30d
+ movx.w @r5+r8,x0 movy.w @r7,y1 ! .word 0xf34d
+ movx.w @r5+r8,x1 movy.w @r7,y0 ! .word 0xf38d
+ movx.w @r5+r8,x1 movy.w @r7,y1 ! .word 0xf3cd
+ movx.w @r4+r8,x0 movy.w @r6+,y0 ! .word 0xf00e
+ movx.w @r4+r8,x0 movy.w @r6+,y1 ! .word 0xf04e
+ movx.w @r4+r8,x1 movy.w @r6+,y0 ! .word 0xf08e
+ movx.w @r4+r8,x1 movy.w @r6+,y1 ! .word 0xf0ce
+ movx.w @r4+r8,x0 movy.w @r7+,y0 ! .word 0xf10e
+ movx.w @r4+r8,x0 movy.w @r7+,y1 ! .word 0xf14e
+ movx.w @r4+r8,x1 movy.w @r7+,y0 ! .word 0xf18e
+ movx.w @r4+r8,x1 movy.w @r7+,y1 ! .word 0xf1ce
+ movx.w @r5+r8,x0 movy.w @r6+,y0 ! .word 0xf20e
+ movx.w @r5+r8,x0 movy.w @r6+,y1 ! .word 0xf24e
+ movx.w @r5+r8,x1 movy.w @r6+,y0 ! .word 0xf28e
+ movx.w @r5+r8,x1 movy.w @r6+,y1 ! .word 0xf2ce
+ movx.w @r5+r8,x0 movy.w @r7+,y0 ! .word 0xf30e
+ movx.w @r5+r8,x0 movy.w @r7+,y1 ! .word 0xf34e
+ movx.w @r5+r8,x1 movy.w @r7+,y0 ! .word 0xf38e
+ movx.w @r5+r8,x1 movy.w @r7+,y1 ! .word 0xf3ce
+ movx.w @r4+r8,x0 movy.w @r6+r9,y0 ! .word 0xf00f
+ movx.w @r4+r8,x0 movy.w @r6+r9,y1 ! .word 0xf04f
+ movx.w @r4+r8,x1 movy.w @r6+r9,y0 ! .word 0xf08f
+ movx.w @r4+r8,x1 movy.w @r6+r9,y1 ! .word 0xf0cf
+ movx.w @r4+r8,x0 movy.w @r7+r9,y0 ! .word 0xf10f
+ movx.w @r4+r8,x0 movy.w @r7+r9,y1 ! .word 0xf14f
+ movx.w @r4+r8,x1 movy.w @r7+r9,y0 ! .word 0xf18f
+ movx.w @r4+r8,x1 movy.w @r7+r9,y1 ! .word 0xf1cf
+ movx.w @r5+r8,x0 movy.w @r6+r9,y0 ! .word 0xf20f
+ movx.w @r5+r8,x0 movy.w @r6+r9,y1 ! .word 0xf24f
+ movx.w @r5+r8,x1 movy.w @r6+r9,y0 ! .word 0xf28f
+ movx.w @r5+r8,x1 movy.w @r6+r9,y1 ! .word 0xf2cf
+ movx.w @r5+r8,x0 movy.w @r7+r9,y0 ! .word 0xf30f
+ movx.w @r5+r8,x0 movy.w @r7+r9,y1 ! .word 0xf34f
+ movx.w @r5+r8,x1 movy.w @r7+r9,y0 ! .word 0xf38f
+ movx.w @r5+r8,x1 movy.w @r7+r9,y1 ! .word 0xf3cf
+ movx.w @r4,x0 movy.w a0,@r6 ! .word 0xf015
+ movx.w @r4,x0 movy.w a1,@r6 ! .word 0xf055
+ movx.w @r4,x1 movy.w a0,@r6 ! .word 0xf095
+ movx.w @r4,x1 movy.w a1,@r6 ! .word 0xf0d5
+ movx.w @r4,x0 movy.w a0,@r7 ! .word 0xf115
+ movx.w @r4,x0 movy.w a1,@r7 ! .word 0xf155
+ movx.w @r4,x1 movy.w a0,@r7 ! .word 0xf195
+ movx.w @r4,x1 movy.w a1,@r7 ! .word 0xf1d5
+ movx.w @r5,x0 movy.w a0,@r6 ! .word 0xf215
+ movx.w @r5,x0 movy.w a1,@r6 ! .word 0xf255
+ movx.w @r5,x1 movy.w a0,@r6 ! .word 0xf295
+ movx.w @r5,x1 movy.w a1,@r6 ! .word 0xf2d5
+ movx.w @r5,x0 movy.w a0,@r7 ! .word 0xf315
+ movx.w @r5,x0 movy.w a1,@r7 ! .word 0xf355
+ movx.w @r5,x1 movy.w a0,@r7 ! .word 0xf395
+ movx.w @r5,x1 movy.w a1,@r7 ! .word 0xf3d5
+ movx.w @r4,x0 movy.w a0,@r6+ ! .word 0xf016
+ movx.w @r4,x0 movy.w a1,@r6+ ! .word 0xf056
+ movx.w @r4,x1 movy.w a0,@r6+ ! .word 0xf096
+ movx.w @r4,x1 movy.w a1,@r6+ ! .word 0xf0d6
+ movx.w @r4,x0 movy.w a0,@r7+ ! .word 0xf116
+ movx.w @r4,x0 movy.w a1,@r7+ ! .word 0xf156
+ movx.w @r4,x1 movy.w a0,@r7+ ! .word 0xf196
+ movx.w @r4,x1 movy.w a1,@r7+ ! .word 0xf1d6
+ movx.w @r5,x0 movy.w a0,@r6+ ! .word 0xf216
+ movx.w @r5,x0 movy.w a1,@r6+ ! .word 0xf256
+ movx.w @r5,x1 movy.w a0,@r6+ ! .word 0xf296
+ movx.w @r5,x1 movy.w a1,@r6+ ! .word 0xf2d6
+ movx.w @r5,x0 movy.w a0,@r7+ ! .word 0xf316
+ movx.w @r5,x0 movy.w a1,@r7+ ! .word 0xf356
+ movx.w @r5,x1 movy.w a0,@r7+ ! .word 0xf396
+ movx.w @r5,x1 movy.w a1,@r7+ ! .word 0xf3d6
+ movx.w @r4,x0 movy.w a0,@r6+r9 ! .word 0xf017
+ movx.w @r4,x0 movy.w a1,@r6+r9 ! .word 0xf057
+ movx.w @r4,x1 movy.w a0,@r6+r9 ! .word 0xf097
+ movx.w @r4,x1 movy.w a1,@r6+r9 ! .word 0xf0d7
+ movx.w @r4,x0 movy.w a0,@r7+r9 ! .word 0xf117
+ movx.w @r4,x0 movy.w a1,@r7+r9 ! .word 0xf157
+ movx.w @r4,x1 movy.w a0,@r7+r9 ! .word 0xf197
+ movx.w @r4,x1 movy.w a1,@r7+r9 ! .word 0xf1d7
+ movx.w @r5,x0 movy.w a0,@r6+r9 ! .word 0xf217
+ movx.w @r5,x0 movy.w a1,@r6+r9 ! .word 0xf257
+ movx.w @r5,x1 movy.w a0,@r6+r9 ! .word 0xf297
+ movx.w @r5,x1 movy.w a1,@r6+r9 ! .word 0xf2d7
+ movx.w @r5,x0 movy.w a0,@r7+r9 ! .word 0xf317
+ movx.w @r5,x0 movy.w a1,@r7+r9 ! .word 0xf357
+ movx.w @r5,x1 movy.w a0,@r7+r9 ! .word 0xf397
+ movx.w @r5,x1 movy.w a1,@r7+r9 ! .word 0xf3d7
+ movx.w @r4+,x0 movy.w a0,@r6 ! .word 0xf019
+ movx.w @r4+,x0 movy.w a1,@r6 ! .word 0xf059
+ movx.w @r4+,x1 movy.w a0,@r6 ! .word 0xf099
+ movx.w @r4+,x1 movy.w a1,@r6 ! .word 0xf0d9
+ movx.w @r4+,x0 movy.w a0,@r7 ! .word 0xf119
+ movx.w @r4+,x0 movy.w a1,@r7 ! .word 0xf159
+ movx.w @r4+,x1 movy.w a0,@r7 ! .word 0xf199
+ movx.w @r4+,x1 movy.w a1,@r7 ! .word 0xf1d9
+ movx.w @r5+,x0 movy.w a0,@r6 ! .word 0xf219
+ movx.w @r5+,x0 movy.w a1,@r6 ! .word 0xf259
+ movx.w @r5+,x1 movy.w a0,@r6 ! .word 0xf299
+ movx.w @r5+,x1 movy.w a1,@r6 ! .word 0xf2d9
+ movx.w @r5+,x0 movy.w a0,@r7 ! .word 0xf319
+ movx.w @r5+,x0 movy.w a1,@r7 ! .word 0xf359
+ movx.w @r5+,x1 movy.w a0,@r7 ! .word 0xf399
+ movx.w @r5+,x1 movy.w a1,@r7 ! .word 0xf3d9
+ movx.w @r4+,x0 movy.w a0,@r6+ ! .word 0xf01a
+ movx.w @r4+,x0 movy.w a1,@r6+ ! .word 0xf05a
+ movx.w @r4+,x1 movy.w a0,@r6+ ! .word 0xf09a
+ movx.w @r4+,x1 movy.w a1,@r6+ ! .word 0xf0da
+ movx.w @r4+,x0 movy.w a0,@r7+ ! .word 0xf11a
+ movx.w @r4+,x0 movy.w a1,@r7+ ! .word 0xf15a
+ movx.w @r4+,x1 movy.w a0,@r7+ ! .word 0xf19a
+ movx.w @r4+,x1 movy.w a1,@r7+ ! .word 0xf1da
+ movx.w @r5+,x0 movy.w a0,@r6+ ! .word 0xf21a
+ movx.w @r5+,x0 movy.w a1,@r6+ ! .word 0xf25a
+ movx.w @r5+,x1 movy.w a0,@r6+ ! .word 0xf29a
+ movx.w @r5+,x1 movy.w a1,@r6+ ! .word 0xf2da
+ movx.w @r5+,x0 movy.w a0,@r7+ ! .word 0xf31a
+ movx.w @r5+,x0 movy.w a1,@r7+ ! .word 0xf35a
+ movx.w @r5+,x1 movy.w a0,@r7+ ! .word 0xf39a
+ movx.w @r5+,x1 movy.w a1,@r7+ ! .word 0xf3da
+ movx.w @r4+,x0 movy.w a0,@r6+r9 ! .word 0xf01b
+ movx.w @r4+,x0 movy.w a1,@r6+r9 ! .word 0xf05b
+ movx.w @r4+,x1 movy.w a0,@r6+r9 ! .word 0xf09b
+ movx.w @r4+,x1 movy.w a1,@r6+r9 ! .word 0xf0db
+ movx.w @r4+,x0 movy.w a0,@r7+r9 ! .word 0xf11b
+ movx.w @r4+,x0 movy.w a1,@r7+r9 ! .word 0xf15b
+ movx.w @r4+,x1 movy.w a0,@r7+r9 ! .word 0xf19b
+ movx.w @r4+,x1 movy.w a1,@r7+r9 ! .word 0xf1db
+ movx.w @r5+,x0 movy.w a0,@r6+r9 ! .word 0xf21b
+ movx.w @r5+,x0 movy.w a1,@r6+r9 ! .word 0xf25b
+ movx.w @r5+,x1 movy.w a0,@r6+r9 ! .word 0xf29b
+ movx.w @r5+,x1 movy.w a1,@r6+r9 ! .word 0xf2db
+ movx.w @r5+,x0 movy.w a0,@r7+r9 ! .word 0xf31b
+ movx.w @r5+,x0 movy.w a1,@r7+r9 ! .word 0xf35b
+ movx.w @r5+,x1 movy.w a0,@r7+r9 ! .word 0xf39b
+ movx.w @r5+,x1 movy.w a1,@r7+r9 ! .word 0xf3db
+ movx.w @r4+r8,x0 movy.w a0,@r6 ! .word 0xf01d
+ movx.w @r4+r8,x0 movy.w a1,@r6 ! .word 0xf05d
+ movx.w @r4+r8,x1 movy.w a0,@r6 ! .word 0xf09d
+ movx.w @r4+r8,x1 movy.w a1,@r6 ! .word 0xf0dd
+ movx.w @r4+r8,x0 movy.w a0,@r7 ! .word 0xf11d
+ movx.w @r4+r8,x0 movy.w a1,@r7 ! .word 0xf15d
+ movx.w @r4+r8,x1 movy.w a0,@r7 ! .word 0xf19d
+ movx.w @r4+r8,x1 movy.w a1,@r7 ! .word 0xf1dd
+ movx.w @r5+r8,x0 movy.w a0,@r6 ! .word 0xf21d
+ movx.w @r5+r8,x0 movy.w a1,@r6 ! .word 0xf25d
+ movx.w @r5+r8,x1 movy.w a0,@r6 ! .word 0xf29d
+ movx.w @r5+r8,x1 movy.w a1,@r6 ! .word 0xf2dd
+ movx.w @r5+r8,x0 movy.w a0,@r7 ! .word 0xf31d
+ movx.w @r5+r8,x0 movy.w a1,@r7 ! .word 0xf35d
+ movx.w @r5+r8,x1 movy.w a0,@r7 ! .word 0xf39d
+ movx.w @r5+r8,x1 movy.w a1,@r7 ! .word 0xf3dd
+ movx.w @r4+r8,x0 movy.w a0,@r6+ ! .word 0xf01e
+ movx.w @r4+r8,x0 movy.w a1,@r6+ ! .word 0xf05e
+ movx.w @r4+r8,x1 movy.w a0,@r6+ ! .word 0xf09e
+ movx.w @r4+r8,x1 movy.w a1,@r6+ ! .word 0xf0de
+ movx.w @r4+r8,x0 movy.w a0,@r7+ ! .word 0xf11e
+ movx.w @r4+r8,x0 movy.w a1,@r7+ ! .word 0xf15e
+ movx.w @r4+r8,x1 movy.w a0,@r7+ ! .word 0xf19e
+ movx.w @r4+r8,x1 movy.w a1,@r7+ ! .word 0xf1de
+ movx.w @r5+r8,x0 movy.w a0,@r6+ ! .word 0xf21e
+ movx.w @r5+r8,x0 movy.w a1,@r6+ ! .word 0xf25e
+ movx.w @r5+r8,x1 movy.w a0,@r6+ ! .word 0xf29e
+ movx.w @r5+r8,x1 movy.w a1,@r6+ ! .word 0xf2de
+ movx.w @r5+r8,x0 movy.w a0,@r7+ ! .word 0xf31e
+ movx.w @r5+r8,x0 movy.w a1,@r7+ ! .word 0xf35e
+ movx.w @r5+r8,x1 movy.w a0,@r7+ ! .word 0xf39e
+ movx.w @r5+r8,x1 movy.w a1,@r7+ ! .word 0xf3de
+ movx.w @r4+r8,x0 movy.w a0,@r6+r9 ! .word 0xf01f
+ movx.w @r4+r8,x0 movy.w a1,@r6+r9 ! .word 0xf05f
+ movx.w @r4+r8,x1 movy.w a0,@r6+r9 ! .word 0xf09f
+ movx.w @r4+r8,x1 movy.w a1,@r6+r9 ! .word 0xf0df
+ movx.w @r4+r8,x0 movy.w a0,@r7+r9 ! .word 0xf11f
+ movx.w @r4+r8,x0 movy.w a1,@r7+r9 ! .word 0xf15f
+ movx.w @r4+r8,x1 movy.w a0,@r7+r9 ! .word 0xf19f
+ movx.w @r4+r8,x1 movy.w a1,@r7+r9 ! .word 0xf1df
+ movx.w @r5+r8,x0 movy.w a0,@r6+r9 ! .word 0xf21f
+ movx.w @r5+r8,x0 movy.w a1,@r6+r9 ! .word 0xf25f
+ movx.w @r5+r8,x1 movy.w a0,@r6+r9 ! .word 0xf29f
+ movx.w @r5+r8,x1 movy.w a1,@r6+r9 ! .word 0xf2df
+ movx.w @r5+r8,x0 movy.w a0,@r7+r9 ! .word 0xf31f
+ movx.w @r5+r8,x0 movy.w a1,@r7+r9 ! .word 0xf35f
+ movx.w @r5+r8,x1 movy.w a0,@r7+r9 ! .word 0xf39f
+ movx.w @r5+r8,x1 movy.w a1,@r7+r9 ! .word 0xf3df
+ movx.w a0,@r4 movy.w @r6,y0 ! .word 0xf025
+ movx.w a0,@r4 movy.w @r6,y1 ! .word 0xf065
+ movx.w a1,@r4 movy.w @r6,y0 ! .word 0xf0a5
+ movx.w a1,@r4 movy.w @r6,y1 ! .word 0xf0e5
+ movx.w a0,@r4 movy.w @r7,y0 ! .word 0xf125
+ movx.w a0,@r4 movy.w @r7,y1 ! .word 0xf165
+ movx.w a1,@r4 movy.w @r7,y0 ! .word 0xf1a5
+ movx.w a1,@r4 movy.w @r7,y1 ! .word 0xf1e5
+ movx.w a0,@r5 movy.w @r6,y0 ! .word 0xf225
+ movx.w a0,@r5 movy.w @r6,y1 ! .word 0xf265
+ movx.w a1,@r5 movy.w @r6,y0 ! .word 0xf2a5
+ movx.w a1,@r5 movy.w @r6,y1 ! .word 0xf2e5
+ movx.w a0,@r5 movy.w @r7,y0 ! .word 0xf325
+ movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf365
+ movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf3a5
+ movx.w a1,@r5 movy.w @r7,y1 ! .word 0xf3e5
+ movx.w a0,@r4 movy.w @r6+,y0 ! .word 0xf026
+ movx.w a0,@r4 movy.w @r6+,y1 ! .word 0xf066
+ movx.w a1,@r4 movy.w @r6+,y0 ! .word 0xf0a6
+ movx.w a1,@r4 movy.w @r6+,y1 ! .word 0xf0e6
+ movx.w a0,@r4 movy.w @r7+,y0 ! .word 0xf126
+ movx.w a0,@r4 movy.w @r7+,y1 ! .word 0xf166
+ movx.w a1,@r4 movy.w @r7+,y0 ! .word 0xf1a6
+ movx.w a1,@r4 movy.w @r7+,y1 ! .word 0xf1e6
+ movx.w a0,@r5 movy.w @r6+,y0 ! .word 0xf226
+ movx.w a0,@r5 movy.w @r6+,y1 ! .word 0xf266
+ movx.w a1,@r5 movy.w @r6+,y0 ! .word 0xf2a6
+ movx.w a1,@r5 movy.w @r6+,y1 ! .word 0xf2e6
+ movx.w a0,@r5 movy.w @r7+,y0 ! .word 0xf326
+ movx.w a0,@r5 movy.w @r7+,y1 ! .word 0xf366
+ movx.w a1,@r5 movy.w @r7+,y0 ! .word 0xf3a6
+ movx.w a1,@r5 movy.w @r7+,y1 ! .word 0xf3e6
+ movx.w a0,@r4 movy.w @r6+r9,y0 ! .word 0xf027
+ movx.w a0,@r4 movy.w @r6+r9,y1 ! .word 0xf067
+ movx.w a1,@r4 movy.w @r6+r9,y0 ! .word 0xf0a7
+ movx.w a1,@r4 movy.w @r6+r9,y1 ! .word 0xf0e7
+ movx.w a0,@r4 movy.w @r7+r9,y0 ! .word 0xf127
+ movx.w a0,@r4 movy.w @r7+r9,y1 ! .word 0xf167
+ movx.w a1,@r4 movy.w @r7+r9,y0 ! .word 0xf1a7
+ movx.w a1,@r4 movy.w @r7+r9,y1 ! .word 0xf1e7
+ movx.w a0,@r5 movy.w @r6+r9,y0 ! .word 0xf227
+ movx.w a0,@r5 movy.w @r6+r9,y1 ! .word 0xf267
+ movx.w a1,@r5 movy.w @r6+r9,y0 ! .word 0xf2a7
+ movx.w a1,@r5 movy.w @r6+r9,y1 ! .word 0xf2e7
+ movx.w a0,@r5 movy.w @r7+r9,y0 ! .word 0xf327
+ movx.w a0,@r5 movy.w @r7+r9,y1 ! .word 0xf367
+ movx.w a1,@r5 movy.w @r7+r9,y0 ! .word 0xf3a7
+ movx.w a1,@r5 movy.w @r7+r9,y1 ! .word 0xf3e7
+ movx.w a0,@r4+ movy.w @r6,y0 ! .word 0xf029
+ movx.w a0,@r4+ movy.w @r6,y1 ! .word 0xf069
+ movx.w a1,@r4+ movy.w @r6,y0 ! .word 0xf0a9
+ movx.w a1,@r4+ movy.w @r6,y1 ! .word 0xf0e9
+ movx.w a0,@r4+ movy.w @r7,y0 ! .word 0xf129
+ movx.w a0,@r4+ movy.w @r7,y1 ! .word 0xf169
+ movx.w a1,@r4+ movy.w @r7,y0 ! .word 0xf1a9
+ movx.w a1,@r4+ movy.w @r7,y1 ! .word 0xf1e9
+ movx.w a0,@r5+ movy.w @r6,y0 ! .word 0xf229
+ movx.w a0,@r5+ movy.w @r6,y1 ! .word 0xf269
+ movx.w a1,@r5+ movy.w @r6,y0 ! .word 0xf2a9
+ movx.w a1,@r5+ movy.w @r6,y1 ! .word 0xf2e9
+ movx.w a0,@r5+ movy.w @r7,y0 ! .word 0xf329
+ movx.w a0,@r5+ movy.w @r7,y1 ! .word 0xf369
+ movx.w a1,@r5+ movy.w @r7,y0 ! .word 0xf3a9
+ movx.w a1,@r5+ movy.w @r7,y1 ! .word 0xf3e9
+ movx.w a0,@r4+ movy.w @r6+,y0 ! .word 0xf02a
+ movx.w a0,@r4+ movy.w @r6+,y1 ! .word 0xf06a
+ movx.w a1,@r4+ movy.w @r6+,y0 ! .word 0xf0aa
+ movx.w a1,@r4+ movy.w @r6+,y1 ! .word 0xf0ea
+ movx.w a0,@r4+ movy.w @r7+,y0 ! .word 0xf12a
+ movx.w a0,@r4+ movy.w @r7+,y1 ! .word 0xf16a
+ movx.w a1,@r4+ movy.w @r7+,y0 ! .word 0xf1aa
+ movx.w a1,@r4+ movy.w @r7+,y1 ! .word 0xf1ea
+ movx.w a0,@r5+ movy.w @r6+,y0 ! .word 0xf22a
+ movx.w a0,@r5+ movy.w @r6+,y1 ! .word 0xf26a
+ movx.w a1,@r5+ movy.w @r6+,y0 ! .word 0xf2aa
+ movx.w a1,@r5+ movy.w @r6+,y1 ! .word 0xf2ea
+ movx.w a0,@r5+ movy.w @r7+,y0 ! .word 0xf32a
+ movx.w a0,@r5+ movy.w @r7+,y1 ! .word 0xf36a
+ movx.w a1,@r5+ movy.w @r7+,y0 ! .word 0xf3aa
+ movx.w a1,@r5+ movy.w @r7+,y1 ! .word 0xf3ea
+ movx.w a0,@r4+ movy.w @r6+r9,y0 ! .word 0xf02b
+ movx.w a0,@r4+ movy.w @r6+r9,y1 ! .word 0xf06b
+ movx.w a1,@r4+ movy.w @r6+r9,y0 ! .word 0xf0ab
+ movx.w a1,@r4+ movy.w @r6+r9,y1 ! .word 0xf0eb
+ movx.w a0,@r4+ movy.w @r7+r9,y0 ! .word 0xf12b
+ movx.w a0,@r4+ movy.w @r7+r9,y1 ! .word 0xf16b
+ movx.w a1,@r4+ movy.w @r7+r9,y0 ! .word 0xf1ab
+ movx.w a1,@r4+ movy.w @r7+r9,y1 ! .word 0xf1eb
+ movx.w a0,@r5+ movy.w @r6+r9,y0 ! .word 0xf22b
+ movx.w a0,@r5+ movy.w @r6+r9,y1 ! .word 0xf26b
+ movx.w a1,@r5+ movy.w @r6+r9,y0 ! .word 0xf2ab
+ movx.w a1,@r5+ movy.w @r6+r9,y1 ! .word 0xf2eb
+ movx.w a0,@r5+ movy.w @r7+r9,y0 ! .word 0xf32b
+ movx.w a0,@r5+ movy.w @r7+r9,y1 ! .word 0xf36b
+ movx.w a1,@r5+ movy.w @r7+r9,y0 ! .word 0xf3ab
+ movx.w a1,@r5+ movy.w @r7+r9,y1 ! .word 0xf3eb
+ movx.w a0,@r4+r8 movy.w @r6,y0 ! .word 0xf02d
+ movx.w a0,@r4+r8 movy.w @r6,y1 ! .word 0xf06d
+ movx.w a1,@r4+r8 movy.w @r6,y0 ! .word 0xf0ad
+ movx.w a1,@r4+r8 movy.w @r6,y1 ! .word 0xf0ed
+ movx.w a0,@r4+r8 movy.w @r7,y0 ! .word 0xf12d
+ movx.w a0,@r4+r8 movy.w @r7,y1 ! .word 0xf16d
+ movx.w a1,@r4+r8 movy.w @r7,y0 ! .word 0xf1ad
+ movx.w a1,@r4+r8 movy.w @r7,y1 ! .word 0xf1ed
+ movx.w a0,@r5+r8 movy.w @r6,y0 ! .word 0xf22d
+ movx.w a0,@r5+r8 movy.w @r6,y1 ! .word 0xf26d
+ movx.w a1,@r5+r8 movy.w @r6,y0 ! .word 0xf2ad
+ movx.w a1,@r5+r8 movy.w @r6,y1 ! .word 0xf2ed
+ movx.w a0,@r5+r8 movy.w @r7,y0 ! .word 0xf32d
+ movx.w a0,@r5+r8 movy.w @r7,y1 ! .word 0xf36d
+ movx.w a1,@r5+r8 movy.w @r7,y0 ! .word 0xf3ad
+ movx.w a1,@r5+r8 movy.w @r7,y1 ! .word 0xf3ed
+ movx.w a0,@r4+r8 movy.w @r6+,y0 ! .word 0xf02e
+ movx.w a0,@r4+r8 movy.w @r6+,y1 ! .word 0xf06e
+ movx.w a1,@r4+r8 movy.w @r6+,y0 ! .word 0xf0ae
+ movx.w a1,@r4+r8 movy.w @r6+,y1 ! .word 0xf0ee
+ movx.w a0,@r4+r8 movy.w @r7+,y0 ! .word 0xf12e
+ movx.w a0,@r4+r8 movy.w @r7+,y1 ! .word 0xf16e
+ movx.w a1,@r4+r8 movy.w @r7+,y0 ! .word 0xf1ae
+ movx.w a1,@r4+r8 movy.w @r7+,y1 ! .word 0xf1ee
+ movx.w a0,@r5+r8 movy.w @r6+,y0 ! .word 0xf22e
+ movx.w a0,@r5+r8 movy.w @r6+,y1 ! .word 0xf26e
+ movx.w a1,@r5+r8 movy.w @r6+,y0 ! .word 0xf2ae
+ movx.w a1,@r5+r8 movy.w @r6+,y1 ! .word 0xf2ee
+ movx.w a0,@r5+r8 movy.w @r7+,y0 ! .word 0xf32e
+ movx.w a0,@r5+r8 movy.w @r7+,y1 ! .word 0xf36e
+ movx.w a1,@r5+r8 movy.w @r7+,y0 ! .word 0xf3ae
+ movx.w a1,@r5+r8 movy.w @r7+,y1 ! .word 0xf3ee
+ movx.w a0,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf02f
+ movx.w a0,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf06f
+ movx.w a1,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf0af
+ movx.w a1,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf0ef
+ movx.w a0,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf12f
+ movx.w a0,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf16f
+ movx.w a1,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf1af
+ movx.w a1,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf1ef
+ movx.w a0,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf22f
+ movx.w a0,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf26f
+ movx.w a1,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf2af
+ movx.w a1,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf2ef
+ movx.w a0,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf32f
+ movx.w a0,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf36f
+ movx.w a1,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf3af
+ movx.w a1,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf3ef
+
+ movxwaxydxy:
+ movx.w @r4,x0 !
+ movx.w @r4,y0 !
+ movx.w @r4,x1 !
+ movx.w @r4,y1 !
+ movx.w @r0,x0 !
+ movx.w @r0,y0 !
+ movx.w @r0,x1 !
+ movx.w @r0,y1 !
+ movx.w @r5,x0 !
+ movx.w @r5,y0 !
+ movx.w @r5,x1 !
+ movx.w @r5,y1 !
+ movx.w @r1,x0 !
+ movx.w @r1,y0 !
+ movx.w @r1,x1 !
+ movx.w @r1,y1 !
+ movx.w @r4+,x0 !
+ movx.w @r4+,y0 !
+ movx.w @r4+,x1 !
+ movx.w @r4+,y1 !
+ movx.w @r0+,x0 !
+ movx.w @r0+,y0 !
+ movx.w @r0+,x1 !
+ movx.w @r0+,y1 !
+ movx.w @r5+,x0 !
+ movx.w @r5+,y0 !
+ movx.w @r5+,x1 !
+ movx.w @r5+,y1 !
+ movx.w @r1+,x0 !
+ movx.w @r1+,y0 !
+ movx.w @r1+,x1 !
+ movx.w @r1+,y1 !
+ movx.w @r4+r8,x0 !
+ movx.w @r4+r8,y0 !
+ movx.w @r4+r8,x1 !
+ movx.w @r4+r8,y1 !
+ movx.w @r0+r8,x0 !
+ movx.w @r0+r8,y0 !
+ movx.w @r0+r8,x1 !
+ movx.w @r0+r8,y1 !
+ movx.w @r5+r8,x0 !
+ movx.w @r5+r8,y0 !
+ movx.w @r5+r8,x1 !
+ movx.w @r5+r8,y1 !
+ movx.w @r1+r8,x0 !
+ movx.w @r1+r8,y0 !
+ movx.w @r1+r8,x1 !
+ movx.w @r1+r8,y1 !
+
+ movxwdaxaxy: !
+ movx.w a0,@r4 !
+ movx.w x0,@r4 !
+ movx.w a1,@r4 !
+ movx.w x1,@r4 !
+ movx.w a0,@r0 !
+ movx.w x0,@r0 !
+ movx.w a1,@r0 !
+ movx.w x1,@r0 !
+ movx.w a0,@r5 !
+ movx.w x0,@r5 !
+ movx.w a1,@r5 !
+ movx.w x1,@r5 !
+ movx.w a0,@r1 !
+ movx.w x0,@r1 !
+ movx.w a1,@r1 !
+ movx.w x1,@r1 !
+ movx.w a0,@r4+ !
+ movx.w x0,@r4+ !
+ movx.w a1,@r4+ !
+ movx.w x1,@r4+ !
+ movx.w a0,@r0+ !
+ movx.w x0,@r0+ !
+ movx.w a1,@r0+ !
+ movx.w x1,@r0+ !
+ movx.w a0,@r5+ !
+ movx.w x0,@r5+ !
+ movx.w a1,@r5+ !
+ movx.w x1,@r5+ !
+ movx.w a0,@r1+ !
+ movx.w x0,@r1+ !
+ movx.w a1,@r1+ !
+ movx.w x1,@r1+ !
+ movx.w a0,@r4+r8 !
+ movx.w x0,@r4+r8 !
+ movx.w a1,@r4+r8 !
+ movx.w x1,@r4+r8 !
+ movx.w a0,@r0+r8 !
+ movx.w x0,@r0+r8 !
+ movx.w a1,@r0+r8 !
+ movx.w x1,@r0+r8 !
+ movx.w a0,@r5+r8 !
+ movx.w x0,@r5+r8 !
+ movx.w a1,@r5+r8 !
+ movx.w x1,@r5+r8 !
+ movx.w a0,@r1+r8 !
+ movx.w x0,@r1+r8 !
+ movx.w a1,@r1+r8 !
+ movx.w x1,@r1+r8 !
+
+ movywayxdyx: !
+ movy.w @r6,y0 !
+ movy.w @r6,y1 !
+ movy.w @r6,x0 !
+ movy.w @r6,x1 !
+ movy.w @r7,y0 !
+ movy.w @r7,y1 !
+ movy.w @r7,x0 !
+ movy.w @r7,x1 !
+ movy.w @r2,y0 !
+ movy.w @r2,y1 !
+ movy.w @r2,x0 !
+ movy.w @r2,x1 !
+ movy.w @r3,y0 !
+ movy.w @r3,y1 !
+ movy.w @r3,x0 !
+ movy.w @r3,x1 !
+ movy.w @r6+,y0 !
+ movy.w @r6+,y1 !
+ movy.w @r6+,x0 !
+ movy.w @r6+,x1 !
+ movy.w @r7+,y0 !
+ movy.w @r7+,y1 !
+ movy.w @r7+,x0 !
+ movy.w @r7+,x1 !
+ movy.w @r2+,y0 !
+ movy.w @r2+,y1 !
+ movy.w @r2+,x0 !
+ movy.w @r2+,x1 !
+ movy.w @r3+,y0 !
+ movy.w @r3+,y1 !
+ movy.w @r3+,x0 !
+ movy.w @r3+,x1 !
+ movy.w @r6+r9,y0 !
+ movy.w @r6+r9,y1 !
+ movy.w @r6+r9,x0 !
+ movy.w @r6+r9,x1 !
+ movy.w @r7+r9,y0 !
+ movy.w @r7+r9,y1 !
+ movy.w @r7+r9,x0 !
+ movy.w @r7+r9,x1 !
+ movy.w @r2+r9,y0 !
+ movy.w @r2+r9,y1 !
+ movy.w @r2+r9,x0 !
+ movy.w @r2+r9,x1 !
+ movy.w @r3+r9,y0 !
+ movy.w @r3+r9,y1 !
+ movy.w @r3+r9,x0 !
+ movy.w @r3+r9,x1 !
+
+ movywdayayx:
+ movy.w a0,@r6
+ movy.w a1,@r6
+ movy.w y0,@r6
+ movy.w y1,@r6
+ movy.w a0,@r7
+ movy.w a1,@r7
+ movy.w y0,@r7
+ movy.w y1,@r7
+ movy.w a0,@r2
+ movy.w a1,@r2
+ movy.w y0,@r2
+ movy.w y1,@r2
+ movy.w a0,@r3
+ movy.w a1,@r3
+ movy.w y0,@r3
+ movy.w y1,@r3
+ movy.w a0,@r6+
+ movy.w a1,@r6+
+ movy.w y0,@r6+
+ movy.w y1,@r6+
+ movy.w a0,@r7+
+ movy.w a1,@r7+
+ movy.w y0,@r7+
+ movy.w y1,@r7+
+ movy.w a0,@r2+
+ movy.w a1,@r2+
+ movy.w y0,@r2+
+ movy.w y1,@r2+
+ movy.w a0,@r3+
+ movy.w a1,@r3+
+ movy.w y0,@r3+
+ movy.w y1,@r3+
+ movy.w a0,@r6+r9
+ movy.w a1,@r6+r9
+ movy.w y0,@r6+r9
+ movy.w y1,@r6+r9
+ movy.w a0,@r7+r9
+ movy.w a1,@r7+r9
+ movy.w y0,@r7+r9
+ movy.w y1,@r7+r9
+ movy.w a0,@r2+r9
+ movy.w a1,@r2+r9
+ movy.w y0,@r2+r9
+ movy.w y1,@r2+r9
+ movy.w a0,@r3+r9
+ movy.w a1,@r3+r9
+ movy.w y0,@r3+r9
+ movy.w y1,@r3+r9
+
+ mov r4, r0
+ mov r4, r1
+ mov r4, r2
+ mov r4, r3
+ mov r4, r5
+ mov r4, r6
+ mov r5, r7
+
+ movxlaxydxy:
+ movx.l @r4,x0
+ movx.l @r4,y0
+ movx.l @r4,x1
+ movx.l @r4,y1
+ movx.l @r0,x0
+ movx.l @r0,y0
+ movx.l @r0,x1
+ movx.l @r0,y1
+ movx.l @r5,x0
+ movx.l @r5,y0
+ movx.l @r5,x1
+ movx.l @r5,y1
+ movx.l @r1,x0
+ movx.l @r1,y0
+ movx.l @r1,x1
+ movx.l @r1,y1
+ movx.l @r4+,x0
+ movx.l @r4+,y0
+ movx.l @r4+,x1
+ movx.l @r4+,y1
+ movx.l @r0+,x0
+ movx.l @r0+,y0
+ movx.l @r0+,x1
+ movx.l @r0+,y1
+ movx.l @r5+,x0
+ movx.l @r5+,y0
+ movx.l @r5+,x1
+ movx.l @r5+,y1
+ movx.l @r1+,x0
+ movx.l @r1+,y0
+ movx.l @r1+,x1
+ movx.l @r1+,y1
+ movx.l @r4+r8,x0
+ movx.l @r4+r8,y0
+ movx.l @r4+r8,x1
+ movx.l @r4+r8,y1
+ movx.l @r0+r8,x0
+ movx.l @r0+r8,y0
+ movx.l @r0+r8,x1
+ movx.l @r0+r8,y1
+ movx.l @r5+r8,x0
+ movx.l @r5+r8,y0
+ movx.l @r5+r8,x1
+ movx.l @r5+r8,y1
+ movx.l @r1+r8,x0
+ movx.l @r1+r8,y0
+ movx.l @r1+r8,x1
+ movx.l @r1+r8,y1
+
+ movxldaxaxy:
+ movx.l a0,@r4
+ movx.l x0,@r4
+ movx.l a1,@r4
+ movx.l x1,@r4
+ movx.l a0,@r0
+ movx.l x0,@r0
+ movx.l a1,@r0
+ movx.l x1,@r0
+ movx.l a0,@r5
+ movx.l x0,@r5
+ movx.l a1,@r5
+ movx.l x1,@r5
+ movx.l a0,@r1
+ movx.l x0,@r1
+ movx.l a1,@r1
+ movx.l x1,@r1
+ movx.l a0,@r4+
+ movx.l x0,@r4+
+ movx.l a1,@r4+
+ movx.l x1,@r4+
+ movx.l a0,@r0+
+ movx.l x0,@r0+
+ movx.l a1,@r0+
+ movx.l x1,@r0+
+ movx.l a0,@r5+
+ movx.l x0,@r5+
+ movx.l a1,@r5+
+ movx.l x1,@r5+
+ movx.l a0,@r1+
+ movx.l x0,@r1+
+ movx.l a1,@r1+
+ movx.l x1,@r1+
+ movx.l a0,@r4+r8
+ movx.l x0,@r4+r8
+ movx.l a1,@r4+r8
+ movx.l x1,@r4+r8
+ movx.l a0,@r0+r8
+ movx.l x0,@r0+r8
+ movx.l a1,@r0+r8
+ movx.l x1,@r0+r8
+ movx.l a0,@r5+r8
+ movx.l x0,@r5+r8
+ movx.l a1,@r5+r8
+ movx.l x1,@r5+r8
+ movx.l a0,@r1+r8
+ movx.l x0,@r1+r8
+ movx.l a1,@r1+r8
+ movx.l x1,@r1+r8
+
+ movylayxdyx:
+ movy.l @r6,y0
+ movy.l @r6,y1
+ movy.l @r6,x0
+ movy.l @r6,x1
+ movy.l @r7,y0
+ movy.l @r7,y1
+ movy.l @r7,x0
+ movy.l @r7,x1
+ movy.l @r2,y0
+ movy.l @r2,y1
+ movy.l @r2,x0
+ movy.l @r2,x1
+ movy.l @r3,y0
+ movy.l @r3,y1
+ movy.l @r3,x0
+ movy.l @r3,x1
+ movy.l @r6+,y0
+ movy.l @r6+,y1
+ movy.l @r6+,x0
+ movy.l @r6+,x1
+ movy.l @r7+,y0
+ movy.l @r7+,y1
+ movy.l @r7+,x0
+ movy.l @r7+,x1
+ movy.l @r2+,y0
+ movy.l @r2+,y1
+ movy.l @r2+,x0
+ movy.l @r2+,x1
+ movy.l @r3+,y0
+ movy.l @r3+,y1
+ movy.l @r3+,x0
+ movy.l @r3+,x1
+ movy.l @r6+r9,y0
+ movy.l @r6+r9,y1
+ movy.l @r6+r9,x0
+ movy.l @r6+r9,x1
+ movy.l @r7+r9,y0
+ movy.l @r7+r9,y1
+ movy.l @r7+r9,x0
+ movy.l @r7+r9,x1
+ movy.l @r2+r9,y0
+ movy.l @r2+r9,y1
+ movy.l @r2+r9,x0
+ movy.l @r2+r9,x1
+ movy.l @r3+r9,y0
+ movy.l @r3+r9,y1
+ movy.l @r3+r9,x0
+ movy.l @r3+r9,x1
+
+ movyldayayx:
+ movy.l a0,@r6
+ movy.l a1,@r6
+ movy.l y0,@r6
+ movy.l y1,@r6
+ movy.l a0,@r7
+ movy.l a1,@r7
+ movy.l y0,@r7
+ movy.l y1,@r7
+ movy.l a0,@r2
+ movy.l a1,@r2
+ movy.l y0,@r2
+ movy.l y1,@r2
+ movy.l a0,@r3
+ movy.l a1,@r3
+ movy.l y0,@r3
+ movy.l y1,@r3
+ movy.l a0,@r6+
+ movy.l a1,@r6+
+ movy.l y0,@r6+
+ movy.l y1,@r6+
+ movy.l a0,@r7+
+ movy.l a1,@r7+
+ movy.l y0,@r7+
+ movy.l y1,@r7+
+ movy.l a0,@r2+
+ movy.l a1,@r2+
+ movy.l y0,@r2+
+ movy.l y1,@r2+
+ movy.l a0,@r3+
+ movy.l a1,@r3+
+ movy.l y0,@r3+
+ movy.l y1,@r3+
+ movy.l a0,@r6+r9
+ movy.l a1,@r6+r9
+ movy.l y0,@r6+r9
+ movy.l y1,@r6+r9
+ movy.l a0,@r7+r9
+ movy.l a1,@r7+r9
+ movy.l y0,@r7+r9
+ movy.l y1,@r7+r9
+ movy.l a0,@r2+r9
+ movy.l a1,@r2+r9
+ movy.l y0,@r2+r9
+ movy.l y1,@r2+r9
+ movy.l a0,@r3+r9
+ movy.l a1,@r3+r9
+ movy.l y0,@r3+r9
+ movy.l y1,@r3+r9
+
+ pass
+ exit 0
Index: pabs.s
===================================================================
RCS file: pabs.s
diff -N pabs.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- pabs.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,54 ----
+ # sh testcase for pabs
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ # FIXME: opcode table ambiguity in ignored bits 4-7.
+
+ .include "testutils.inc"
+
+ start
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ pabs x0, x1
+ pabs y0, y1
+ assert_sreg 0x5a5a5a5b, x1
+ assert_sreg 0x5a5a5a5b, y1
+ pabs x1, x0
+ pabs y1, y0
+ assert_sreg 0x5a5a5a5b, x0
+ assert_sreg 0x5a5a5a5b, y0
+
+ set_dcfalse
+ dct pabs a0, a0
+ dct pabs m0, m0
+ assert_sreg 0xa5a5a5a5, a0
+ assert_sreg2 0xa5a5a5a5, m0
+ set_dctrue
+ dct pabs a0, a0
+ dct pabs m0, m0
+ assert_sreg 0x5a5a5a5b, a0
+ assert_sreg2 0x5a5a5a5b, m0
+
+ set_dctrue
+ dcf pabs a1, a1
+ dcf pabs m1, m1
+ assert_sreg2 0xa5a5a5a5, a1
+ assert_sreg2 0xa5a5a5a5, m1
+ set_dcfalse
+ dcf pabs a1, a1
+ dcf pabs m1, m1
+ assert_sreg2 0x5a5a5a5b, a1
+ assert_sreg2 0x5a5a5a5b, m1
+
+ test_grs_a5a5
+
+ pass
+ exit 0
Index: pclr.s
===================================================================
RCS file: pclr.s
diff -N pclr.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- pclr.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,65 ----
+ # sh testcase for pclr
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ # FIXME: opcode table ambiguity in ignored bits 4-7.
+
+ .include "testutils.inc"
+
+ start
+ pclr_cc:
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ assert_sreg 0xa5a5a5a5, x0
+ pclr x0
+ assert_sreg 0, x0
+
+ set_dcfalse
+ dct pclr x1
+ assert_sreg 0xa5a5a5a5, x1
+ set_dctrue
+ dct pclr x1
+ assert_sreg 0, x1
+
+ set_dctrue
+ dcf pclr y0
+ assert_sreg 0xa5a5a5a5, y0
+ set_dcfalse
+ dcf pclr y0
+ assert_sreg 0, y0
+
+ test_grs_a5a5
+ assert_sreg 0xa5a5a5a5, a0
+ assert_sreg 0xa5a5a5a5, y1
+ assert_sreg2 0xa5a5a5a5, a1
+ assert_sreg2 0xa5a5a5a5, m0
+ assert_sreg2 0xa5a5a5a5, m1
+
+ pclr_pmuls:
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ pclr x0 pmuls y0, y1, a0
+
+ assert_sreg 0, x0
+ assert_sreg 0x3fc838b2, a0 ! 0xa5a5 x 0xa5a5
+
+ test_grs_a5a5
+
+ pass
+ exit 0
Index: prnd.s
===================================================================
RCS file: prnd.s
diff -N prnd.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- prnd.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,90 ----
+ # sh testcase for prnd
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ # FIXME: opcode table ambiguity in ignored bits 4-7.
+
+ .include "testutils.inc"
+
+ start
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ # prnd(0xa5a5a5a5) = 0xa5a60000
+ prnd x0, x0
+ prnd y0, y0
+ assert_sreg 0xa5a60000, x0
+ assert_sreg 0xa5a60000, y0
+
+ # prnd(1) = 1
+ mov #1, r0
+ shll16 r0
+ lds r0, x0
+ pcopy x0, y0
+ prnd x0, x0
+ prnd y0, y0
+ assert_sreg 0x10000, x0
+ assert_sreg 0x10000, y0
+
+ # prnd(1.4999999) = 1
+ mov #1, r0
+ shll8 r0
+ or #0x7f, r0
+ shll8 r0
+ or #0xff, r0
+ lds r0, x0
+ pcopy x0, y0
+ prnd x0, x0
+ prnd y0, y0
+ assert_sreg 0x10000, x0
+ assert_sreg 0x10000, y0
+
+ # prnd(1.5) = 2
+ mov #1, r0
+ shll8 r0
+ or #0x80, r0
+ shll8 r0
+ lds r0, x0
+ pcopy x0, y0
+ prnd x0, x0
+ prnd y0, y0
+ assert_sreg 0x20000, x0
+ assert_sreg 0x20000, y0
+
+ # dct prnd
+ set_dcfalse
+ dct prnd x0, x1
+ dct prnd y0, y1
+ assert_sreg2 0xa5a5a5a5, x1
+ assert_sreg2 0xa5a5a5a5, y1
+ set_dctrue
+ dct prnd x0, x1
+ dct prnd y0, y1
+ assert_sreg2 0x20000, x1
+ assert_sreg2 0x20000, y1
+
+ # dcf prnd
+ set_dctrue
+ dcf prnd x0, m0
+ dcf prnd y0, m1
+ assert_sreg2 0xa5a5a5a5, m0
+ assert_sreg2 0xa5a5a5a5, m1
+ set_dcfalse
+ dcf prnd x0, m0
+ dcf prnd y0, m1
+ assert_sreg2 0x20000, m0
+ assert_sreg2 0x20000, m1
+
+ set_greg 0xa5a5a5a5, r0
+ test_grs_a5a5
+ assert_sreg 0xa5a5a5a5, a0
+ assert_sreg2 0xa5a5a5a5, a1
+ pass
+ exit 0
Index: psub.s
===================================================================
RCS file: psub.s
diff -N psub.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- psub.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,64 ----
+ # sh testcase for psub
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ psub_sx_sy:
+ # 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero
+ psub x0, y0, a0
+ assert_sreg 0, a0
+
+ psub_sy_sx:
+ # 100 - 25 = 75
+ mov #100, r0
+ mov #25, r1
+ lds r0, y1
+ lds r1, x1
+ psub y1, x1, a0
+ assert_sreg 75, a0
+
+ dct_psub:
+ # 100 - 25 = 75
+ set_dcfalse
+ dct psub y1, x1, a1
+ assert_sreg2 0xa5a5a5a5, a1
+ set_dctrue
+ dct psub y1, x1, a1
+ assert_sreg2 75, a1
+
+ dcf_psub:
+ # 25 - 100 = -75
+ set_dctrue
+ dcf psub x1, y1, m1
+ assert_sreg2 0xa5a5a5a5, m1
+ set_dcfalse
+ dcf psub x1, y1, m1
+ assert_sreg2 -75, m1
+
+ psub_pmuls:
+ # 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four)
+ mov #2, r0
+ shll16 r0
+ lds r0, x0
+ lds r0, y0
+ psub x1, y1, a1 pmuls x0, y0, a0
+ assert_sreg 8, a0
+ assert_sreg2 -75, a1
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+ test_grs_a5a5
+ pass
+ exit 0
Index: pswap.s
===================================================================
RCS file: pswap.s
diff -N pswap.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- pswap.s 7 Jan 2004 21:58:26 -0000
***************
*** 0 ****
--- 1,177 ----
+ # sh testcase for pswap
+ # mach: shdsp
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+
+ pswapx:
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ set_greg 0xa5a57777, r0
+ lds r0, x0
+ pswap x0, y0
+ assert_sreg 0x7777a5a5, y0
+
+ set_greg 0xa5a5a5a5, r0
+ test_grs_a5a5
+ assert_sreg 0xa5a57777, x0
+ assert_sreg 0xa5a5a5a5, x1
+ assert_sreg 0xa5a5a5a5, y1
+ assert_sreg 0xa5a5a5a5, a0
+ assert_sreg2 0xa5a5a5a5, a1
+ assert_sreg2 0xa5a5a5a5, m0
+ assert_sreg2 0xa5a5a5a5, m1
+
+ pswapy:
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ set_greg 0xa5a57777, r0
+ lds r0, y0
+ pswap y0, x0
+ assert_sreg 0x7777a5a5, x0
+
+ set_greg 0xa5a5a5a5, r0
+ test_grs_a5a5
+ assert_sreg 0xa5a57777, y0
+ assert_sreg 0xa5a5a5a5, x1
+ assert_sreg 0xa5a5a5a5, y1
+ assert_sreg 0xa5a5a5a5, a0
+ assert_sreg2 0xa5a5a5a5, a1
+ assert_sreg2 0xa5a5a5a5, m0
+ assert_sreg2 0xa5a5a5a5, m1
+
+ pswapa:
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ set_greg 0xa5a57777, r0
+ lds r0, a0
+ pcopy a0, a1
+ pswap a1, y0
+ assert_sreg 0x7777a5a5, y0
+
+ set_greg 0xa5a5a5a5, r0
+ test_grs_a5a5
+ assert_sreg 0xa5a57777, a0
+ assert_sreg2 0xa5a57777, a1
+ assert_sreg 0xa5a5a5a5, x0
+ assert_sreg 0xa5a5a5a5, x1
+ assert_sreg 0xa5a5a5a5, y1
+ assert_sreg2 0xa5a5a5a5, m0
+ assert_sreg2 0xa5a5a5a5, m1
+
+ pswapm:
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ set_greg 0xa5a57777, r0
+ lds r0, a0
+ pcopy a0, m1
+ pswap m1, y0
+ assert_sreg 0x7777a5a5, y0
+
+ set_greg 0xa5a5a5a5, r0
+ test_grs_a5a5
+ assert_sreg 0xa5a57777, a0
+ assert_sreg2 0xa5a57777, m1
+ assert_sreg 0xa5a5a5a5, x0
+ assert_sreg 0xa5a5a5a5, x1
+ assert_sreg 0xa5a5a5a5, y1
+ assert_sreg2 0xa5a5a5a5, a1
+ assert_sreg2 0xa5a5a5a5, m0
+
+
+ dct_pswapx:
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ set_greg 0xa5a57777, r0
+ lds r0, x0
+ set_dcfalse
+ dct pswap x0, y0
+ assert_sreg 0xa5a5a5a5, y0
+ set_dctrue
+ dct pswap x0, y0
+ assert_sreg 0x7777a5a5, y0
+
+ set_greg 0xa5a5a5a5, r0
+ test_grs_a5a5
+ assert_sreg 0xa5a57777, x0
+ assert_sreg 0xa5a5a5a5, x1
+ assert_sreg 0xa5a5a5a5, y1
+ assert_sreg 0xa5a5a5a5, a0
+ assert_sreg2 0xa5a5a5a5, a1
+ assert_sreg2 0xa5a5a5a5, m0
+ assert_sreg2 0xa5a5a5a5, m1
+
+ dcf_pswapy:
+ set_grs_a5a5
+ lds r0, a0
+ pcopy a0, a1
+ lds r0, x0
+ lds r0, x1
+ lds r0, y0
+ lds r0, y1
+ pcopy x0, m0
+ pcopy y1, m1
+
+ set_greg 0xa5a57777, r0
+ lds r0, x0
+ set_dctrue
+ dcf pswap x0, y0
+ assert_sreg 0xa5a5a5a5, y0
+ set_dcfalse
+ dcf pswap x0, y0
+ assert_sreg 0x7777a5a5, y0
+
+ set_greg 0xa5a5a5a5, r0
+ test_grs_a5a5
+ assert_sreg 0xa5a57777, x0
+ assert_sreg 0xa5a5a5a5, x1
+ assert_sreg 0xa5a5a5a5, y1
+ assert_sreg 0xa5a5a5a5, a0
+ assert_sreg2 0xa5a5a5a5, a1
+ assert_sreg2 0xa5a5a5a5, m0
+ assert_sreg2 0xa5a5a5a5, m1
+
+ pass
+ exit 0
Index: testutils.inc
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/sh/testutils.inc,v
retrieving revision 1.1
diff -p -r1.1 testutils.inc
*** testutils.inc 23 Jul 2003 21:40:43 -0000 1.1
--- testutils.inc 7 Jan 2004 21:58:26 -0000
*************** set_greg\@:
*** 473,479 ****
pop r0
.endm
! .macro set_sr_bit
push r0
push r1
get_sr r0
--- 473,479 ----
pop r0
.endm
! .macro set_sr_bit val
push r0
push r1
get_sr r0
*************** set_greg\@:
*** 532,537 ****
--- 532,538 ----
pop r0
bra .Lssr\@
nop
+ .align 2
.Lssrval\@:
.long \val
.Lssr\@:
*************** set_greg\@:
*** 550,555 ****
--- 551,557 ----
pop r0
bra .Lssr2_\@
nop
+ .align 2
.Lssr2val\@:
.long \val
.Lssr2_\@:
*************** set_greg\@:
*** 564,569 ****
--- 566,572 ----
pop r0
bra .Lscr\@
nop
+ .align 2
.Lscrval\@:
.long \val
.Lscr\@:
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFA] Add sh4a tests to sim/testsuite/sim/sh
2004-01-07 22:04 ` [RFA] Add sh4a tests to sim/testsuite/sim/sh Michael Snyder
@ 2004-01-08 15:07 ` Joern Rennecke
2004-01-08 22:04 ` Michael Snyder
2004-01-09 13:19 ` Joern Rennecke
1 sibling, 1 reply; 14+ messages in thread
From: Joern Rennecke @ 2004-01-08 15:07 UTC (permalink / raw)
To: Michael Snyder; +Cc: joern.rennecke, amylaar, andrew.stubbs, gdb-patches
> + # FIXME I'm not sure if cmp is signed or unsigned.
> + # This seems wrong.
> + test_qnanm:
> + # Test negantive qnan
> + fldi0 fr11
> + mov.l qnanm, r0
> + lds r0, fpul
> + fsts fpul, fr0
> + fipr fv0, fv8
> + # fr11 should be minus qnan (or less)
> + flds fr11, fpul
> + sts fpul, r1
> + cmp/ge r1, r0
> + bt .L2
> + fail
> + .L2:
cmp/ge is signed.
cmp/hs is unsigned.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFA] Add sh4a to sh-sim (2nd iteration)
2004-01-07 21:56 [RFA] Add sh4a to sh-sim (2nd iteration) Michael Snyder
2004-01-07 22:04 ` [RFA] Add sh4a tests to sim/testsuite/sim/sh Michael Snyder
@ 2004-01-08 16:15 ` Joern Rennecke
2004-01-08 22:02 ` Michael Snyder
1 sibling, 1 reply; 14+ messages in thread
From: Joern Rennecke @ 2004-01-08 16:15 UTC (permalink / raw)
To: Michael Snyder; +Cc: joern.rennecke, amylaar, andrew.stubbs, gdb-patches
> (expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit
> instead of 8-bit table (some insns are ambiguous to 8 bits).
You are converting iteration into recursion - I don't see what is flat about
deep recursion.
> --- gencode.c 7 Jan 2004 21:38:26 -0000
> ***************
> *** 1,4 ****
> ! /* Simulator/Opcode generator for the Hitachi Super-H architecture.
>
> Written by Steve Chamberlain of Cygnus Support.
> sac@cygnus.com
> --- 1,5 ----
> ! /* Simulator/Opcode generator for the Renesas
> ! (formerly Hitachi) Super-H architecture.
>
> Written by Steve Chamberlain of Cygnus Support.
> sac@cygnus.com
That should be Renesas (formerly Hitachi) / SuperH Inc SuperH architecture.
> + /* sh4a */
> + { "", "", "ftrv <FV_N>", "1111vv0111111101",
> + "if (FPSCR_PR)",
> + " RAISE_EXCEPTION (SIGILL);",
> + "else",
> + "{",
> + " /* FIXME not implemented. */",
> + " printf (\"ftrv xmtrx, FV%d\\n\", v1);",
> + "}",
> + },
ftrv is an sh4 instruction.
> { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
> "MA (1);",
> "DBR = RLAT (R[n]);",
> "R[n] += 4;",
> "/* FIXME: user mode */",
> },
> ! { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
> ! "if (SR_MD)",
> ! "{ /* priv mode */",
> ! " MA (1);",
> ! " DBR = RLAT (R[n]);",
> ! " R[n] += 4;",
> ! "}",
> ! "else",
> ! " RAISE_EXCEPTION (SIGILL); /* user mode */",
> ! },
Why do you keep the old "ldc.l @<REG_N>+,DBR" version around?
> ! { "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
> ! "MACL = ((int) R[n]) * ((int) R[m]);",
> },
The #if 0 was left there as a reminder that the casts to int are not fully
portable. The casts should be replaced with the SEXT32 macro.
> ! { "", "n", "movx.w @<REG_xy>,<DSP_XY>", "111100xyXY0001??",
> "DSP_R (m) = RSWAT (R[n]) << 16;",
> ! "if (iword & 3)",
> ! " {",
> ! " iword &= 0xfd53; goto top;",
> ! " }",
> ! },
I think I understand the way the new move instructions were added a bit
better now.
The implementation could be made faster by having the movx/nopy
patterns separate, but I suppose speed is not such an issue for sh-dsp
simulation, seeing that we don't have time-intensive testcases that
use dsp move instructions.
> *************** op ppi_tab[] =
> *** 1379,1385 ****
> "COMPUTE_OVERFLOW;",
> "greater_equal = 0;",
> },
> ! { "","", "pmuls Se,Sf,Dg", "0100eeffxxyygguu",
> "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
> "if (res == 0x80000000)",
> " res = 0x7fffffff;",
> --- 1581,1587 ----
> "COMPUTE_OVERFLOW;",
> "greater_equal = 0;",
> },
> ! { "","", "pmuls Se,Sf,Dg", "0100eeff0000gguu",
> "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
> "if (res == 0x80000000)",
> " res = 0x7fffffff;",
According to the sh2-dsp manual that is still at the Renesas web site,
the xx / yy fields are still present in the pmuls instruction.
> printf ("ppi_insn (iword)\n");
> printf (" int iword;\n");
> printf ("{\n");
> + printf (" /* 'ee' = [x0, x1, y0, a1] (FIXME [x0, x1, a1, m1]) */\n");
> printf (" static char e_tab[] = { 8, 9, 10, 5};\n");
> + printf (" /* 'ff' = [y0, y1, x0, a1] (FIXME [y0, y1, a1, m1]) */\n");
> printf (" static char f_tab[] = {10, 11, 8, 5};\n");
> + printf (" /* 'xx'(?) = [x0, x1, a0, a1] */\n");
> printf (" static char x_tab[] = { 8, 9, 7, 5};\n");
> + printf (" /* 'yy'(?) = [y0, y1, m0, m1] */\n");
> printf (" static char y_tab[] = {10, 11, 12, 14};\n");
> + printf (" /* 'gg' = [m0, m1, a0, a1] */\n");
> printf (" static char g_tab[] = {12, 14, 7, 5};\n");
> + printf (" /* 'uu' = [x0, y0, a0, a1] (FIXME [m1, x1, a0, a1]) */\n");
> printf (" static char u_tab[] = { 8, 10, 7, 5};\n");
What are theses FIXMEs supposed to mean?
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFA] Add sh4a to sh-sim (2nd iteration)
2004-01-08 16:15 ` [RFA] Add sh4a to sh-sim (2nd iteration) Joern Rennecke
@ 2004-01-08 22:02 ` Michael Snyder
2004-01-09 12:37 ` Joern Rennecke
0 siblings, 1 reply; 14+ messages in thread
From: Michael Snyder @ 2004-01-08 22:02 UTC (permalink / raw)
To: Joern Rennecke; +Cc: amylaar, andrew.stubbs, gdb-patches
Joern Rennecke wrote:
>> (expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit
>> instead of 8-bit table (some insns are ambiguous to 8 bits).
>
>
> You are converting iteration into recursion - I don't see
> what is flat about deep recursion.
Just the code structure -- it's one "loop" shallower.
It's also more consistant with the other expand_opcode
function, in which all the recursions are explicit.
And it's not that deep -- upper limit, 12 levels;
in practice never that many.
>>--- gencode.c 7 Jan 2004 21:38:26 -0000
>>***************
>>*** 1,4 ****
>>! /* Simulator/Opcode generator for the Hitachi Super-H architecture.
>>
>> Written by Steve Chamberlain of Cygnus Support.
>> sac@cygnus.com
>>--- 1,5 ----
>>! /* Simulator/Opcode generator for the Renesas
>>! (formerly Hitachi) Super-H architecture.
>>
>> Written by Steve Chamberlain of Cygnus Support.
>> sac@cygnus.com
>
>
> That should be Renesas (formerly Hitachi) / SuperH Inc SuperH architecture.
OK.
>>+ /* sh4a */
>>+ { "", "", "ftrv <FV_N>", "1111vv0111111101",
>>+ "if (FPSCR_PR)",
>>+ " RAISE_EXCEPTION (SIGILL);",
>>+ "else",
>>+ "{",
>>+ " /* FIXME not implemented. */",
>>+ " printf (\"ftrv xmtrx, FV%d\\n\", v1);",
>>+ "}",
>>+ },
>
>
> ftrv is an sh4 instruction.
OK.
>> { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
>> "MA (1);",
>> "DBR = RLAT (R[n]);",
>> "R[n] += 4;",
>> "/* FIXME: user mode */",
>> },
>>! { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
>>! "if (SR_MD)",
>>! "{ /* priv mode */",
>>! " MA (1);",
>>! " DBR = RLAT (R[n]);",
>>! " R[n] += 4;",
>>! "}",
>>! "else",
>>! " RAISE_EXCEPTION (SIGILL); /* user mode */",
>>! },
>
>
> Why do you keep the old "ldc.l @<REG_N>+,DBR" version around?
Good question. Assume that I will delete it, unles I say otherwise.
>>! { "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
>>! "MACL = ((int) R[n]) * ((int) R[m]);",
>> },
>
>
> The #if 0 was left there as a reminder that the casts to int are not fully
> portable. The casts should be replaced with the SEXT32 macro.
OK, I'll either put them back or do the replacement.
If I put them back, I'll add this as a comment.
>>! { "", "n", "movx.w @<REG_xy>,<DSP_XY>", "111100xyXY0001??",
>> "DSP_R (m) = RSWAT (R[n]) << 16;",
>>! "if (iword & 3)",
>>! " {",
>>! " iword &= 0xfd53; goto top;",
>>! " }",
>>! },
>
>
> I think I understand the way the new move instructions were added a bit
> better now.
> The implementation could be made faster by having the movx/nopy
> patterns separate, but I suppose speed is not such an issue for sh-dsp
> simulation, seeing that we don't have time-intensive testcases that
> use dsp move instructions.
Shall we commit it as is for now, and save speed improvements
for a later round?
>
>
>>*************** op ppi_tab[] =
>>*** 1379,1385 ****
>> "COMPUTE_OVERFLOW;",
>> "greater_equal = 0;",
>> },
>>! { "","", "pmuls Se,Sf,Dg", "0100eeffxxyygguu",
>> "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
>> "if (res == 0x80000000)",
>> " res = 0x7fffffff;",
>>--- 1581,1587 ----
>> "COMPUTE_OVERFLOW;",
>> "greater_equal = 0;",
>> },
>>! { "","", "pmuls Se,Sf,Dg", "0100eeff0000gguu",
>> "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
>> "if (res == 0x80000000)",
>> " res = 0x7fffffff;",
>
>
> According to the sh2-dsp manual that is still at the Renesas web site,
> the xx / yy fields are still present in the pmuls instruction.
Hmm, well, are they used for anything? I think I took them out to
resolve a conflict with another insn (but I don't remember for sure).
Since there's no corresponding register parameter, and the code
does not use them -- is there any harm? If the other patterns
are not used now, they probably will be someday.
>> printf ("ppi_insn (iword)\n");
>> printf (" int iword;\n");
>> printf ("{\n");
>>+ printf (" /* 'ee' = [x0, x1, y0, a1] (FIXME [x0, x1, a1, m1]) */\n");
>> printf (" static char e_tab[] = { 8, 9, 10, 5};\n");
>>+ printf (" /* 'ff' = [y0, y1, x0, a1] (FIXME [y0, y1, a1, m1]) */\n");
>> printf (" static char f_tab[] = {10, 11, 8, 5};\n");
>>+ printf (" /* 'xx'(?) = [x0, x1, a0, a1] */\n");
>> printf (" static char x_tab[] = { 8, 9, 7, 5};\n");
>>+ printf (" /* 'yy'(?) = [y0, y1, m0, m1] */\n");
>> printf (" static char y_tab[] = {10, 11, 12, 14};\n");
>>+ printf (" /* 'gg' = [m0, m1, a0, a1] */\n");
>> printf (" static char g_tab[] = {12, 14, 7, 5};\n");
>>+ printf (" /* 'uu' = [x0, y0, a0, a1] (FIXME [m1, x1, a0, a1]) */\n");
>> printf (" static char u_tab[] = { 8, 10, 7, 5};\n");
>
>
> What are these FIXMEs supposed to mean?
I did this work 4 months ago. Probably I thought the
comment was wrong, and that the actual set of registers
was as shown. Your second opinion would be appreciated.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFA] Add sh4a tests to sim/testsuite/sim/sh
2004-01-08 15:07 ` Joern Rennecke
@ 2004-01-08 22:04 ` Michael Snyder
0 siblings, 0 replies; 14+ messages in thread
From: Michael Snyder @ 2004-01-08 22:04 UTC (permalink / raw)
To: Joern Rennecke; +Cc: amylaar, andrew.stubbs, gdb-patches
Joern Rennecke wrote:
>>+ # FIXME I'm not sure if cmp is signed or unsigned.
>>+ # This seems wrong.
>>+ test_qnanm:
>>+ # Test negantive qnan
>>+ fldi0 fr11
>>+ mov.l qnanm, r0
>>+ lds r0, fpul
>>+ fsts fpul, fr0
>>+ fipr fv0, fv8
>>+ # fr11 should be minus qnan (or less)
>>+ flds fr11, fpul
>>+ sts fpul, r1
>>+ cmp/ge r1, r0
>>+ bt .L2
>>+ fail
>>+ .L2:
>
>
> cmp/ge is signed.
> cmp/hs is unsigned.
OK, then the test is OK and I should remove the comment?
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFA] Add sh4a to sh-sim (2nd iteration)
2004-01-08 22:02 ` Michael Snyder
@ 2004-01-09 12:37 ` Joern Rennecke
2004-01-09 19:45 ` Michael Snyder
0 siblings, 1 reply; 14+ messages in thread
From: Joern Rennecke @ 2004-01-09 12:37 UTC (permalink / raw)
To: Michael Snyder; +Cc: Joern Rennecke, amylaar, andrew.stubbs, gdb-patches
> Shall we commit it as is for now, and save speed improvements
> for a later round?
Ok.
> >>*************** op ppi_tab[] =
> >>*** 1379,1385 ****
> >> "COMPUTE_OVERFLOW;",
> >> "greater_equal = 0;",
> >> },
> >>! { "","", "pmuls Se,Sf,Dg", "0100eeffxxyygguu",
> >> "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
> >> "if (res == 0x80000000)",
> >> " res = 0x7fffffff;",
> >>--- 1581,1587 ----
> >> "COMPUTE_OVERFLOW;",
> >> "greater_equal = 0;",
> >> },
> >>! { "","", "pmuls Se,Sf,Dg", "0100eeff0000gguu",
> >> "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
> >> "if (res == 0x80000000)",
> >> " res = 0x7fffffff;",
> >
> >
> > According to the sh2-dsp manual that is still at the Renesas web site,
> > the xx / yy fields are still present in the pmuls instruction.
>
> Hmm, well, are they used for anything? I think I took them out to
> resolve a conflict with another insn (but I don't remember for sure).
> Since there's no corresponding register parameter, and the code
> does not use them -- is there any harm? If the other patterns
> are not used now, they probably will be someday.
According to the manual, because of the ignored x,y,u operands, there are
64 valid pmuls opcodes for each e,f,g combination. I can't find anything
in the manual that says that any one of these opcodes is preferred.
If there is a conflict, it appears that the sh4a-dsp is not actually
backward compatible with the sh3-dsp, and we'll need another opcode table
modification depending on bfd_get_mach. OTOH I seem to remember that we
were asked to zero unused fields in the assembler, but that might be just
to get reproducible results. You should probably ask Renesas for
clarification.
>
>
>
> >> printf ("ppi_insn (iword)\n");
> >> printf (" int iword;\n");
> >> printf ("{\n");
> >>+ printf (" /* 'ee' = [x0, x1, y0, a1] (FIXME [x0, x1, a1, m1]) */\n");
> >> printf (" static char e_tab[] = { 8, 9, 10, 5};\n");
> >>+ printf (" /* 'ff' = [y0, y1, x0, a1] (FIXME [y0, y1, a1, m1]) */\n");
> >> printf (" static char f_tab[] = {10, 11, 8, 5};\n");
> >>+ printf (" /* 'xx'(?) = [x0, x1, a0, a1] */\n");
> >> printf (" static char x_tab[] = { 8, 9, 7, 5};\n");
> >>+ printf (" /* 'yy'(?) = [y0, y1, m0, m1] */\n");
> >> printf (" static char y_tab[] = {10, 11, 12, 14};\n");
> >>+ printf (" /* 'gg' = [m0, m1, a0, a1] */\n");
> >> printf (" static char g_tab[] = {12, 14, 7, 5};\n");
> >>+ printf (" /* 'uu' = [x0, y0, a0, a1] (FIXME [m1, x1, a0, a1]) */\n");
> >> printf (" static char u_tab[] = { 8, 10, 7, 5};\n");
> >
> >
> > What are these FIXMEs supposed to mean?
>
> I did this work 4 months ago. Probably I thought the
> comment was wrong, and that the actual set of registers
> was as shown. Your second opinion would be appreciated.
The first part of the comments is right, the FIXMEs are wrong. The
registers are numbered like in the movs instruction which is the same
as in the the Dz parameter, with A1G / A0G having a number 8 higher
than A1 / A0. See also the macros in interp.c after DSR_R.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFA] Add sh4a tests to sim/testsuite/sim/sh
2004-01-07 22:04 ` [RFA] Add sh4a tests to sim/testsuite/sim/sh Michael Snyder
2004-01-08 15:07 ` Joern Rennecke
@ 2004-01-09 13:19 ` Joern Rennecke
2004-01-09 19:47 ` Michael Snyder
` (2 more replies)
1 sibling, 3 replies; 14+ messages in thread
From: Joern Rennecke @ 2004-01-09 13:19 UTC (permalink / raw)
To: Michael Snyder; +Cc: joern.rennecke, amylaar, andrew.stubbs, gdb-patches
> + test_infm:
> + # Test negitive infinity
negative.
> + fldi0 fr11
> + mov.l infm, r0
> + lds r0, fpul
> + fsts fpul, fr0
> + fipr fv0, fv8
> + # fr11 should be plus infinity
minus.
>> cmp/ge is signed.
>> cmp/hs is unsigned.
>
>OK, then the test is OK and I should remove the comment?
Yes.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFA] Add sh4a to sh-sim (2nd iteration)
2004-01-09 12:37 ` Joern Rennecke
@ 2004-01-09 19:45 ` Michael Snyder
0 siblings, 0 replies; 14+ messages in thread
From: Michael Snyder @ 2004-01-09 19:45 UTC (permalink / raw)
To: Joern Rennecke; +Cc: amylaar, andrew.stubbs, gdb-patches
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Joern Rennecke wrote:
>>>According to the sh2-dsp manual that is still at the Renesas web site,
>>>the xx / yy fields are still present in the pmuls instruction.
>>
>>Hmm, well, are they used for anything? I think I took them out to
>>resolve a conflict with another insn (but I don't remember for sure).
>>Since there's no corresponding register parameter, and the code
>>does not use them -- is there any harm? If the other patterns
>>are not used now, they probably will be someday.
>
>
> According to the manual, because of the ignored x,y,u operands, there are
> 64 valid pmuls opcodes for each e,f,g combination. I can't find anything
> in the manual that says that any one of these opcodes is preferred.
> If there is a conflict, it appears that the sh4a-dsp is not actually
> backward compatible with the sh3-dsp, and we'll need another opcode table
> modification depending on bfd_get_mach. OTOH I seem to remember that we
> were asked to zero unused fields in the assembler, but that might be just
> to get reproducible results. You should probably ask Renesas for
> clarification.
OK, I'll restore the xxyy for now, just to get it committed,
and address it either as it comes up or as clarification obtains.
>>>What are these FIXMEs supposed to mean?
>>
>>I did this work 4 months ago. Probably I thought the
>>comment was wrong, and that the actual set of registers
>>was as shown. Your second opinion would be appreciated.
>
>
> The first part of the comments is right, the FIXMEs are wrong. The
> registers are numbered like in the movs instruction which is the same
> as in the the Dz parameter, with A1G / A0G having a number 8 higher
> than A1 / A0. See also the macros in interp.c after DSR_R.
OK, removing the fixme comments. Committing with changes
as attached below:
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2004-01-07 Michael Snyder <msnyder@redhat.com>
* gencode.c: Replace 'Hitachi' with 'Renesas'.
(op tab): Add new instructions for sh4a, DBR, SBR.
(expand_opcode): Add handling for new movxy combinations.
(gensym_caselist): Ditto.
(expand_ppi_movxy): Remove movx/movy expansions,
now handled in expand_opcode.
(gensym): Add some helpful macros.
(expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit
instead of 8-bit table (some insns are ambiguous to 8 bits).
(ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table.
* interp.c: Replace 'Hitachi' with 'Renesas'.
(union saved_state_type): Add dbr, sgr, ldst.
(get_loop_bounds_ext): New function.
(init_dsp): Add bfd_mach_sh4al_dsp.
(sim_resume): Handle extended loop bounds.
Index: gencode.c
===================================================================
RCS file: /cvs/src/src/sim/sh/gencode.c,v
retrieving revision 1.22
diff -p -r1.22 gencode.c
*** gencode.c 6 Jan 2004 01:05:02 -0000 1.22
--- gencode.c 9 Jan 2004 19:33:38 -0000
***************
*** 1,4 ****
! /* Simulator/Opcode generator for the Hitachi Super-H architecture.
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
--- 1,5 ----
! /* Simulator/Opcode generator for the Renesas
! (formerly Hitachi) / SuperH Inc. Super-H architecture.
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
*************** op tab[] =
*** 151,156 ****
--- 152,162 ----
"SET_SR_T (0);",
},
+ /* sh4a */
+ { "", "", "clrdmxy", "0000000010001000",
+ "saved_state.asregs.cregs.named.sr &= ~(SR_MASK_DMX | SR_MASK_DMY);"
+ },
+
{ "", "0", "cmp/eq #<imm>,R0", "10001000i8*1....",
"SET_SR_T (R0 == SEXT (i));",
},
*************** op tab[] =
*** 195,201 ****
"SET_SR_T (0);",
},
! { "", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100", /* ? MVS */
"div1 (R, m, n/*, T*/);",
},
--- 201,207 ----
"SET_SR_T (0);",
},
! { "", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100",
"div1 (R, m, n/*, T*/);",
},
*************** op tab[] =
*** 285,294 ****
},
/* sh4 */
! { "", "", "fipr <FV_M>,<FV_N>", "1111nnmm11101101",
! "/* FIXME: not implemented */",
! "RAISE_EXCEPTION (SIGILL);",
! "/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh2e */
--- 291,309 ----
},
/* sh4 */
! { "", "", "fipr <FV_M>,<FV_N>", "1111vvVV11101101",
! "if (FPSCR_PR)",
! " RAISE_EXCEPTION (SIGILL);",
! "else",
! "{",
! " double fsum = 0;",
! " /* FIXME: check for nans and infinities. */",
! " fsum += FR (v1+0) * FR (v2+0);",
! " fsum += FR (v1+1) * FR (v2+1);",
! " fsum += FR (v1+2) * FR (v2+2);",
! " fsum += FR (v1+3) * FR (v2+3);",
! " SET_FR (v1+3, fsum);",
! "}",
},
/* sh2e */
*************** op tab[] =
*** 440,445 ****
--- 455,465 ----
"FP_UNARY(n, -);",
},
+ /* sh4a */
+ { "", "", "fpchg", "1111011111111101",
+ "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_PR);",
+ },
+
/* sh4 */
{ "", "", "frchg", "1111101111111101",
"if (FPSCR_PR)",
*************** op tab[] =
*** 498,503 ****
--- 518,534 ----
" FPUL = (int)FR(n);",
},
+ /* sh4 */
+ { "", "", "ftrv <FV_N>", "1111vv0111111101",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ "{",
+ " /* FIXME not implemented. */",
+ " printf (\"ftrv xmtrx, FV%d\\n\", v1);",
+ "}",
+ },
+
/* sh2e */
{ "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101",
" union",
*************** op tab[] =
*** 535,546 ****
{ "", "n", "ldc <REG_N>,MOD", "0100nnnn01011110",
"SET_MOD (R[n]);",
},
- #if 0
{ "", "n", "ldc <REG_N>,DBR", "0100nnnn11111010",
! "DBR = R[n];",
! "/* FIXME: user mode */",
},
- #endif
{ "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
"MA (1);",
"CREG (m) = RLAT (R[n]);",
--- 566,583 ----
{ "", "n", "ldc <REG_N>,MOD", "0100nnnn01011110",
"SET_MOD (R[n]);",
},
{ "", "n", "ldc <REG_N>,DBR", "0100nnnn11111010",
! "if (SR_MD)",
! " DBR = R[n]; /* priv mode */",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
! },
! { "", "n", "ldc <REG_N>,SGR", "0100nnnn00111010",
! "if (SR_MD)",
! " SGR = R[n]; /* priv mode */",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
"MA (1);",
"CREG (m) = RLAT (R[n]);",
*************** op tab[] =
*** 558,571 ****
"SET_MOD (RLAT (R[n]));",
"R[n] += 4;",
},
- #if 0
{ "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
! "MA (1);",
! "DBR = RLAT (R[n]);",
! "R[n] += 4;",
! "/* FIXME: user mode */",
},
- #endif
/* sh-dsp */
{ "", "", "ldre @(<disp>,PC)", "10001110i8p1....",
--- 595,620 ----
"SET_MOD (RLAT (R[n]));",
"R[n] += 4;",
},
{ "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
! "if (SR_MD)",
! "{ /* priv mode */",
! " MA (1);",
! " DBR = RLAT (R[n]);",
! " R[n] += 4;",
! "}",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
! },
! { "n", "n", "ldc.l @<REG_N>+,SGR", "0100nnnn00110110",
! "if (SR_MD)",
! "{ /* priv mode */",
! " MA (1);",
! " SGR = RLAT (R[n]);",
! " R[n] += 4;",
! "}",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
/* sh-dsp */
{ "", "", "ldre @(<disp>,PC)", "10001110i8p1....",
*************** op tab[] =
*** 575,580 ****
--- 624,643 ----
"RS = SEXT (i) * 2 + 4 + PH2T (PC);",
},
+ /* sh4a */
+ { "", "n", "ldrc <REG_N>", "0100nnnn00110100",
+ "SET_RC (R[n]);",
+ "loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);",
+ "CHECK_INSN_PTR (insn_ptr);",
+ "RE |= 1;",
+ },
+ { "", "", "ldrc #<imm>", "10001010i8*1....",
+ "SET_RC (i);",
+ "loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);",
+ "CHECK_INSN_PTR (insn_ptr);",
+ "RE |= 1;",
+ },
+
{ "", "n", "lds <REG_N>,<SREG_M>", "0100nnnnssss1010",
"SREG (m) = R[n];",
},
*************** op tab[] =
*** 777,790 ****
"WLAT (R[n], R[0]);",
},
{ "n", "", "movt <REG_N>", "0000nnnn00101001",
"R[n] = T;",
},
{ "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
! "MACL = ((int)R[n]) * ((int)R[m]);",
},
! #if 0
{ "", "nm", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
"MACL = R[n] * R[m];",
},
--- 840,888 ----
"WLAT (R[n], R[0]);",
},
+ { "n", "0", "movco.l R0, @<REG_N>", "0000nnnn01110011",
+ "/* LDST -> T */",
+ "SET_SR_T (LDST);",
+ "/* if (T) R0 -> (Rn) */",
+ "if (T)",
+ " WLAT (R[n], R[0]);",
+ "/* 0 -> LDST */",
+ "SET_LDST (0);",
+ },
+
+ { "0", "n", "movli.l @<REG_N>, R0", "0000nnnn01100011",
+ "/* 1 -> LDST */",
+ "SET_LDST (1);",
+ "/* (Rn) -> R0 */",
+ "R[0] = RLAT (R[n]);",
+ "/* if (interrupt/exception) 0 -> LDST */",
+ "/* (we don't simulate asynchronous interrupts/exceptions) */",
+ },
+
{ "n", "", "movt <REG_N>", "0000nnnn00101001",
"R[n] = T;",
},
+ { "0", "n", "movua.l @<REG_N>,R0", "0100nnnn10101001",
+ "int regn = R[n];",
+ "MA (1);",
+ "R[0] = (RBAT (regn) << 24) + (RBAT (regn + 1) << 16) + ",
+ " (RBAT (regn + 2) << 8) + RBAT (regn + 3);",
+ "L (n);",
+ },
+ { "0n", "n", "movua.l @<REG_N>+,R0", "0100nnnn11101001",
+ "int regn = R[n];",
+ "MA (1);",
+ "R[0] = (RBAT (regn) << 24) + (RBAT (regn + 1) << 16) + ",
+ " (RBAT (regn + 2) << 8) + RBAT (regn + 3);",
+ "R[n] += 4;",
+ "L (n);",
+ },
{ "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
! "MACL = ((int) R[n]) * ((int) R[m]);",
},
! #if 0 /* FIXME: The above cast to int is not really portable.
! It should be replaced by a SEXT32 macro. */
{ "", "nm", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
"MACL = R[n] * R[m];",
},
*************** op tab[] =
*** 820,825 ****
--- 918,929 ----
"R[n] = ~R[m];",
},
+ /* sh4a */
+ { "", "n", "icbi @<REG_N>", "0000nnnn11100011",
+ "/* Except for the effect on the cache - which is not simulated -",
+ " this is like a nop. */",
+ },
+
{ "", "n", "ocbi @<REG_N>", "0000nnnn10010011",
"RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */",
"/* FIXME: Cache not implemented */",
*************** op tab[] =
*** 851,856 ****
--- 955,972 ----
" this is like a nop. */",
},
+ /* sh4a */
+ { "", "n", "prefi @<REG_N>", "0000nnnn11010011",
+ "/* Except for the effect on the cache - which is not simulated -",
+ " this is like a nop. */",
+ },
+
+ /* sh4a */
+ { "", "", "synco", "0000000010101011",
+ "/* Except for the effect on the pipeline - which is not simulated -",
+ " this is like a nop. */",
+ },
+
{ "n", "n", "rotcl <REG_N>", "0100nnnn00100100",
"ult = R[n] < 0;",
"R[n] = (R[n] << 1) | T;",
*************** op tab[] =
*** 898,903 ****
--- 1014,1031 ----
"Delay_Slot (PC + 2);",
},
+ /* sh4a */
+ { "", "", "setdmx", "0000000010011000",
+ "saved_state.asregs.cregs.named.sr |= SR_MASK_DMX;"
+ "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMY;"
+ },
+
+ /* sh4a */
+ { "", "", "setdmy", "0000000011001000",
+ "saved_state.asregs.cregs.named.sr |= SR_MASK_DMY;"
+ "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMX;"
+ },
+
/* sh-dsp */
{ "", "n", "setrc <REG_N>", "0100nnnn00010100",
"SET_RC (R[n]);",
*************** op tab[] =
*** 980,1010 ****
"R[n] = CREG (m);",
},
- #if 0
{ "n", "", "stc SGR,<REG_N>", "0000nnnn00111010",
! "R[n] = SGR;",
},
{ "n", "", "stc DBR,<REG_N>", "0000nnnn11111010",
! "R[n] = DBR;",
},
- #endif
{ "n", "n", "stc.l <CREG_M>,@-<REG_N>", "0100nnnnmmmm0011",
"MA (1);",
"R[n] -= 4;",
"WLAT (R[n], CREG (m));",
},
- #if 0
{ "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010",
! "MA (1);",
! "R[n] -= 4;",
! "WLAT (R[n], SGR);",
},
{ "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010",
! "MA (1);",
! "R[n] -= 4;",
! "WLAT (R[n], DBR);",
},
- #endif
{ "n", "", "sts <SREG_M>,<REG_N>", "0000nnnnssss1010",
"R[n] = SREG (m);",
--- 1108,1150 ----
"R[n] = CREG (m);",
},
{ "n", "", "stc SGR,<REG_N>", "0000nnnn00111010",
! "if (SR_MD)",
! " R[n] = SGR; /* priv mode */",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "", "stc DBR,<REG_N>", "0000nnnn11111010",
! "if (SR_MD)",
! " R[n] = DBR; /* priv mode */",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "n", "stc.l <CREG_M>,@-<REG_N>", "0100nnnnmmmm0011",
"MA (1);",
"R[n] -= 4;",
"WLAT (R[n], CREG (m));",
},
{ "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010",
! "if (SR_MD)",
! "{ /* priv mode */",
! " MA (1);",
! " R[n] -= 4;",
! " WLAT (R[n], SGR);",
! "}",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010",
! "if (SR_MD)",
! "{ /* priv mode */",
! " MA (1);",
! " R[n] -= 4;",
! " WLAT (R[n], DBR);",
! "}",
! "else",
! " RAISE_EXCEPTION (SIGILL); /* user mode */",
},
{ "n", "", "sts <SREG_M>,<REG_N>", "0000nnnnssss1010",
"R[n] = SREG (m);",
*************** op movsxy_tab[] =
*** 1258,1313 ****
"WLAT (R[n], SEXT (DSP_R (m)));",
"R[n] += R[8];",
},
! { "", "n", "movx.w @<REG_x>,<DSP_XX>", "111100xxXX000100",
"DSP_R (m) = RSWAT (R[n]) << 16;",
! "iword &= 0xfd53; goto top;",
},
! { "n", "n", "movx.w @<REG_x>+,<DSP_XX>", "111100xxXX001000",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
! "iword &= 0xfd53; goto top;",
},
! { "n", "n8","movx.w @<REG_x>+REG_8,<DSP_XX>", "111100xxXX001100",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
! "iword &= 0xfd53; goto top;",
},
! { "", "n", "movx.w <DSP_Aa>,@<REG_x>", "111100xxaa100100",
"WWAT (R[n], DSP_R (m) >> 16);",
! "iword &= 0xfd53; goto top;",
},
! { "n", "n", "movx.w <DSP_Aa>,@<REG_x>+", "111100xxaa101000",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
! "iword &= 0xfd53; goto top;",
},
! { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101100",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
! "iword &= 0xfd53; goto top;",
},
! { "", "n", "movy.w @<REG_y>,<DSP_YY>", "111100yyYY000001",
"DSP_R (m) = RSWAT (R[n]) << 16;",
},
! { "n", "n", "movy.w @<REG_y>+,<DSP_YY>", "111100yyYY000010",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
! { "n", "n9","movy.w @<REG_y>+REG_9,<DSP_YY>", "111100yyYY000011",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
! { "", "n", "movy.w <DSP_Aa>,@<REG_y>", "111100yyAA010001",
"WWAT (R[n], DSP_R (m) >> 16);",
},
! { "n", "n", "movy.w <DSP_Aa>,@<REG_y>+", "111100yyAA010010",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
! { "n", "n9", "movy.w <DSP_Aa>,@<REG_y>+REG_9", "111100yyAA010011",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
{ "", "", "nopx nopy", "1111000000000000",
"/* nop */",
},
--- 1398,1515 ----
"WLAT (R[n], SEXT (DSP_R (m)));",
"R[n] += R[8];",
},
! { "", "n", "movx.w @<REG_xy>,<DSP_XY>", "111100xyXY0001??",
"DSP_R (m) = RSWAT (R[n]) << 16;",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "", "n", "movx.l @<REG_xy>,<DSP_XY>", "111100xyXY010100",
! "DSP_R (m) = RLAT (R[n]);",
},
! { "n", "n", "movx.w @<REG_xy>+,<DSP_XY>", "111100xyXY0010??",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "n", "n", "movx.l @<REG_xy>+,<DSP_XY>", "111100xyXY011000",
! "DSP_R (m) = RLAT (R[n]);",
! "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 4;",
},
! { "n", "n8","movx.w @<REG_xy>+REG_8,<DSP_XY>", "111100xyXY0011??",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "n", "n8","movx.l @<REG_xy>+REG_8,<DSP_XY>", "111100xyXY011100",
! "DSP_R (m) = RLAT (R[n]);",
! "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
},
! { "", "n", "movx.w <DSP_Ax>,@<REG_xy>", "111100xyax1001??",
"WWAT (R[n], DSP_R (m) >> 16);",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "", "n", "movx.l <DSP_Ax>,@<REG_xy>", "111100xyax110100",
! "WLAT (R[n], DSP_R (m));",
},
! { "n", "n", "movx.w <DSP_Ax>,@<REG_xy>+", "111100xyax1010??",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
},
! { "n", "n", "movx.l <DSP_Ax>,@<REG_xy>+", "111100xyax111000",
! "WLAT (R[n], DSP_R (m));",
! "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 4;",
! },
! { "n", "n8","movx.w <DSP_Ax>,@<REG_xy>+REG_8","111100xyax1011??",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
! "if (iword & 3)",
! " {",
! " iword &= 0xfd53; goto top;",
! " }",
! },
! { "n", "n8","movx.l <DSP_Ax>,@<REG_xy>+REG_8","111100xyax111100",
! "WLAT (R[n], DSP_R (m));",
! "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
},
! { "", "n", "movy.w @<REG_yx>,<DSP_YX>", "111100yxYX000001",
"DSP_R (m) = RSWAT (R[n]) << 16;",
},
! { "n", "n", "movy.w @<REG_yx>+,<DSP_YX>", "111100yxYX000010",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
! { "n", "n9","movy.w @<REG_yx>+REG_9,<DSP_YX>", "111100yxYX000011",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
! { "", "n", "movy.w <DSP_Ay>,@<REG_yx>", "111100yxAY010001",
"WWAT (R[n], DSP_R (m) >> 16);",
},
! { "n", "n", "movy.w <DSP_Ay>,@<REG_yx>+", "111100yxAY010010",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
! { "n", "n9", "movy.w <DSP_Ay>,@<REG_yx>+REG_9", "111100yxAY010011",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
+ { "", "n", "movy.l @<REG_yx>,<DSP_YX>", "111100yxYX100001",
+ "DSP_R (m) = RLAT (R[n]);",
+ },
+ { "n", "n", "movy.l @<REG_yx>+,<DSP_YX>", "111100yxYX100010",
+ "DSP_R (m) = RLAT (R[n]);",
+ "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 4;",
+ },
+ { "n", "n9","movy.l @<REG_yx>+REG_9,<DSP_YX>", "111100yxYX100011",
+ "DSP_R (m) = RLAT (R[n]);",
+ "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
+ },
+ { "", "n", "movy.l <DSP_Ay>,@<REG_yx>", "111100yxAY110001",
+ "WLAT (R[n], DSP_R (m));",
+ },
+ { "n", "n", "movy.l <DSP_Ay>,@<REG_yx>+", "111100yxAY110010",
+ "WLAT (R[n], DSP_R (m));",
+ "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 4;",
+ },
+ { "n", "n9", "movy.l <DSP_Ay>,@<REG_yx>+REG_9", "111100yxAY110011",
+ "WLAT (R[n], DSP_R (m));",
+ "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
+ },
{ "", "", "nopx nopy", "1111000000000000",
"/* nop */",
},
*************** op ppi_tab[] =
*** 1462,1468 ****
"DSR |= carry;\n",
"goto assign_z;\n",
},
! { "","", "pcmp Sx,Sy", "10000100xxyy....",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
"int Sy = DSP_R (y);",
--- 1664,1670 ----
"DSR |= carry;\n",
"goto assign_z;\n",
},
! { "","", "pcmp Sx,Sy", "10000100xxyyzzzz",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
"int Sy = DSP_R (y);",
*************** op ppi_tab[] =
*** 1479,1484 ****
--- 1681,1704 ----
},
{ "","", "pwad Sx,Sy,Dz", "10110100xxyyzzzz",
},
+ { "","", "(if cc) pabs Sx,Dz", "100010ccxx01zzzz",
+ "/* FIXME: duplicate code pabs. */",
+ "res = DSP_R (x);",
+ "res_grd = GET_DSP_GRD (x);",
+ "if (res >= 0)",
+ " carry = 0;",
+ "else",
+ " {",
+ " res = -res;",
+ " carry = (res != 0); /* The manual has a bug here. */",
+ " res_grd = -res_grd - carry;",
+ " }",
+ "COMPUTE_OVERFLOW;",
+ "/* ??? The re-computing of overflow after",
+ " saturation processing is specific to pabs. */",
+ "overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0;",
+ "ADD_SUB_GE;",
+ },
{ "","", "pabs Sx,Dz", "10001000xx..zzzz",
"res = DSP_R (x);",
"res_grd = GET_DSP_GRD (x);",
*************** op ppi_tab[] =
*** 1496,1501 ****
--- 1716,1733 ----
"overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0;",
"ADD_SUB_GE;",
},
+
+ { "","", "(if cc) prnd Sx,Dz", "100110ccxx01zzzz",
+ "/* FIXME: duplicate code prnd. */",
+ "int Sx = DSP_R (x);",
+ "int Sx_grd = GET_DSP_GRD (x);",
+ "",
+ "res = (Sx + 0x8000) & 0xffff0000;",
+ "carry = (unsigned) res < (unsigned) Sx;",
+ "res_grd = Sx_grd + carry;",
+ "COMPUTE_OVERFLOW;",
+ "ADD_SUB_GE;",
+ },
{ "","", "prnd Sx,Dz", "10011000xx..zzzz",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
*************** op ppi_tab[] =
*** 1506,1511 ****
--- 1738,1768 ----
"COMPUTE_OVERFLOW;",
"ADD_SUB_GE;",
},
+
+ { "","", "(if cc) pabs Sy,Dz", "101010cc01yyzzzz",
+ "/* FIXME: duplicate code pabs. */",
+ "res = DSP_R (y);",
+ "res_grd = 0;",
+ "overflow = 0;",
+ "greater_equal = DSR_MASK_G;",
+ "if (res >= 0)",
+ " carry = 0;",
+ "else",
+ " {",
+ " res = -res;",
+ " carry = 1;",
+ " if (res < 0)",
+ " {",
+ " if (S)",
+ " res = 0x7fffffff;",
+ " else",
+ " {",
+ " overflow = DSR_MASK_V;",
+ " greater_equal = 0;",
+ " }",
+ " }",
+ " }",
+ },
{ "","", "pabs Sy,Dz", "10101000..yyzzzz",
"res = DSP_R (y);",
"res_grd = 0;",
*************** op ppi_tab[] =
*** 1529,1534 ****
--- 1786,1802 ----
" }",
" }",
},
+ { "","", "(if cc) prnd Sy,Dz", "101110cc01yyzzzz",
+ "/* FIXME: duplicate code prnd. */",
+ "int Sy = DSP_R (y);",
+ "int Sy_grd = SIGN32 (Sy);",
+ "",
+ "res = (Sy + 0x8000) & 0xffff0000;",
+ "carry = (unsigned) res < (unsigned) Sy;",
+ "res_grd = Sy_grd + carry;",
+ "COMPUTE_OVERFLOW;",
+ "ADD_SUB_GE;",
+ },
{ "","", "prnd Sy,Dz", "10111000..yyzzzz",
"int Sy = DSP_R (y);",
"int Sy_grd = SIGN32 (Sy);",
*************** op ppi_tab[] =
*** 1609,1614 ****
--- 1877,1894 ----
"COMPUTE_OVERFLOW;",
"ADD_SUB_GE;",
},
+ { "","", "(if cc) psub Sy,Sx,Dz", "100001ccxxyyzzzz",
+ "int Sx = DSP_R (x);",
+ "int Sx_grd = GET_DSP_GRD (x);",
+ "int Sy = DSP_R (y);",
+ "int Sy_grd = SIGN32 (Sy);",
+ "",
+ "res = Sy - Sx;",
+ "carry = (unsigned) res > (unsigned) Sy;",
+ "res_grd = Sy_grd - Sx_grd - carry;",
+ "COMPUTE_OVERFLOW;",
+ "ADD_SUB_GE;",
+ },
{ "","", "(if cc) padd Sx,Sy,Dz", "101100ccxxyyzzzz",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
*************** op ppi_tab[] =
*** 1698,1703 ****
--- 1978,1998 ----
"overflow = 0;",
"greater_equal = 1;",
},
+ { "","", "pclr Du pmuls Se,Sf,Dg", "0100eeff0001gguu",
+ "/* Do multiply. */",
+ "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
+ "if (res == 0x80000000)",
+ " res = 0x7fffffff;",
+ "DSP_R (g) = res;",
+ "DSP_GRD (g) = SIGN32 (res);",
+ "/* FIXME: update DSR based on results of multiply! */",
+ "",
+ "/* Do clr. */",
+ "z = u;",
+ "res = 0;",
+ "res_grd = 0;",
+ "goto assign_z;",
+ },
{ "","", "(if cc) pdmsb Sx,Dz", "100111ccxx..zzzz",
"unsigned Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
*************** op ppi_tab[] =
*** 1813,1818 ****
--- 2108,2134 ----
" MACL = DSP_R (z) = res;",
"return;",
},
+ /* sh4a */
+ { "","", "(if cc) pswap Sx,Dz", "100111ccxx01zzzz",
+ "int Sx = DSP_R (x);",
+ "",
+ "res = ((Sx & 0xffff) * 65536) + ((Sx >> 16) & 0xffff);",
+ "res_grd = GET_DSP_GRD (x);",
+ "carry = 0;",
+ "overflow = 0;",
+ "greater_equal = res & 0x80000000 ? 0 : DSR_MASK_G;",
+ },
+ /* sh4a */
+ { "","", "(if cc) pswap Sy,Dz", "101111cc01yyzzzz",
+ "int Sy = DSP_R (y);",
+ "",
+ "res = ((Sy & 0xffff) * 65536) + ((Sy >> 16) & 0xffff);",
+ "res_grd = SIGN32 (Sy);",
+ "carry = 0;",
+ "overflow = 0;",
+ "greater_equal = res & 0x80000000 ? 0 : DSR_MASK_G;",
+ },
+
{0, 0}
};
*************** expand_opcode (val, i, s)
*** 1976,2001 ****
exit (1);
case '0':
case '1':
! /* Consume an arbitrary number of ones and zeros. */
! do {
! j = (j << 1) + (s[m++] - '0');
! } while (s[m] == '0' || s[m] == '1');
! expand_opcode ((val << m) | j, i, s + m);
! break;
!
case 'N': /* NN -- four-way fork */
for (j = 0; j < 4; j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
! case 'x': /* xx -- 2-way fork */
! /* Cross-breeding with movy moved to separate function. */
! for (j = 0; j < 4; j += 2)
expand_opcode ((val << 2) | j, i, s + 2);
break;
! case 'y': /* yy -- two-way fork */
! for (j = 0; j < 2; j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
case 'i': /* eg. "i8*1" */
case '.': /* "...." is a wildcard */
case 'n':
--- 2292,2323 ----
exit (1);
case '0':
case '1':
! /* Consume an arbitrary number of ones and zeros. */
! do {
! j = (j << 1) + (s[m++] - '0');
! } while (s[m] == '0' || s[m] == '1');
! expand_opcode ((val << m) | j, i, s + m);
! break;
case 'N': /* NN -- four-way fork */
for (j = 0; j < 4; j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
! case 'x': /* xx or xy -- two-way or four-way fork */
! for (j = 0; j < 4; j += (s[1] == 'x' ? 2 : 1))
expand_opcode ((val << 2) | j, i, s + 2);
break;
! case 'y': /* yy or yx -- two-way or four-way fork */
! for (j = 0; j < (s[1] == 'x' ? 4 : 2); j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
+ case '?': /* Seven-way "wildcard" fork for movxy */
+ expand_opcode ((val << 2), i, s + 2);
+ for (j = 1; j < 4; j++)
+ {
+ expand_opcode ((val << 2) | j, i, s + 2);
+ expand_opcode ((val << 2) | (j + 16), i, s + 2);
+ }
+ break;
case 'i': /* eg. "i8*1" */
case '.': /* "...." is a wildcard */
case 'n':
*************** expand_opcode (val, i, s)
*** 2033,2049 ****
expand_opcode ((val << 4) | j, i, s + 4);
break;
case 'X':
case 'a':
! /* XX, aa -- two-way fork */
! for (j = 0; j < 4; j += 2)
expand_opcode ((val << 2) | j, i, s + 2);
break;
case 'Y':
case 'A':
! /* YY, AA -- two-way fork */
! for (j = 0; j < 2; j++)
expand_opcode ((val << 2) | j, i, s + 2);
break;
}
}
}
--- 2355,2395 ----
expand_opcode ((val << 4) | j, i, s + 4);
break;
case 'X':
+ /* XX/XY -- 2/4 way fork. */
+ for (j = 0; j < 4; j += (s[1] == 'X' ? 2 : 1))
+ expand_opcode ((val << 2) | j, i, s + 2);
+ break;
case 'a':
! /* aa/ax -- 2/4 way fork. */
! for (j = 0; j < 4; j += (s[1] == 'a' ? 2 : 1))
expand_opcode ((val << 2) | j, i, s + 2);
break;
case 'Y':
+ /* YY/YX -- 2/4 way fork. */
+ for (j = 0; j < (s[1] == 'Y' ? 2 : 4); j += 1)
+ expand_opcode ((val << 2) | j, i, s + 2);
+ break;
case 'A':
! /* AA/AY: 2/4 way fork. */
! for (j = 0; j < (s[1] == 'A' ? 2 : 4); j += 1)
expand_opcode ((val << 2) | j, i, s + 2);
break;
+ case 'v':
+ /* vv(VV) -- 4(16) way fork. */
+ /* Vector register fv0/4/8/12. */
+ if (s[2] == 'V')
+ {
+ /* 2 vector registers. */
+ for (j = 0; j < 15; j++)
+ expand_opcode ((val << 4) | j, i, s + 4);
+ }
+ else
+ {
+ /* 1 vector register. */
+ for (j = 0; j < 4; j += 1)
+ expand_opcode ((val << 2) | j, i, s + 2);
+ }
+ break;
}
}
}
*************** expand_ppi_movxy ()
*** 2113,2136 ****
int i;
for (i = 0xf000; i < 0xf400; i++)
- if ((i & 3) == 0 && (i & 12) != 0 && table[i] != 0)
- {
- /* A movx insn, which needs to be filled out with the
- corresponding movy insns. This used to be done in
- expand_opcode. */
- int m, mv;
-
- for (m = 0; m < 32; m++)
- {
- /* Ignore illegal nopy */
- if ((m & 7) == 0 && m != 0)
- continue;
- mv = m & 3 | (m & 4) << 2 | (m & 8) << 3 | (m & 16) << 4;
- table [i | mv] = table [i];
- }
- }
-
- for (i = 0xf000; i < 0xf400; i++)
if (table[i])
table[i + 0x800] = table[0xf800];
}
--- 2459,2464 ----
*************** gensim_caselist (p)
*** 2161,2166 ****
--- 2489,2506 ----
*s);
exit (1);
break;
+ case '?':
+ /* Wildcard expansion, nothing to do here. */
+ s += 2;
+ break;
+ case 'v':
+ printf (" int v1 = ((iword >> 10) & 3) * 4;\n");
+ s += 2;
+ break;
+ case 'V':
+ printf (" int v2 = ((iword >> 8) & 3) * 4;\n");
+ s += 2;
+ break;
case '0':
case '1':
s += 2;
*************** gensim_caselist (p)
*** 2179,2190 ****
s += 2;
break;
case 'x':
! printf (" int n = ((iword >> 9) & 1) + 4;\n");
needn = 1;
s += 2;
break;
case 'y':
! printf (" int n = ((iword >> 8) & 1) + 6;\n");
needn = 1;
s += 2;
break;
--- 2519,2544 ----
s += 2;
break;
case 'x':
! if (s[1] == 'y') /* xy */
! {
! printf (" int n = (iword & 3) ? \n");
! printf (" ((iword >> 9) & 1) + 4 : \n");
! printf (" REG_xy ((iword >> 8) & 3);\n");
! }
! else
! printf (" int n = ((iword >> 9) & 1) + 4;\n");
needn = 1;
s += 2;
break;
case 'y':
! if (s[1] == 'x') /* yx */
! {
! printf (" int n = (iword & 0xc) ? \n");
! printf (" ((iword >> 8) & 1) + 6 : \n");
! printf (" REG_yx ((iword >> 8) & 3);\n");
! }
! else
! printf (" int n = ((iword >> 8) & 1) + 6;\n");
needn = 1;
s += 2;
break;
*************** gensim_caselist (p)
*** 2197,2215 ****
s += 4;
break;
case 'X':
! printf (" int m = ((iword >> 7) & 1) + 8;\n");
s += 2;
break;
case 'a':
! printf (" int m = 7 - ((iword >> 6) & 2);\n");
s += 2;
break;
case 'Y':
! printf (" int m = ((iword >> 6) & 1) + 10;\n");
s += 2;
break;
case 'A':
! printf (" int m = 7 - ((iword >> 5) & 2);\n");
s += 2;
break;
--- 2551,2597 ----
s += 4;
break;
case 'X':
! if (s[1] == 'Y') /* XY */
! {
! printf (" int m = (iword & 3) ? \n");
! printf (" ((iword >> 7) & 1) + 8 : \n");
! printf (" DSP_xy ((iword >> 6) & 3);\n");
! }
! else
! printf (" int m = ((iword >> 7) & 1) + 8;\n");
s += 2;
break;
case 'a':
! if (s[1] == 'x') /* ax */
! {
! printf (" int m = (iword & 3) ? \n");
! printf (" 7 - ((iword >> 6) & 2) : \n");
! printf (" DSP_ax ((iword >> 6) & 3);\n");
! }
! else
! printf (" int m = 7 - ((iword >> 6) & 2);\n");
s += 2;
break;
case 'Y':
! if (s[1] == 'X') /* YX */
! {
! printf (" int m = (iword & 0xc) ? \n");
! printf (" ((iword >> 6) & 1) + 10 : \n");
! printf (" DSP_yx ((iword >> 6) & 3);\n");
! }
! else
! printf (" int m = ((iword >> 6) & 1) + 10;\n");
s += 2;
break;
case 'A':
! if (s[1] == 'Y') /* AY */
! {
! printf (" int m = (iword & 0xc) ? \n");
! printf (" 7 - ((iword >> 5) & 2) : \n");
! printf (" DSP_ay ((iword >> 6) & 3);\n");
! }
! else
! printf (" int m = 7 - ((iword >> 5) & 2);\n");
s += 2;
break;
*************** static void
*** 2303,2308 ****
--- 2685,2702 ----
gensim ()
{
printf ("{\n");
+ printf ("/* REG_xy = [r4, r5, r0, r1]. */\n");
+ printf ("#define REG_xy(R) ((R)==0 ? 4 : (R)==2 ? 5 : (R)==1 ? 0 : 1)\n");
+ printf ("/* REG_yx = [r6, r7, r2, r3]. */\n");
+ printf ("#define REG_yx(R) ((R)==0 ? 6 : (R)==1 ? 7 : (R)==2 ? 2 : 3)\n");
+ printf ("/* DSP_ax = [a0, a1, x0, x1]. */\n");
+ printf ("#define DSP_ax(R) ((R)==0 ? 7 : (R)==2 ? 5 : (R)==1 ? 8 : 9)\n");
+ printf ("/* DSP_ay = [a0, a1, y0, y1]. */\n");
+ printf ("#define DSP_ay(R) ((R)==0 ? 7 : (R)==1 ? 5 : (R)==2 ? 10 : 11)\n");
+ printf ("/* DSP_xy = [x0, x1, y0, y1]. */\n");
+ printf ("#define DSP_xy(R) ((R)==0 ? 8 : (R)==2 ? 9 : (R)==1 ? 10 : 11)\n");
+ printf ("/* DSP_yx = [y0, y1, x0, x1]. */\n");
+ printf ("#define DSP_yx(R) ((R)==0 ? 10 : (R)==1 ? 11 : (R)==2 ? 8 : 9)\n");
printf (" switch (jump_table[iword]) {\n");
gensim_caselist (tab);
*************** gendefines ()
*** 2341,2347 ****
static int ppi_index;
/* Take a ppi code, expand all varying fields in it and fill all the
! right entries in 'table' with the opcode index. */
static void
expand_ppi_code (val, i, s)
--- 2735,2742 ----
static int ppi_index;
/* Take a ppi code, expand all varying fields in it and fill all the
! right entries in 'table' with the opcode index.
! NOTE: tail recursion optimization removed for simplicity. */
static void
expand_ppi_code (val, i, s)
*************** expand_ppi_code (val, i, s)
*** 2351,2396 ****
{
int j;
! for (;;)
{
! switch (s[0])
! {
! default:
! fprintf (stderr, "gencode/expand_ppi_code: Illegal char '%c'\n",
! s[0]);
! exit (2);
! break;
! /* The last eight bits are disregarded for the switch table. */
! case 'm':
! case 'x':
! case '.':
! table[val] = i;
! return;
! case '0':
! val += val;
! s++;
! break;
! case '1':
! val += val + 1;
! s++;
! break;
! case 'i':
! case 'e': case 'f':
! val += val;
! s++;
! expand_ppi_code (val, i, s);
! val++;
! break;
! case 'c':
! val <<= 2;
! s += 2;
! val++;
! expand_ppi_code (val, ppi_index++, s);
! val++;
! expand_ppi_code (val, i, s);
! val++;
! break;
! }
}
}
--- 2746,2785 ----
{
int j;
! switch (s[0])
{
! default:
! fprintf (stderr, "gencode/expand_ppi_code: Illegal char '%c'\n", s[0]);
! exit (2);
! break;
! case 'g':
! case 'z':
! /* The last four bits are disregarded for the switch table. */
! table[val] = i;
! return;
! case 'm':
! /* Four-bit expansion. */
! for (j = 0; j < 16; j++)
! expand_ppi_code ((val << 4) + j, i, s + 4);
! break;
! case '.':
! case '0':
! expand_ppi_code ((val << 1), i, s + 1);
! break;
! case '1':
! expand_ppi_code ((val << 1) + 1, i, s + 1);
! break;
! case 'i':
! case 'e': case 'f':
! case 'x': case 'y':
! expand_ppi_code ((val << 1), i, s + 1);
! expand_ppi_code ((val << 1) + 1, i, s + 1);
! break;
! case 'c':
! expand_ppi_code ((val << 2) + 1, ppi_index++, s + 2);
! expand_ppi_code ((val << 2) + 2, i, s + 2);
! expand_ppi_code ((val << 2) + 3, i, s + 2);
! break;
}
}
*************** ppi_gensim ()
*** 2442,2459 ****
printf ("ppi_insn (iword)\n");
printf (" int iword;\n");
printf ("{\n");
printf (" static char e_tab[] = { 8, 9, 10, 5};\n");
printf (" static char f_tab[] = {10, 11, 8, 5};\n");
printf (" static char x_tab[] = { 8, 9, 7, 5};\n");
printf (" static char y_tab[] = {10, 11, 12, 14};\n");
printf (" static char g_tab[] = {12, 14, 7, 5};\n");
printf (" static char u_tab[] = { 8, 10, 7, 5};\n");
printf ("\n");
printf (" int z;\n");
printf (" int res, res_grd;\n");
printf (" int carry, overflow, greater_equal;\n");
printf ("\n");
! printf (" switch (ppi_table[iword >> 8]) {\n");
for (; p->name; p++)
{
--- 2831,2854 ----
printf ("ppi_insn (iword)\n");
printf (" int iword;\n");
printf ("{\n");
+ printf (" /* 'ee' = [x0, x1, y0, a1] */\n");
printf (" static char e_tab[] = { 8, 9, 10, 5};\n");
+ printf (" /* 'ff' = [y0, y1, x0, a1] */\n");
printf (" static char f_tab[] = {10, 11, 8, 5};\n");
+ printf (" /* 'xx' = [x0, x1, a0, a1] */\n");
printf (" static char x_tab[] = { 8, 9, 7, 5};\n");
+ printf (" /* 'yy' = [y0, y1, m0, m1] */\n");
printf (" static char y_tab[] = {10, 11, 12, 14};\n");
+ printf (" /* 'gg' = [m0, m1, a0, a1] */\n");
printf (" static char g_tab[] = {12, 14, 7, 5};\n");
+ printf (" /* 'uu' = [x0, y0, a0, a1] */\n");
printf (" static char u_tab[] = { 8, 10, 7, 5};\n");
printf ("\n");
printf (" int z;\n");
printf (" int res, res_grd;\n");
printf (" int carry, overflow, greater_equal;\n");
printf ("\n");
! printf (" switch (ppi_table[iword >> 4]) {\n");
for (; p->name; p++)
{
*************** main (ac, av)
*** 2614,2620 ****
memset (table, 0, sizeof table);
ppi_filltable ();
! dumptable ("ppi_table", 1 << 8, 0);
}
else if (strcmp (av[1], "-x") == 0)
{
--- 3009,3015 ----
memset (table, 0, sizeof table);
ppi_filltable ();
! dumptable ("ppi_table", 1 << 12, 0);
}
else if (strcmp (av[1], "-x") == 0)
{
Index: interp.c
===================================================================
RCS file: /cvs/src/src/sim/sh/interp.c,v
retrieving revision 1.12
diff -p -r1.12 interp.c
*** interp.c 3 Nov 2003 14:14:15 -0000 1.12
--- interp.c 9 Jan 2004 19:33:38 -0000
***************
*** 1,4 ****
! /* Simulator for the Hitachi SH architecture.
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
--- 1,4 ----
! /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
*************** typedef union
*** 120,125 ****
--- 120,128 ----
int re;
/* sh3 */
int bank[8];
+ int dbr; /* debug base register */
+ int sgr; /* saved gr15 */
+ int ldst; /* load/store flag (boolean) */
} named;
int i[16];
} cregs;
*************** static int target_dsp;
*** 167,176 ****
static int host_little_endian;
static char **prog_argv;
- #if 1
static int maskw = 0;
static int maskl = 0;
- #endif
static SIM_OPEN_KIND sim_kind;
static char *myname;
--- 170,177 ----
*************** static char *myname;
*** 189,196 ****
--- 190,199 ----
#define CREG(n) (saved_state.asregs.cregs.i[(n)])
#define GBR saved_state.asregs.cregs.named.gbr
#define VBR saved_state.asregs.cregs.named.vbr
+ #define DBR saved_state.asregs.cregs.named.dbr
#define SSR saved_state.asregs.cregs.named.ssr
#define SPC saved_state.asregs.cregs.named.spc
+ #define SGR saved_state.asregs.cregs.named.sgr
#define SREG(n) (saved_state.asregs.sregs.i[(n)])
#define MACH saved_state.asregs.sregs.named.mach
#define MACL saved_state.asregs.sregs.named.macl
*************** static char *myname;
*** 228,233 ****
--- 231,237 ----
#define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
#define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
#define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
+ #define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
#define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
#define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
*************** do { \
*** 249,254 ****
--- 253,259 ----
#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
#define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
+ #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
/* stc currently relies on being able to read SR without modifications. */
#define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
*************** macl (regs, memory, n, m)
*** 1411,1416 ****
--- 1416,1447 ----
MACH = mach;
}
+
+ /* GET_LOOP_BOUNDS {EXTENDED}
+ These two functions compute the actual starting and ending point
+ of the repeat loop, based on the RS and RE registers (repeat start,
+ repeat stop). The extended version is called for LDRC, and the
+ regular version is called for SETRC. The difference is that for
+ LDRC, the loop start and end instructions are literally the ones
+ pointed to by RS and RE -- for SETRC, they're not (see docs). */
+
+ static struct loop_bounds
+ get_loop_bounds_ext (rs, re, memory, mem_end, maskw, endianw)
+ int rs, re;
+ unsigned char *memory, *mem_end;
+ int maskw, endianw;
+ {
+ struct loop_bounds loop;
+
+ /* FIXME: should I verify RS < RE? */
+ loop.start = PT2H (RS); /* FIXME not using the params? */
+ loop.end = PT2H (RE & ~1); /* Ignore bit 0 of RE. */
+ SKIP_INSN (loop.end);
+ if (loop.end >= mem_end)
+ loop.end = PT2H (0);
+ return loop;
+ }
+
float
fsca_s (int in, double (*f) (double))
{
*************** init_dsp (abfd)
*** 1541,1547 ****
int was_dsp = target_dsp;
unsigned long mach = bfd_get_mach (abfd);
! if (mach == bfd_mach_sh_dsp || mach == bfd_mach_sh3_dsp)
{
int ram_area_size, xram_start, yram_start;
int new_select;
--- 1572,1580 ----
int was_dsp = target_dsp;
unsigned long mach = bfd_get_mach (abfd);
! if (mach == bfd_mach_sh_dsp ||
! mach == bfd_mach_sh4al_dsp ||
! mach == bfd_mach_sh3_dsp)
{
int ram_area_size, xram_start, yram_start;
int new_select;
*************** init_dsp (abfd)
*** 1556,1562 ****
xram_start = 0x0800f000;
ram_area_size = 0x1000;
}
! if (mach == bfd_mach_sh3_dsp)
{
/* SH7612:
8KB each for X & Y memory;
--- 1589,1595 ----
xram_start = 0x0800f000;
ram_area_size = 0x1000;
}
! if (mach == bfd_mach_sh3_dsp || mach == bfd_mach_sh4al_dsp)
{
/* SH7612:
8KB each for X & Y memory;
*************** sim_resume (sd, step, siggnal)
*** 1740,1746 ****
memory = saved_state.asregs.memory;
mem_end = memory + saved_state.asregs.msize;
! loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
insn_ptr = PT2H (saved_state.asregs.pc);
CHECK_INSN_PTR (insn_ptr);
--- 1773,1783 ----
memory = saved_state.asregs.memory;
mem_end = memory + saved_state.asregs.msize;
! if (RE & 1)
! loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);
! else
! loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
!
insn_ptr = PT2H (saved_state.asregs.pc);
CHECK_INSN_PTR (insn_ptr);
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFA] Add sh4a tests to sim/testsuite/sim/sh
2004-01-09 13:19 ` Joern Rennecke
@ 2004-01-09 19:47 ` Michael Snyder
2004-01-10 0:46 ` [PATCH] sim/sh whitespace cleanup Michael Snyder
2004-01-13 20:00 ` [OB] fix array size in sh-dis.c Michael Snyder
2 siblings, 0 replies; 14+ messages in thread
From: Michael Snyder @ 2004-01-09 19:47 UTC (permalink / raw)
To: Joern Rennecke; +Cc: amylaar, andrew.stubbs, gdb-patches
Joern Rennecke wrote:
>>+ test_infm:
>>+ # Test negitive infinity
>
> negative.
>
>>+ fldi0 fr11
>>+ mov.l infm, r0
>>+ lds r0, fpul
>>+ fsts fpul, fr0
>>+ fipr fv0, fv8
>>+ # fr11 should be plus infinity
>
> minus.
>
>
>>>cmp/ge is signed.
>>>cmp/hs is unsigned.
>>
>>OK, then the test is OK and I should remove the comment?
>
>
> Yes.
OK, committed with that change.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] sim/sh whitespace cleanup
2004-01-09 13:19 ` Joern Rennecke
2004-01-09 19:47 ` Michael Snyder
@ 2004-01-10 0:46 ` Michael Snyder
2004-01-13 20:00 ` [OB] fix array size in sh-dis.c Michael Snyder
2 siblings, 0 replies; 14+ messages in thread
From: Michael Snyder @ 2004-01-10 0:46 UTC (permalink / raw)
To: Joern Rennecke; +Cc: amylaar, andrew.stubbs, gdb-patches
[-- Attachment #1: Type: text/plain, Size: 13 bytes --]
Committed.
[-- Attachment #2: spaces --]
[-- Type: text/plain, Size: 33307 bytes --]
Index: gencode.c
===================================================================
RCS file: /cvs/src/src/sim/sh/gencode.c,v
retrieving revision 1.23
diff -p -r1.23 gencode.c
*** gencode.c 9 Jan 2004 19:44:50 -0000 1.23
--- gencode.c 10 Jan 2004 00:12:05 -0000
*************** op tab[] =
*** 49,55 ****
{
{ "n", "", "add #<imm>,<REG_N>", "0111nnnni8*1....",
! "R[n] += SEXT(i);",
"if (i == 0) {",
" UNDEF(n); /* see #ifdef PARANOID */",
" break;",
--- 49,55 ----
{
{ "n", "", "add #<imm>,<REG_N>", "0111nnnni8*1....",
! "R[n] += SEXT (i);",
"if (i == 0) {",
" UNDEF(n); /* see #ifdef PARANOID */",
" break;",
*************** op tab[] =
*** 85,91 ****
{ "", "", "bf <bdisp8>", "10001011i8p1....",
"if (!T) {",
! " SET_NIP (PC + 4 + (SEXT(i) * 2));",
" cycles += 2;",
"}",
},
--- 85,91 ----
{ "", "", "bf <bdisp8>", "10001011i8p1....",
"if (!T) {",
! " SET_NIP (PC + 4 + (SEXT (i) * 2));",
" cycles += 2;",
"}",
},
*************** op tab[] =
*** 235,241 ****
/* sh2e */
{ "", "", "fabs <FREG_N>", "1111nnnn01011101",
"FP_UNARY (n, fabs);",
! "/* FIXME: FR(n) &= 0x7fffffff; */",
},
/* sh2e */
--- 235,241 ----
/* sh2e */
{ "", "", "fabs <FREG_N>", "1111nnnn01011101",
"FP_UNARY (n, fabs);",
! "/* FIXME: FR (n) &= 0x7fffffff; */",
},
/* sh2e */
*************** op tab[] =
*** 263,269 ****
" int i;",
" float f;",
" } u;",
! " u.f = DR(n);",
" FPUL = u.i;",
"}",
},
--- 263,269 ----
" int i;",
" float f;",
" } u;",
! " u.f = DR (n);",
" FPUL = u.i;",
"}",
},
*************** op tab[] =
*** 280,286 ****
" float f;",
" } u;",
" u.i = FPUL;",
! " SET_DR(n, u.f);",
"}",
},
--- 280,286 ----
" float f;",
" } u;",
" u.i = FPUL;",
! " SET_DR (n, u.f);",
"}",
},
*************** op tab[] =
*** 308,320 ****
/* sh2e */
{ "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
! "SET_FR (n, (float)0.0);",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh2e */
{ "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
! "SET_FR (n, (float)1.0);",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
--- 308,320 ----
/* sh2e */
{ "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
! "SET_FR (n, (float) 0.0);",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh2e */
{ "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
! "SET_FR (n, (float) 1.0);",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
*************** op tab[] =
*** 325,331 ****
" int i;",
" float f;",
" } u;",
! " u.f = FR(n);",
" FPUL = u.i;",
},
--- 325,331 ----
" int i;",
" float f;",
" } u;",
! " u.f = FR (n);",
" FPUL = u.i;",
},
*************** op tab[] =
*** 333,348 ****
{ "", "", "float FPUL,<FREG_N>", "1111nnnn00101101",
/* sh4 */
"if (FPSCR_PR)",
! " SET_DR (n, (double)FPUL);",
"else",
"{",
! " SET_FR (n, (float)FPUL);",
"}",
},
/* sh2e */
{ "", "", "fmac <FREG_0>,<FREG_M>,<FREG_N>", "1111nnnnmmmm1110",
! "SET_FR (n, FR(m) * FR(0) + FR(n));",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
--- 333,348 ----
{ "", "", "float FPUL,<FREG_N>", "1111nnnn00101101",
/* sh4 */
"if (FPSCR_PR)",
! " SET_DR (n, (double) FPUL);",
"else",
"{",
! " SET_FR (n, (float) FPUL);",
"}",
},
/* sh2e */
{ "", "", "fmac <FREG_0>,<FREG_M>,<FREG_N>", "1111nnnnmmmm1110",
! "SET_FR (n, FR (m) * FR (0) + FR (n));",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
*************** op tab[] =
*** 370,376 ****
"else",
"{",
" MA (1);",
! " WLAT (R[n], FI(m));",
"}",
},
/* sh2e */
--- 370,376 ----
"else",
"{",
" MA (1);",
! " WLAT (R[n], FI (m));",
"}",
},
/* sh2e */
*************** op tab[] =
*** 383,389 ****
"else",
"{",
" MA (1);",
! " SET_FI(n, RLAT(R[m]));",
"}",
},
/* sh2e */
--- 383,389 ----
"else",
"{",
" MA (1);",
! " SET_FI (n, RLAT (R[m]));",
"}",
},
/* sh2e */
*************** op tab[] =
*** 413,419 ****
"{",
" MA (1);",
" R[n] -= 4;",
! " WLAT (R[n], FI(m));",
"}",
},
/* sh2e */
--- 413,419 ----
"{",
" MA (1);",
" R[n] -= 4;",
! " WLAT (R[n], FI (m));",
"}",
},
/* sh2e */
*************** op tab[] =
*** 426,432 ****
"else",
"{",
" MA (1);",
! " SET_FI(n, RLAT(R[0] + R[m]));",
"}",
},
/* sh2e */
--- 426,432 ----
"else",
"{",
" MA (1);",
! " SET_FI (n, RLAT (R[0] + R[m]));",
"}",
},
/* sh2e */
*************** op tab[] =
*** 439,445 ****
"else",
"{",
" MA (1);",
! " WLAT((R[0]+R[n]), FI(m));",
"}",
},
--- 439,445 ----
"else",
"{",
" MA (1);",
! " WLAT ((R[0]+R[n]), FI (m));",
"}",
},
*************** op tab[] =
*** 447,463 ****
/* sh2e */
{ "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010",
! "FP_OP(n, *, m);",
},
/* sh2e */
{ "", "", "fneg <FREG_N>", "1111nnnn01001101",
! "FP_UNARY(n, -);",
},
/* sh4a */
{ "", "", "fpchg", "1111011111111101",
! "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_PR);",
},
/* sh4 */
--- 447,463 ----
/* sh2e */
{ "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010",
! "FP_OP (n, *, m);",
},
/* sh2e */
{ "", "", "fneg <FREG_N>", "1111nnnn01001101",
! "FP_UNARY (n, -);",
},
/* sh4a */
{ "", "", "fpchg", "1111011111111101",
! "SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_PR);",
},
/* sh4 */
*************** op tab[] =
*** 465,471 ****
"if (FPSCR_PR)",
" RAISE_EXCEPTION (SIGILL);",
"else",
! " SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_FR);",
},
/* sh4 */
--- 465,471 ----
"if (FPSCR_PR)",
" RAISE_EXCEPTION (SIGILL);",
"else",
! " SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_FR);",
},
/* sh4 */
*************** op tab[] =
*** 481,492 ****
/* sh4 */
{ "", "", "fschg", "1111001111111101",
! "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_SZ);",
},
/* sh3e */
{ "", "", "fsqrt <FREG_N>", "1111nnnn01101101",
! "FP_UNARY(n, sqrt);",
},
/* sh4 */
--- 481,492 ----
/* sh4 */
{ "", "", "fschg", "1111001111111101",
! "SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_SZ);",
},
/* sh3e */
{ "", "", "fsqrt <FREG_N>", "1111nnnn01101101",
! "FP_UNARY (n, sqrt);",
},
/* sh4 */
*************** op tab[] =
*** 499,521 ****
/* sh2e */
{ "", "", "fsub <FREG_M>,<FREG_N>", "1111nnnnmmmm0001",
! "FP_OP(n, -, m);",
},
/* sh2e */
{ "", "", "ftrc <FREG_N>, FPUL", "1111nnnn00111101",
/* sh4 */
"if (FPSCR_PR) {",
! " if (DR(n) != DR(n)) /* NaN */",
" FPUL = 0x80000000;",
" else",
! " FPUL = (int)DR(n);",
"}",
"else",
! "if (FR(n) != FR(n)) /* NaN */",
" FPUL = 0x80000000;",
"else",
! " FPUL = (int)FR(n);",
},
/* sh4 */
--- 499,521 ----
/* sh2e */
{ "", "", "fsub <FREG_M>,<FREG_N>", "1111nnnnmmmm0001",
! "FP_OP (n, -, m);",
},
/* sh2e */
{ "", "", "ftrc <FREG_N>, FPUL", "1111nnnn00111101",
/* sh4 */
"if (FPSCR_PR) {",
! " if (DR (n) != DR (n)) /* NaN */",
" FPUL = 0x80000000;",
" else",
! " FPUL = (int) DR (n);",
"}",
"else",
! "if (FR (n) != FR (n)) /* NaN */",
" FPUL = 0x80000000;",
"else",
! " FPUL = (int) FR (n);",
},
/* sh4 */
*************** op tab[] =
*** 643,659 ****
},
{ "n", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110",
"MA (1);",
! "SREG (m) = RLAT(R[n]);",
"R[n] += 4;",
},
/* sh2e / sh-dsp (lds <REG_N>,DSR) */
{ "", "n", "lds <REG_N>,FPSCR", "0100nnnn01101010",
! "SET_FPSCR(R[n]);",
},
/* sh2e / sh-dsp (lds.l @<REG_N>+,DSR) */
{ "n", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110",
"MA (1);",
! "SET_FPSCR (RLAT(R[n]));",
"R[n] += 4;",
},
--- 643,659 ----
},
{ "n", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110",
"MA (1);",
! "SREG (m) = RLAT (R[n]);",
"R[n] += 4;",
},
/* sh2e / sh-dsp (lds <REG_N>,DSR) */
{ "", "n", "lds <REG_N>,FPSCR", "0100nnnn01101010",
! "SET_FPSCR (R[n]);",
},
/* sh2e / sh-dsp (lds.l @<REG_N>+,DSR) */
{ "n", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110",
"MA (1);",
! "SET_FPSCR (RLAT (R[n]));",
"R[n] += 4;",
},
*************** op tab[] =
*** 662,676 ****
},
{ "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
! "macl(&R0,memory,n,m);",
},
{ "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
! "macw(&R0,memory,n,m,endianw);",
},
{ "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....",
! "R[n] = SEXT(i);",
},
{ "n", "m", "mov <REG_M>,<REG_N>", "0110nnnnmmmm0011",
"R[n] = R[m];",
--- 662,676 ----
},
{ "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
! "macl (&R0,memory,n,m);",
},
{ "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
! "macw (&R0,memory,n,m,endianw);",
},
{ "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....",
! "R[n] = SEXT (i);",
},
{ "n", "m", "mov <REG_M>,<REG_N>", "0110nnnnmmmm0011",
"R[n] = R[m];",
*************** op tab[] =
*** 890,902 ****
/* muls.w - see muls */
{ "", "mn", "muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
! "MACL = ((int)(short)R[n]) * ((int)(short)R[m]);",
},
/* mulu.w - see mulu */
{ "", "mn", "mulu <REG_M>,<REG_N>", "0010nnnnmmmm1110",
! "MACL = (((unsigned int)(unsigned short)R[n])",
! " * ((unsigned int)(unsigned short)R[m]));",
},
{ "n", "m", "neg <REG_M>,<REG_N>", "0110nnnnmmmm1011",
--- 890,902 ----
/* muls.w - see muls */
{ "", "mn", "muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
! "MACL = ((int) (short) R[n]) * ((int) (short) R[m]);",
},
/* mulu.w - see mulu */
{ "", "mn", "mulu <REG_M>,<REG_N>", "0010nnnnmmmm1110",
! "MACL = (((unsigned int) (unsigned short) R[n])",
! " * ((unsigned int) (unsigned short) R[m]));",
},
{ "n", "m", "neg <REG_M>,<REG_N>", "0110nnnnmmmm1011",
*************** op tab[] =
*** 1184,1192 ****
{ "", "n", "tas.b @<REG_N>", "0100nnnn00011011",
"MA (1);",
! "ult = RBAT(R[n]);",
"SET_SR_T (ult == 0);",
! "WBAT(R[n],ult|0x80);",
},
{ "0", "", "trapa #<imm>", "11000011i8*1....",
--- 1184,1192 ----
{ "", "n", "tas.b @<REG_N>", "0100nnnn00011011",
"MA (1);",
! "ult = RBAT (R[n]);",
"SET_SR_T (ult == 0);",
! "WBAT (R[n],ult|0x80);",
},
{ "0", "", "trapa #<imm>", "11000011i8*1....",
*************** op tab[] =
*** 1196,1210 ****
#if 0
"else {",
/* SH-[12] */
! " R[15]-=4;",
! " WLAT (R[15], GET_SR());",
! " R[15]-=4;",
" WLAT (R[15], PH2T (PC + 2));",
#else
"else if (!SR_BL) {",
! " SSR = GET_SR();",
" SPC = PH2T (PC + 2);",
! " SET_SR (GET_SR() | SR_MASK_MD | SR_MASK_BL | SR_MASK_RB);",
" /* FIXME: EXPEVT = 0x00000160; */",
#endif
" SET_NIP (PT2H (RLAT (VBR + (imm<<2))));",
--- 1196,1210 ----
#if 0
"else {",
/* SH-[12] */
! " R[15] -= 4;",
! " WLAT (R[15], GET_SR ());",
! " R[15] -= 4;",
" WLAT (R[15], PH2T (PC + 2));",
#else
"else if (!SR_BL) {",
! " SSR = GET_SR ();",
" SPC = PH2T (PC + 2);",
! " SET_SR (GET_SR () | SR_MASK_MD | SR_MASK_BL | SR_MASK_RB);",
" /* FIXME: EXPEVT = 0x00000160; */",
#endif
" SET_NIP (PT2H (RLAT (VBR + (imm<<2))));",
*************** op tab[] =
*** 1242,1251 ****
#if 0
{ "divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110",
! "divl(0,R[n],R[m]);",
},
{ "divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101",
! "divl(0,R[n],R[m]);",
},
#endif
--- 1242,1251 ----
#if 0
{ "divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110",
! "divl (0,R[n],R[m]);",
},
{ "divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101",
! "divl (0,R[n],R[m]);",
},
#endif
*************** gensim_caselist (p)
*** 2619,2628 ****
case '1':
break;
case '2':
! printf ("<<1");
break;
case '4':
! printf ("<<2");
break;
}
printf (";\n");
--- 2619,2628 ----
case '1':
break;
case '2':
! printf (" << 1");
break;
case '4':
! printf (" << 2");
break;
}
printf (";\n");
*************** gensim_caselist (p)
*** 2631,2657 ****
}
if (sextbit > 0)
{
! printf (" i = (i ^ (1<<%d))-(1<<%d);\n",
sextbit - 1, sextbit - 1);
}
if (needm && needn)
! printf (" TB(m,n);\n");
else if (needm)
! printf (" TL(m);\n");
else if (needn)
! printf (" TL(n);\n");
{
/* Do the refs */
char *r;
for (r = p->refs; *r; r++)
{
! if (*r == '0') printf(" CREF(0);\n");
! if (*r == '8') printf(" CREF(8);\n");
! if (*r == '9') printf(" CREF(9);\n");
! if (*r == 'n') printf(" CREF(n);\n");
! if (*r == 'm') printf(" CREF(m);\n");
}
}
--- 2631,2657 ----
}
if (sextbit > 0)
{
! printf (" i = (i ^ (1 << %d)) - (1 << %d);\n",
sextbit - 1, sextbit - 1);
}
if (needm && needn)
! printf (" TB (m,n);\n");
else if (needm)
! printf (" TL (m);\n");
else if (needn)
! printf (" TL (n);\n");
{
/* Do the refs */
char *r;
for (r = p->refs; *r; r++)
{
! if (*r == '0') printf (" CREF (0);\n");
! if (*r == '8') printf (" CREF (8);\n");
! if (*r == '9') printf (" CREF (9);\n");
! if (*r == 'n') printf (" CREF (n);\n");
! if (*r == 'm') printf (" CREF (m);\n");
}
}
*************** gensim_caselist (p)
*** 2670,2678 ****
char *r;
for (r = p->defs; *r; r++)
{
! if (*r == '0') printf(" CDEF(0);\n");
! if (*r == 'n') printf(" CDEF(n);\n");
! if (*r == 'm') printf(" CDEF(m);\n");
}
}
--- 2670,2678 ----
char *r;
for (r = p->defs; *r; r++)
{
! if (*r == '0') printf(" CDEF (0);\n");
! if (*r == 'n') printf(" CDEF (n);\n");
! if (*r == 'm') printf(" CDEF (m);\n");
}
}
*************** gendefines ()
*** 2720,2741 ****
char *s = p->name;
printf ("#define OPC_");
while (*s) {
! if (isupper(*s))
! *s = tolower(*s);
! if (isalpha(*s)) printf("%c", *s);
! if (*s == ' ') printf("_");
! if (*s == '@') printf("ind_");
! if (*s == ',') printf("_");
s++;
}
! printf(" %d\n",p->index);
}
}
static int ppi_index;
/* Take a ppi code, expand all varying fields in it and fill all the
! right entries in 'table' with the opcode index.
NOTE: tail recursion optimization removed for simplicity. */
static void
--- 2720,2745 ----
char *s = p->name;
printf ("#define OPC_");
while (*s) {
! if (isupper (*s))
! *s = tolower (*s);
! if (isalpha (*s))
! printf ("%c", *s);
! if (*s == ' ')
! printf ("_");
! if (*s == '@')
! printf ("ind_");
! if (*s == ',')
! printf ("_");
s++;
}
! printf (" %d\n",p->index);
}
}
static int ppi_index;
/* Take a ppi code, expand all varying fields in it and fill all the
! right entries in 'table' with the opcode index.
NOTE: tail recursion optimization removed for simplicity. */
static void
Index: interp.c
===================================================================
RCS file: /cvs/src/src/sim/sh/interp.c,v
retrieving revision 1.13
diff -p -r1.13 interp.c
*** interp.c 9 Jan 2004 19:44:49 -0000 1.13
--- interp.c 10 Jan 2004 00:12:05 -0000
*************** static char *myname;
*** 183,191 ****
#define R0 saved_state.asregs.regs[0]
#define Rn saved_state.asregs.regs[n]
#define Rm saved_state.asregs.regs[m]
! #define UR0 (unsigned int)(saved_state.asregs.regs[0])
! #define UR (unsigned int)R
! #define UR (unsigned int)R
#define SR0 saved_state.asregs.regs[0]
#define CREG(n) (saved_state.asregs.cregs.i[(n)])
#define GBR saved_state.asregs.cregs.named.gbr
--- 183,191 ----
#define R0 saved_state.asregs.regs[0]
#define Rn saved_state.asregs.regs[n]
#define Rm saved_state.asregs.regs[m]
! #define UR0 (unsigned int) (saved_state.asregs.regs[0])
! #define UR (unsigned int) R
! #define UR (unsigned int) R
#define SR0 saved_state.asregs.regs[0]
#define CREG(n) (saved_state.asregs.cregs.i[(n)])
#define GBR saved_state.asregs.cregs.named.gbr
*************** do { \
*** 270,278 ****
#define FPSCR_MASK_SZ (1 << 20)
#define FPSCR_MASK_PR (1 << 19)
! #define FPSCR_FR ((GET_FPSCR() & FPSCR_MASK_FR) != 0)
! #define FPSCR_SZ ((GET_FPSCR() & FPSCR_MASK_SZ) != 0)
! #define FPSCR_PR ((GET_FPSCR() & FPSCR_MASK_PR) != 0)
/* Count the number of arguments in an argv. */
static int
--- 270,278 ----
#define FPSCR_MASK_SZ (1 << 20)
#define FPSCR_MASK_PR (1 << 19)
! #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
! #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
! #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
/* Count the number of arguments in an argv. */
static int
*************** void
*** 330,336 ****
raise_exception (x)
int x;
{
! RAISE_EXCEPTION(x);
}
void
--- 330,336 ----
raise_exception (x)
int x;
{
! RAISE_EXCEPTION (x);
}
void
*************** do { \
*** 405,411 ****
#ifdef PARANOID
int valid[16];
! #define CREF(x) if(!valid[x]) fail();
#define CDEF(x) valid[x] = 1;
#define UNDEF(x) valid[x] = 0;
#else
--- 405,411 ----
#ifdef PARANOID
int valid[16];
! #define CREF(x) if (!valid[x]) fail ();
#define CDEF(x) valid[x] = 1;
#define UNDEF(x) valid[x] = 0;
#else
*************** int valid[16];
*** 416,429 ****
static void parse_and_set_memory_size PARAMS ((char *str));
static int IOMEM PARAMS ((int addr, int write, int value));
! static struct loop_bounds get_loop_bounds PARAMS((int, int, unsigned char *,
! unsigned char *, int, int));
! static void process_wlat_addr PARAMS((int, int));
! static void process_wwat_addr PARAMS((int, int));
! static void process_wbat_addr PARAMS((int, int));
! static int process_rlat_addr PARAMS((int));
! static int process_rwat_addr PARAMS((int));
! static int process_rbat_addr PARAMS((int));
static void INLINE wlat_fast PARAMS ((unsigned char *, int, int, int));
static void INLINE wwat_fast PARAMS ((unsigned char *, int, int, int, int));
static void INLINE wbat_fast PARAMS ((unsigned char *, int, int, int));
--- 416,429 ----
static void parse_and_set_memory_size PARAMS ((char *str));
static int IOMEM PARAMS ((int addr, int write, int value));
! static struct loop_bounds get_loop_bounds PARAMS ((int, int, unsigned char *,
! unsigned char *, int, int));
! static void process_wlat_addr PARAMS ((int, int));
! static void process_wwat_addr PARAMS ((int, int));
! static void process_wbat_addr PARAMS ((int, int));
! static int process_rlat_addr PARAMS ((int));
! static int process_rwat_addr PARAMS ((int));
! static int process_rbat_addr PARAMS ((int));
static void INLINE wlat_fast PARAMS ((unsigned char *, int, int, int));
static void INLINE wwat_fast PARAMS ((unsigned char *, int, int, int, int));
static void INLINE wbat_fast PARAMS ((unsigned char *, int, int, int));
*************** set_dr (n, exp)
*** 522,531 ****
if (((n) & 1) || ((m) & 1)) \
RAISE_EXCEPTION (SIGILL); \
else \
! SET_DR(n, (DR(n) OP DR(m))); \
} \
else \
! SET_FR(n, (FR(n) OP FR(m))); \
} while (0)
#define FP_UNARY(n, OP) \
--- 522,531 ----
if (((n) & 1) || ((m) & 1)) \
RAISE_EXCEPTION (SIGILL); \
else \
! SET_DR (n, (DR (n) OP DR (m))); \
} \
else \
! SET_FR (n, (FR (n) OP FR (m))); \
} while (0)
#define FP_UNARY(n, OP) \
*************** set_dr (n, exp)
*** 535,544 ****
if ((n) & 1) \
RAISE_EXCEPTION (SIGILL); \
else \
! SET_DR(n, (OP (DR(n)))); \
} \
else \
! SET_FR(n, (OP (FR(n)))); \
} while (0)
#define FP_CMP(n, OP, m) \
--- 535,544 ----
if ((n) & 1) \
RAISE_EXCEPTION (SIGILL); \
else \
! SET_DR (n, (OP (DR (n)))); \
} \
else \
! SET_FR (n, (OP (FR (n)))); \
} while (0)
#define FP_CMP(n, OP, m) \
*************** set_dr (n, exp)
*** 548,557 ****
if (((n) & 1) || ((m) & 1)) \
RAISE_EXCEPTION (SIGILL); \
else \
! SET_SR_T (DR(n) OP DR(m)); \
} \
else \
! SET_SR_T (FR(n) OP FR(m)); \
} while (0)
static void
--- 548,557 ----
if (((n) & 1) || ((m) & 1)) \
RAISE_EXCEPTION (SIGILL); \
else \
! SET_SR_T (DR (n) OP DR (m)); \
} \
else \
! SET_SR_T (FR (n) OP FR (m)); \
} while (0)
static void
*************** wlat_fast (memory, x, value, maskl)
*** 580,586 ****
unsigned char *memory;
{
int v = value;
! unsigned int *p = (unsigned int *)(memory + x);
WRITE_BUSERROR (x, maskl, v, process_wlat_addr);
*p = v;
}
--- 580,586 ----
unsigned char *memory;
{
int v = value;
! unsigned int *p = (unsigned int *) (memory + x);
WRITE_BUSERROR (x, maskl, v, process_wlat_addr);
*p = v;
}
*************** wwat_fast (memory, x, value, maskw, endi
*** 590,596 ****
unsigned char *memory;
{
int v = value;
! unsigned short *p = (unsigned short *)(memory + (x ^ endianw));
WRITE_BUSERROR (x, maskw, v, process_wwat_addr);
*p = v;
}
--- 590,596 ----
unsigned char *memory;
{
int v = value;
! unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
WRITE_BUSERROR (x, maskw, v, process_wwat_addr);
*p = v;
}
*************** static int INLINE
*** 611,617 ****
rlat_fast (memory, x, maskl)
unsigned char *memory;
{
! unsigned int *p = (unsigned int *)(memory + x);
READ_BUSERROR (x, maskl, process_rlat_addr);
return *p;
--- 611,617 ----
rlat_fast (memory, x, maskl)
unsigned char *memory;
{
! unsigned int *p = (unsigned int *) (memory + x);
READ_BUSERROR (x, maskl, process_rlat_addr);
return *p;
*************** rwat_fast (memory, x, maskw, endianw)
*** 622,628 ****
unsigned char *memory;
int x, maskw, endianw;
{
! unsigned short *p = (unsigned short *)(memory + (x ^ endianw));
READ_BUSERROR (x, maskw, process_rwat_addr);
return *p;
--- 622,628 ----
unsigned char *memory;
int x, maskw, endianw;
{
! unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
READ_BUSERROR (x, maskw, process_rwat_addr);
return *p;
*************** static int INLINE
*** 632,638 ****
riat_fast (insn_ptr, endianw)
unsigned char *insn_ptr;
{
! unsigned short *p = (unsigned short *)((size_t) insn_ptr ^ endianw);
return *p;
}
--- 632,638 ----
riat_fast (insn_ptr, endianw)
unsigned char *insn_ptr;
{
! unsigned short *p = (unsigned short *) ((size_t) insn_ptr ^ endianw);
return *p;
}
*************** rbat_fast (memory, x, maskb)
*** 655,664 ****
#define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
#define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
! #define RUWAT(x) (RWAT(x) & 0xffff)
! #define RSWAT(x) ((short)(RWAT(x)))
! #define RSLAT(x) ((long)(RLAT(x)))
! #define RSBAT(x) (SEXT(RBAT(x)))
#define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
static int
--- 655,664 ----
#define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
#define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
! #define RUWAT(x) (RWAT (x) & 0xffff)
! #define RSWAT(x) ((short) (RWAT (x)))
! #define RSLAT(x) ((long) (RLAT (x)))
! #define RSBAT(x) (SEXT (RBAT (x)))
#define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
static int
*************** process_rbat_addr (addr)
*** 763,773 ****
#define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
#define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
! #define SEXTW(y) ((int)((short)y))
#if 0
! #define SEXT32(x) ((int)((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
#else
! #define SEXT32(x) ((int)(x))
#endif
#define SIGN32(x) (SEXT32 (x) >> 31)
--- 763,773 ----
#define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
#define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
! #define SEXTW(y) ((int) ((short) y))
#if 0
! #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
#else
! #define SEXT32(x) ((int) (x))
#endif
#define SIGN32(x) (SEXT32 (x) >> 31)
*************** do { \
*** 806,812 ****
#define L(x) thislock = x;
#define TL(x) if ((x) == prevlock) stalls++;
! #define TB(x,y) if ((x) == prevlock || (y)==prevlock) stalls++;
#endif
--- 806,812 ----
#define L(x) thislock = x;
#define TL(x) if ((x) == prevlock) stalls++;
! #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
#endif
*************** trap (i, regs, insn_ptr, memory, maskl,
*** 1004,1013 ****
Besides, it's quite dangerous. */
#if 0
case SYS_execve:
! regs[0] = execve (ptr (regs[5]), (char **)ptr (regs[6]), (char **)ptr (regs[7]));
break;
case SYS_execv:
! regs[0] = execve (ptr (regs[5]),(char **) ptr (regs[6]), 0);
break;
#endif
case SYS_pipe:
--- 1004,1014 ----
Besides, it's quite dangerous. */
#if 0
case SYS_execve:
! regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]),
! (char **) ptr (regs[7]));
break;
case SYS_execv:
! regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), 0);
break;
#endif
case SYS_pipe:
*************** trap (i, regs, insn_ptr, memory, maskl,
*** 1032,1040 ****
case SYS_write:
strnswap (regs[6], regs[7]);
if (regs[5] == 1)
! regs[0] = (int)callback->write_stdout (callback, ptr(regs[6]), regs[7]);
else
! regs[0] = (int)callback->write (callback, regs[5], ptr (regs[6]), regs[7]);
strnswap (regs[6], regs[7]);
break;
case SYS_lseek:
--- 1033,1043 ----
case SYS_write:
strnswap (regs[6], regs[7]);
if (regs[5] == 1)
! regs[0] = (int) callback->write_stdout (callback,
! ptr (regs[6]), regs[7]);
else
! regs[0] = (int) callback->write (callback, regs[5],
! ptr (regs[6]), regs[7]);
strnswap (regs[6], regs[7]);
break;
case SYS_lseek:
*************** trap (i, regs, insn_ptr, memory, maskl,
*** 1047,1053 ****
{
int len = strswaplen (regs[5]);
strnswap (regs[5], len);
! regs[0] = callback->open (callback,ptr (regs[5]), regs[6]);
strnswap (regs[5], len);
break;
}
--- 1050,1056 ----
{
int len = strswaplen (regs[5]);
strnswap (regs[5], len);
! regs[0] = callback->open (callback, ptr (regs[5]), regs[6]);
strnswap (regs[5], len);
break;
}
*************** macw (regs, memory, n, m, endianw)
*** 1338,1348 ****
long tempm, tempn;
long prod, macl, sum;
! tempm=RSWAT(regs[m]); regs[m]+=2;
! tempn=RSWAT(regs[n]); regs[n]+=2;
macl = MACL;
! prod = (long)(short) tempm * (long)(short) tempn;
sum = prod + macl;
if (S)
{
--- 1341,1351 ----
long tempm, tempn;
long prod, macl, sum;
! tempm=RSWAT (regs[m]); regs[m]+=2;
! tempn=RSWAT (regs[n]); regs[n]+=2;
macl = MACL;
! prod = (long) (short) tempm * (long) (short) tempn;
sum = prod + macl;
if (S)
{
*************** macl (regs, memory, n, m)
*** 1382,1391 ****
long long m64; /* 64 bit MAC */
}mac64;
! tempm = RSLAT(regs[m]);
regs[m] += 4;
! tempn = RSLAT(regs[n]);
regs[n] += 4;
mach = MACH;
--- 1385,1394 ----
long long m64; /* 64 bit MAC */
}mac64;
! tempm = RSLAT (regs[m]);
regs[m] += 4;
! tempn = RSLAT (regs[n]);
regs[n] += 4;
mach = MACH;
*************** macl (regs, memory, n, m)
*** 1394,1400 ****
mac64.m[0] = macl;
mac64.m[1] = mach;
! ans = (long long)tempm * (long long)tempn; /* Multiply 32bit * 32bit */
mac64.m64 += ans; /* Accumulate 64bit + 64 bit */
--- 1397,1403 ----
mac64.m[0] = macl;
mac64.m[1] = mach;
! ans = (long long) tempm * (long long) tempn; /* Multiply 32bit * 32bit */
mac64.m64 += ans; /* Accumulate 64bit + 64 bit */
*************** fsrra_s (float in)
*** 1477,1483 ****
architectural spec. */
frac = frexp (result, &exp);
frac = ldexp (frac, 24);
! error = 4.; /* 1 << 24-1-21 */
/* use eps to compensate for possible 1 ulp error in our 'exact' result. */
eps = ldexp (1., -29);
upper = floor (frac + error - eps);
--- 1480,1486 ----
architectural spec. */
frac = frexp (result, &exp);
frac = ldexp (frac, 24);
! error = 4.0; /* 1 << 24-1-21 */
/* use eps to compensate for possible 1 ulp error in our 'exact' result. */
eps = ldexp (1., -29);
upper = floor (frac + error - eps);
*************** get_loop_bounds (rs, re, memory, mem_end
*** 1530,1537 ****
return loop;
}
! static void
! ppi_insn();
#include "ppi.c"
--- 1533,1539 ----
return loop;
}
! static void ppi_insn ();
#include "ppi.c"
*************** static void
*** 1657,1663 ****
init_pointers ()
{
host_little_endian = 0;
! *(char*)&host_little_endian = 1;
host_little_endian &= 1;
if (saved_state.asregs.msize != 1 << sim_memory_size)
--- 1659,1665 ----
init_pointers ()
{
host_little_endian = 0;
! * (char*) &host_little_endian = 1;
host_little_endian &= 1;
if (saved_state.asregs.msize != 1 << sim_memory_size)
*************** sim_store_register (sd, rn, memory, leng
*** 1948,1954 ****
unsigned val;
init_pointers ();
! val = swap (* (int *)memory);
switch (rn)
{
case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
--- 1950,1956 ----
unsigned val;
init_pointers ();
! val = swap (* (int *) memory);
switch (rn)
{
case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
*************** sim_info (sd, verbose)
*** 2240,2246 ****
SIM_DESC sd;
int verbose;
{
! double timetaken = (double) saved_state.asregs.ticks / (double) now_persec ();
double virttime = saved_state.asregs.cycles / 36.0e6;
callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
--- 2242,2249 ----
SIM_DESC sd;
int verbose;
{
! double timetaken =
! (double) saved_state.asregs.ticks / (double) now_persec ();
double virttime = saved_state.asregs.cycles / 36.0e6;
callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
*************** sim_create_inferior (sd, prog_bfd, argv,
*** 2394,2400 ****
{
/* Clear the registers. */
memset (&saved_state, 0,
! (char*)&saved_state.asregs.end_of_registers - (char*)&saved_state);
/* Set the PC. */
if (prog_bfd != NULL)
--- 2397,2403 ----
{
/* Clear the registers. */
memset (&saved_state, 0,
! (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state);
/* Set the PC. */
if (prog_bfd != NULL)
*************** sim_do_command (sd, cmd)
*** 2420,2432 ****
}
cmdsize = strlen (sms_cmd);
! if (strncmp (cmd, sms_cmd, cmdsize) == 0 && strchr (" \t", cmd[cmdsize]) != NULL)
{
parse_and_set_memory_size (cmd + cmdsize + 1);
}
else if (strcmp (cmd, "help") == 0)
{
! (callback->printf_filtered) (callback, "List of SH simulator commands:\n\n");
(callback->printf_filtered) (callback, "set-memory-size <n> -- Set the number of address bits to use\n");
(callback->printf_filtered) (callback, "\n");
}
--- 2423,2437 ----
}
cmdsize = strlen (sms_cmd);
! if (strncmp (cmd, sms_cmd, cmdsize) == 0
! && strchr (" \t", cmd[cmdsize]) != NULL)
{
parse_and_set_memory_size (cmd + cmdsize + 1);
}
else if (strcmp (cmd, "help") == 0)
{
! (callback->printf_filtered) (callback,
! "List of SH simulator commands:\n\n");
(callback->printf_filtered) (callback, "set-memory-size <n> -- Set the number of address bits to use\n");
(callback->printf_filtered) (callback, "\n");
}
^ permalink raw reply [flat|nested] 14+ messages in thread
* [OB] fix array size in sh-dis.c
2004-01-09 13:19 ` Joern Rennecke
2004-01-09 19:47 ` Michael Snyder
2004-01-10 0:46 ` [PATCH] sim/sh whitespace cleanup Michael Snyder
@ 2004-01-13 20:00 ` Michael Snyder
2004-01-13 23:23 ` Andrew Cagney
2004-01-14 17:14 ` Joern Rennecke
2 siblings, 2 replies; 14+ messages in thread
From: Michael Snyder @ 2004-01-13 20:00 UTC (permalink / raw)
To: Joern Rennecke; +Cc: amylaar, andrew.stubbs, gdb-patches, Elena Zannoni
[-- Attachment #1: Type: text/plain, Size: 155 bytes --]
This array needs to be four bytes, in case we have to
disassemble a four byte insn (eg. ppi). Otherwise, it
clobbers one of the nearby local variables.
[-- Attachment #2: insn --]
[-- Type: text/plain, Size: 841 bytes --]
2004-01-13 Michael Snyder <msnyder@redhat.com>
* sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
Index: sh-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/sh-dis.c,v
retrieving revision 1.17
diff -p -r1.17 sh-dis.c
*** sh-dis.c 5 Dec 2003 02:02:32 -0000 1.17
--- sh-dis.c 13 Jan 2004 19:56:21 -0000
*************** print_insn_sh (memaddr, info)
*** 397,403 ****
{
fprintf_ftype fprintf_fn = info->fprintf_func;
void *stream = info->stream;
! unsigned char insn[2];
unsigned char nibs[4];
int status;
bfd_vma relmask = ~(bfd_vma) 0;
--- 397,403 ----
{
fprintf_ftype fprintf_fn = info->fprintf_func;
void *stream = info->stream;
! unsigned char insn[4];
unsigned char nibs[4];
int status;
bfd_vma relmask = ~(bfd_vma) 0;
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [OB] fix array size in sh-dis.c
2004-01-13 20:00 ` [OB] fix array size in sh-dis.c Michael Snyder
@ 2004-01-13 23:23 ` Andrew Cagney
2004-01-14 17:14 ` Joern Rennecke
1 sibling, 0 replies; 14+ messages in thread
From: Andrew Cagney @ 2004-01-13 23:23 UTC (permalink / raw)
To: Michael Snyder
Cc: Joern Rennecke, amylaar, andrew.stubbs, gdb-patches, Elena Zannoni
> 2004-01-13 Michael Snyder <msnyder@redhat.com>
>
> * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
>
Michael,
opcodes/ patches should be sent to binutils@
Andrew
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [OB] fix array size in sh-dis.c
2004-01-13 20:00 ` [OB] fix array size in sh-dis.c Michael Snyder
2004-01-13 23:23 ` Andrew Cagney
@ 2004-01-14 17:14 ` Joern Rennecke
1 sibling, 0 replies; 14+ messages in thread
From: Joern Rennecke @ 2004-01-14 17:14 UTC (permalink / raw)
To: Michael Snyder
Cc: Joern Rennecke, amylaar, andrew.stubbs, gdb-patches,
Elena Zannoni, binutils
> This array needs to be four bytes, in case we have to
> disassemble a four byte insn (eg. ppi). Otherwise, it
> clobbers one of the nearby local variables.
How would that happen? I don't see any place where more than two bytes are
used.
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2004-01-14 17:14 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2004-01-07 21:56 [RFA] Add sh4a to sh-sim (2nd iteration) Michael Snyder
2004-01-07 22:04 ` [RFA] Add sh4a tests to sim/testsuite/sim/sh Michael Snyder
2004-01-08 15:07 ` Joern Rennecke
2004-01-08 22:04 ` Michael Snyder
2004-01-09 13:19 ` Joern Rennecke
2004-01-09 19:47 ` Michael Snyder
2004-01-10 0:46 ` [PATCH] sim/sh whitespace cleanup Michael Snyder
2004-01-13 20:00 ` [OB] fix array size in sh-dis.c Michael Snyder
2004-01-13 23:23 ` Andrew Cagney
2004-01-14 17:14 ` Joern Rennecke
2004-01-08 16:15 ` [RFA] Add sh4a to sh-sim (2nd iteration) Joern Rennecke
2004-01-08 22:02 ` Michael Snyder
2004-01-09 12:37 ` Joern Rennecke
2004-01-09 19:45 ` Michael Snyder
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