* [RFC] correct XMM register positions
@ 2001-11-21 14:10 Pierre Muller
2001-11-21 14:21 ` Momchil Velikov
2001-11-30 3:54 ` Pierre Muller
0 siblings, 2 replies; 8+ messages in thread
From: Pierre Muller @ 2001-11-21 14:10 UTC (permalink / raw)
To: gdb-patches
After some testing of my SSE register
patch, I finally discovered why I didn't get any correct display of
the xmm registers.
It seems that (at least for Pentium IV processor)
the SSE registers are not the first fields of the ExtendedRegisters
byte array. They start at offset 160.
The first part might be filled with MMX regs ???
I still don't know where the MXCSR register is.
If someone can give me some more extensive
SSE source for which this register changes
in a known way, I could probably locate it.
I found NO info on the microsoft site about the content of this array...
the only thing I found was that it is CPU specific, so
this might still fail for non intel processors....
The patch below does give correct results for me,
the problem is that my test code is written in Free Pascal,
so its probably not useful for most people...
2001-11-30 Pierre Muller <muller@ics.u-strasbg.fr>
* win32-nat.c (mappings): Correct position of XMM registers.
Index: win32-nat.c
===================================================================
RCS file: /cvs/src/src/gdb/win32-nat.c,v
retrieving revision 1.40
diff -r1.40 win32-nat.c
182,189c182,189
< context_offset (ExtendedRegisters[0*16]),
< context_offset (ExtendedRegisters[1*16]),
< context_offset (ExtendedRegisters[2*16]),
< context_offset (ExtendedRegisters[3*16]),
< context_offset (ExtendedRegisters[4*16]),
< context_offset (ExtendedRegisters[5*16]),
< context_offset (ExtendedRegisters[6*16]),
< context_offset (ExtendedRegisters[7*16]),
---
> context_offset (ExtendedRegisters[10*16]),
> context_offset (ExtendedRegisters[11*16]),
> context_offset (ExtendedRegisters[12*16]),
> context_offset (ExtendedRegisters[13*16]),
> context_offset (ExtendedRegisters[14*16]),
> context_offset (ExtendedRegisters[15*16]),
> context_offset (ExtendedRegisters[16*16]),
> context_offset (ExtendedRegisters[17*16]),
191c191
< context_offset (ExtendedRegisters[8*16])
---
> context_offset (ExtendedRegisters[18*16])
Pierre Muller
Institut Charles Sadron
6,rue Boussingault
F 67083 STRASBOURG CEDEX (France)
mailto:muller@ics.u-strasbg.fr
Phone : (33)-3-88-41-40-07 Fax : (33)-3-88-41-40-99
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC] correct XMM register positions
2001-11-21 14:10 [RFC] correct XMM register positions Pierre Muller
@ 2001-11-21 14:21 ` Momchil Velikov
2001-11-30 4:00 ` Momchil Velikov
2001-11-30 4:54 ` Pierre Muller
2001-11-30 3:54 ` Pierre Muller
1 sibling, 2 replies; 8+ messages in thread
From: Momchil Velikov @ 2001-11-21 14:21 UTC (permalink / raw)
To: Pierre Muller; +Cc: gdb-patches
>>>>> "Pierre" == Pierre Muller <muller@cerbere.u-strasbg.fr> writes:
Pierre> I found NO info on the microsoft site about the content of this array...
Pierre> the only thing I found was that it is CPU specific, so
Pierre> this might still fail for non intel processors....
Maybe you would want to look at "IA-32 Intel ® Architecture Software
Developer's Manual Volume 2 : Instruction Set Reference", FXSAVE insn.
Regards,
-velco
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC] correct XMM register positions
2001-11-21 14:21 ` Momchil Velikov
@ 2001-11-30 4:00 ` Momchil Velikov
2001-11-30 4:54 ` Pierre Muller
1 sibling, 0 replies; 8+ messages in thread
From: Momchil Velikov @ 2001-11-30 4:00 UTC (permalink / raw)
To: Pierre Muller; +Cc: gdb-patches
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 438 bytes --]
>>>>> "Pierre" == Pierre Muller <muller@cerbere.u-strasbg.fr> writes:
Pierre> I found NO info on the microsoft site about the content of this array...
Pierre> the only thing I found was that it is CPU specific, so
Pierre> this might still fail for non intel processors....
Maybe you would want to look at "IA-32 Intel ® Architecture Software
Developer's Manual Volume 2 : Instruction Set Reference", FXSAVE insn.
Regards,
-velco
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC] correct XMM register positions
2001-11-21 14:21 ` Momchil Velikov
2001-11-30 4:00 ` Momchil Velikov
@ 2001-11-30 4:54 ` Pierre Muller
2001-11-21 14:27 ` Pierre Muller
2001-11-21 14:28 ` Eli Zaretskii
1 sibling, 2 replies; 8+ messages in thread
From: Pierre Muller @ 2001-11-30 4:54 UTC (permalink / raw)
To: Momchil Velikov; +Cc: gdb-patches
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 949 bytes --]
At 13:07 30/11/2001 , Momchil Velikov a écrit:
> >>>>> "Pierre" == Pierre Muller <muller@cerbere.u-strasbg.fr> writes:
>Pierre> I found NO info on the microsoft site about the content of this array...
>Pierre> the only thing I found was that it is CPU specific, so
>Pierre> this might still fail for non intel processors....
>
>Maybe you would want to look at "IA-32 Intel ® Architecture Software
>Developer's Manual Volume 2 : Instruction Set Reference", FXSAVE insn.
Thanks a lot, it does indeed seem that the ExtendedRegisters
is just the layout described there.
Does anyone know if the AMD and the other Pentium clones
also support the same instruction and register layout
in that structure?
Are manuals also available for the different clones?
Pierre Muller
Institut Charles Sadron
6,rue Boussingault
F 67083 STRASBOURG CEDEX (France)
mailto:muller@ics.u-strasbg.fr
Phone : (33)-3-88-41-40-07 Fax : (33)-3-88-41-40-99
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC] correct XMM register positions
2001-11-30 4:54 ` Pierre Muller
@ 2001-11-21 14:27 ` Pierre Muller
2001-11-21 14:28 ` Eli Zaretskii
1 sibling, 0 replies; 8+ messages in thread
From: Pierre Muller @ 2001-11-21 14:27 UTC (permalink / raw)
To: Momchil Velikov; +Cc: gdb-patches
At 13:07 30/11/2001 , Momchil Velikov a écrit:
> >>>>> "Pierre" == Pierre Muller <muller@cerbere.u-strasbg.fr> writes:
>Pierre> I found NO info on the microsoft site about the content of this array...
>Pierre> the only thing I found was that it is CPU specific, so
>Pierre> this might still fail for non intel processors....
>
>Maybe you would want to look at "IA-32 Intel ® Architecture Software
>Developer's Manual Volume 2 : Instruction Set Reference", FXSAVE insn.
Thanks a lot, it does indeed seem that the ExtendedRegisters
is just the layout described there.
Does anyone know if the AMD and the other Pentium clones
also support the same instruction and register layout
in that structure?
Are manuals also available for the different clones?
Pierre Muller
Institut Charles Sadron
6,rue Boussingault
F 67083 STRASBOURG CEDEX (France)
mailto:muller@ics.u-strasbg.fr
Phone : (33)-3-88-41-40-07 Fax : (33)-3-88-41-40-99
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC] correct XMM register positions
2001-11-30 4:54 ` Pierre Muller
2001-11-21 14:27 ` Pierre Muller
@ 2001-11-21 14:28 ` Eli Zaretskii
2001-11-30 5:06 ` Eli Zaretskii
1 sibling, 1 reply; 8+ messages in thread
From: Eli Zaretskii @ 2001-11-21 14:28 UTC (permalink / raw)
To: muller; +Cc: velco, gdb-patches
> Date: Fri, 30 Nov 2001 13:52:56 +0100
> From: Pierre Muller <muller@cerbere.u-strasbg.fr>
>
> Does anyone know if the AMD and the other Pentium clones
> also support the same instruction and register layout
> in that structure?
I think so.
> Are manuals also available for the different clones?
Yes, definitely. You will find them on the sites of the respective
vendors (sometimes even under the same part numbers).
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC] correct XMM register positions
2001-11-21 14:28 ` Eli Zaretskii
@ 2001-11-30 5:06 ` Eli Zaretskii
0 siblings, 0 replies; 8+ messages in thread
From: Eli Zaretskii @ 2001-11-30 5:06 UTC (permalink / raw)
To: muller; +Cc: velco, gdb-patches
> Date: Fri, 30 Nov 2001 13:52:56 +0100
> From: Pierre Muller <muller@cerbere.u-strasbg.fr>
>
> Does anyone know if the AMD and the other Pentium clones
> also support the same instruction and register layout
> in that structure?
I think so.
> Are manuals also available for the different clones?
Yes, definitely. You will find them on the sites of the respective
vendors (sometimes even under the same part numbers).
^ permalink raw reply [flat|nested] 8+ messages in thread
* [RFC] correct XMM register positions
2001-11-21 14:10 [RFC] correct XMM register positions Pierre Muller
2001-11-21 14:21 ` Momchil Velikov
@ 2001-11-30 3:54 ` Pierre Muller
1 sibling, 0 replies; 8+ messages in thread
From: Pierre Muller @ 2001-11-30 3:54 UTC (permalink / raw)
To: gdb-patches
After some testing of my SSE register
patch, I finally discovered why I didn't get any correct display of
the xmm registers.
It seems that (at least for Pentium IV processor)
the SSE registers are not the first fields of the ExtendedRegisters
byte array. They start at offset 160.
The first part might be filled with MMX regs ???
I still don't know where the MXCSR register is.
If someone can give me some more extensive
SSE source for which this register changes
in a known way, I could probably locate it.
I found NO info on the microsoft site about the content of this array...
the only thing I found was that it is CPU specific, so
this might still fail for non intel processors....
The patch below does give correct results for me,
the problem is that my test code is written in Free Pascal,
so its probably not useful for most people...
2001-11-30 Pierre Muller <muller@ics.u-strasbg.fr>
* win32-nat.c (mappings): Correct position of XMM registers.
Index: win32-nat.c
===================================================================
RCS file: /cvs/src/src/gdb/win32-nat.c,v
retrieving revision 1.40
diff -r1.40 win32-nat.c
182,189c182,189
< context_offset (ExtendedRegisters[0*16]),
< context_offset (ExtendedRegisters[1*16]),
< context_offset (ExtendedRegisters[2*16]),
< context_offset (ExtendedRegisters[3*16]),
< context_offset (ExtendedRegisters[4*16]),
< context_offset (ExtendedRegisters[5*16]),
< context_offset (ExtendedRegisters[6*16]),
< context_offset (ExtendedRegisters[7*16]),
---
> context_offset (ExtendedRegisters[10*16]),
> context_offset (ExtendedRegisters[11*16]),
> context_offset (ExtendedRegisters[12*16]),
> context_offset (ExtendedRegisters[13*16]),
> context_offset (ExtendedRegisters[14*16]),
> context_offset (ExtendedRegisters[15*16]),
> context_offset (ExtendedRegisters[16*16]),
> context_offset (ExtendedRegisters[17*16]),
191c191
< context_offset (ExtendedRegisters[8*16])
---
> context_offset (ExtendedRegisters[18*16])
Pierre Muller
Institut Charles Sadron
6,rue Boussingault
F 67083 STRASBOURG CEDEX (France)
mailto:muller@ics.u-strasbg.fr
Phone : (33)-3-88-41-40-07 Fax : (33)-3-88-41-40-99
^ permalink raw reply [flat|nested] 8+ messages in thread
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2001-11-21 14:10 [RFC] correct XMM register positions Pierre Muller
2001-11-21 14:21 ` Momchil Velikov
2001-11-30 4:00 ` Momchil Velikov
2001-11-30 4:54 ` Pierre Muller
2001-11-21 14:27 ` Pierre Muller
2001-11-21 14:28 ` Eli Zaretskii
2001-11-30 5:06 ` Eli Zaretskii
2001-11-30 3:54 ` Pierre Muller
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