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From: Pierre Muller <muller@cerbere.u-strasbg.fr>
To: gdb-patches <gdb-patches@sources.redhat.com>
Subject: [RFC] correct XMM register positions
Date: Wed, 21 Nov 2001 14:10:00 -0000	[thread overview]
Message-ID: <4.2.0.58.20011130124329.00ac9350@ics.u-strasbg.fr> (raw)


After some testing of my SSE register 
patch, I finally discovered why I didn't get any correct display of 
the xmm registers.

   It seems that (at least for Pentium IV processor)
the SSE registers are not the first fields of the ExtendedRegisters 
byte array. They start at offset 160.
The first part might be filled with MMX regs ???
I still don't know where the MXCSR register is.
If someone can give me some more extensive 
SSE source for which this register changes 
in a known way, I could probably locate it.

   I found NO info on the microsoft site about the content of this array...
the only thing I found was that it is CPU specific, so
this might still fail for non intel processors....


The patch below does give correct results for me,
the problem is that my test code is written in Free Pascal,
so its probably not useful for most people...

2001-11-30 Pierre Muller  <muller@ics.u-strasbg.fr>
	* win32-nat.c (mappings): Correct position of XMM registers.

Index: win32-nat.c
===================================================================
RCS file: /cvs/src/src/gdb/win32-nat.c,v
retrieving revision 1.40
diff -r1.40 win32-nat.c
182,189c182,189
<   context_offset (ExtendedRegisters[0*16]),
<   context_offset (ExtendedRegisters[1*16]),
<   context_offset (ExtendedRegisters[2*16]),
<   context_offset (ExtendedRegisters[3*16]),
<   context_offset (ExtendedRegisters[4*16]),
<   context_offset (ExtendedRegisters[5*16]),
<   context_offset (ExtendedRegisters[6*16]),
<   context_offset (ExtendedRegisters[7*16]),
---
 >   context_offset (ExtendedRegisters[10*16]),
 >   context_offset (ExtendedRegisters[11*16]),
 >   context_offset (ExtendedRegisters[12*16]),
 >   context_offset (ExtendedRegisters[13*16]),
 >   context_offset (ExtendedRegisters[14*16]),
 >   context_offset (ExtendedRegisters[15*16]),
 >   context_offset (ExtendedRegisters[16*16]),
 >   context_offset (ExtendedRegisters[17*16]),
191c191
<   context_offset (ExtendedRegisters[8*16])
---
 >   context_offset (ExtendedRegisters[18*16])



Pierre Muller
Institut Charles Sadron
6,rue Boussingault
F 67083 STRASBOURG CEDEX (France)
mailto:muller@ics.u-strasbg.fr
Phone : (33)-3-88-41-40-07  Fax : (33)-3-88-41-40-99


WARNING: multiple messages have this Message-ID
From: Pierre Muller <muller@cerbere.u-strasbg.fr>
To: gdb-patches <gdb-patches@sources.redhat.com>
Subject: [RFC] correct XMM register positions
Date: Fri, 30 Nov 2001 03:54:00 -0000	[thread overview]
Message-ID: <4.2.0.58.20011130124329.00ac9350@ics.u-strasbg.fr> (raw)
Message-ID: <20011130035400.5PbAjnSQU9PplKskSEiQijc8kG1wQlz71oVlnlk9Zzk@z> (raw)

After some testing of my SSE register 
patch, I finally discovered why I didn't get any correct display of 
the xmm registers.

   It seems that (at least for Pentium IV processor)
the SSE registers are not the first fields of the ExtendedRegisters 
byte array. They start at offset 160.
The first part might be filled with MMX regs ???
I still don't know where the MXCSR register is.
If someone can give me some more extensive 
SSE source for which this register changes 
in a known way, I could probably locate it.

   I found NO info on the microsoft site about the content of this array...
the only thing I found was that it is CPU specific, so
this might still fail for non intel processors....


The patch below does give correct results for me,
the problem is that my test code is written in Free Pascal,
so its probably not useful for most people...

2001-11-30 Pierre Muller  <muller@ics.u-strasbg.fr>
	* win32-nat.c (mappings): Correct position of XMM registers.

Index: win32-nat.c
===================================================================
RCS file: /cvs/src/src/gdb/win32-nat.c,v
retrieving revision 1.40
diff -r1.40 win32-nat.c
182,189c182,189
<   context_offset (ExtendedRegisters[0*16]),
<   context_offset (ExtendedRegisters[1*16]),
<   context_offset (ExtendedRegisters[2*16]),
<   context_offset (ExtendedRegisters[3*16]),
<   context_offset (ExtendedRegisters[4*16]),
<   context_offset (ExtendedRegisters[5*16]),
<   context_offset (ExtendedRegisters[6*16]),
<   context_offset (ExtendedRegisters[7*16]),
---
 >   context_offset (ExtendedRegisters[10*16]),
 >   context_offset (ExtendedRegisters[11*16]),
 >   context_offset (ExtendedRegisters[12*16]),
 >   context_offset (ExtendedRegisters[13*16]),
 >   context_offset (ExtendedRegisters[14*16]),
 >   context_offset (ExtendedRegisters[15*16]),
 >   context_offset (ExtendedRegisters[16*16]),
 >   context_offset (ExtendedRegisters[17*16]),
191c191
<   context_offset (ExtendedRegisters[8*16])
---
 >   context_offset (ExtendedRegisters[18*16])



Pierre Muller
Institut Charles Sadron
6,rue Boussingault
F 67083 STRASBOURG CEDEX (France)
mailto:muller@ics.u-strasbg.fr
Phone : (33)-3-88-41-40-07  Fax : (33)-3-88-41-40-99


             reply	other threads:[~2001-11-30 11:54 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2001-11-21 14:10 Pierre Muller [this message]
2001-11-21 14:21 ` Momchil Velikov
2001-11-30  4:00   ` Momchil Velikov
2001-11-30  4:54   ` Pierre Muller
2001-11-21 14:27     ` Pierre Muller
2001-11-21 14:28     ` Eli Zaretskii
2001-11-30  5:06       ` Eli Zaretskii
2001-11-30  3:54 ` Pierre Muller

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