From: Pierre Muller <muller@cerbere.u-strasbg.fr>
To: Momchil Velikov <velco@fadata.bg>
Cc: gdb-patches <gdb-patches@sources.redhat.com>
Subject: Re: [RFC] correct XMM register positions
Date: Fri, 30 Nov 2001 04:54:00 -0000 [thread overview]
Message-ID: <4.2.0.58.20011130134625.013dfc70@ics.u-strasbg.fr> (raw)
In-Reply-To: <87lmgoea2j.fsf@fadata.bg>
At 13:07 30/11/2001 , Momchil Velikov a écrit:
> >>>>> "Pierre" == Pierre Muller <muller@cerbere.u-strasbg.fr> writes:
>Pierre> I found NO info on the microsoft site about the content of this array...
>Pierre> the only thing I found was that it is CPU specific, so
>Pierre> this might still fail for non intel processors....
>
>Maybe you would want to look at "IA-32 Intel ® Architecture Software
>Developer's Manual Volume 2 : Instruction Set Reference", FXSAVE insn.
Thanks a lot, it does indeed seem that the ExtendedRegisters
is just the layout described there.
Does anyone know if the AMD and the other Pentium clones
also support the same instruction and register layout
in that structure?
Are manuals also available for the different clones?
Pierre Muller
Institut Charles Sadron
6,rue Boussingault
F 67083 STRASBOURG CEDEX (France)
mailto:muller@ics.u-strasbg.fr
Phone : (33)-3-88-41-40-07 Fax : (33)-3-88-41-40-99
WARNING: multiple messages have this Message-ID
From: Pierre Muller <muller@cerbere.u-strasbg.fr>
To: Momchil Velikov <velco@fadata.bg>
Cc: gdb-patches <gdb-patches@sources.redhat.com>
Subject: Re: [RFC] correct XMM register positions
Date: Wed, 21 Nov 2001 14:27:00 -0000 [thread overview]
Message-ID: <4.2.0.58.20011130134625.013dfc70@ics.u-strasbg.fr> (raw)
Message-ID: <20011121142700.3qheVwd54v4lWjolWNtNaH9zLbM-D_iI1BrAi3pmqsQ@z> (raw)
In-Reply-To: <87lmgoea2j.fsf@fadata.bg>
At 13:07 30/11/2001 , Momchil Velikov a écrit:
> >>>>> "Pierre" == Pierre Muller <muller@cerbere.u-strasbg.fr> writes:
>Pierre> I found NO info on the microsoft site about the content of this array...
>Pierre> the only thing I found was that it is CPU specific, so
>Pierre> this might still fail for non intel processors....
>
>Maybe you would want to look at "IA-32 Intel ® Architecture Software
>Developer's Manual Volume 2 : Instruction Set Reference", FXSAVE insn.
Thanks a lot, it does indeed seem that the ExtendedRegisters
is just the layout described there.
Does anyone know if the AMD and the other Pentium clones
also support the same instruction and register layout
in that structure?
Are manuals also available for the different clones?
Pierre Muller
Institut Charles Sadron
6,rue Boussingault
F 67083 STRASBOURG CEDEX (France)
mailto:muller@ics.u-strasbg.fr
Phone : (33)-3-88-41-40-07 Fax : (33)-3-88-41-40-99
next prev parent reply other threads:[~2001-11-30 4:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-11-21 14:10 Pierre Muller
2001-11-21 14:21 ` Momchil Velikov
2001-11-30 4:00 ` Momchil Velikov
2001-11-30 4:54 ` Pierre Muller [this message]
2001-11-21 14:27 ` Pierre Muller
2001-11-21 14:28 ` Eli Zaretskii
2001-11-30 5:06 ` Eli Zaretskii
2001-11-30 3:54 ` Pierre Muller
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