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From: Andrew Cagney <ac131313@redhat.com>
To: cgd@broadcom.com, Kevin Buettner <kevinb@redhat.com>
Cc: gdb-patches@sources.redhat.com
Subject: Re: [WIP/RFC] MIPS registers overhaul
Date: Tue, 20 May 2003 20:25:00 -0000	[thread overview]
Message-ID: <3ECA8EC6.6030405@redhat.com> (raw)
In-Reply-To: <yov5wugqa4m8.fsf@broadcom.com>

> At Fri, 16 May 2003 22:25:13 +0000 (UTC), cgd@broadcom.com wrote:
> 
>> This MIPS specifications (M64 1.00 Volume I, page 50, section 5.6.2)
>> indicate that doing 64-bit reads/writes from/to odd FP registers when
>> FR=0 are "illegal", and that values produced by such operations are
>> unpredictable.
> 
> 
> Actually, on the reads they say that the values produced are
> unpredictable.
> 
> For writes, they indicate that the operation itself is unpredictable
> ("UNPREDICTABLE").

When a 64 bit kernel goes to save/resume an o32 process, how does it do 
it?  Does it have a choice?

For instance, do a 64 bit FP restore then clear the FR bit; the reverse; 
some other variant; ...?



Andrew


> in other words, doing an ldc1 when FR == 0 could cause a trap if an
> implementation were paranoid (*cough* simulator 8-).
> 
> So, really, when FR == 0, best to think of yourself as having only 32
> * 32 bits.
> 
> 
> Now, the question is, in the remote protocol, if 64-bit registers are
> being passed, *how*.  (64-bit target, normally 64-bit registers... i'd assume
> they're being passed as 64-bits.)
> 
> One reasonable way to do it, which i believe would be the result of
> using n32 / n64 RDA on linux to debug an o32 executable, would be:
> 
> 	0: meaningful
> 	1: garbage
> 	etc.
> 
> this is the natural way to do it on a 64-bit part, with a 64-bit FPU.
> another reasonable way (but less efficient on a 64-bit part with a
> 64-bit FPU) would be:
> 
> 	0: <high half garbage><low half meaningful>
> 	1: <high half garbage><low half meaningful>
> 
> Are there 64-bit parts out there that have FPUs with 32 single float
> regs which one can operate on (4650, looking at gcc srcs?)  If so, the
> latter would be a reasonable representation for them.
> 
> 
> So, my conclusion is:
> 
> for raw registers that are xferred as 64-bits, yeah, fine, let people
> have acess to them.  that's for debugger-debugging, and people who
> muck with them may be shooting themselves in the head, but if they're
> debugging the debugger they're smart, right?  8-)
> 
> need to have some way to tell which of the ways above is being used to
> xfer the register data.  (or, need to define that only one way may be
> used.)
> 
> 
> chris
> 
> 



  parent reply	other threads:[~2003-05-20 20:25 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2003-05-10  0:25 Kevin Buettner
2003-05-10 20:30 ` Andrew Cagney
2003-05-10 20:40   ` Daniel Jacobowitz
2003-05-14 22:00   ` Kevin Buettner
     [not found]     ` <mailpost.1052949911.28802@news-sj1-1>
2003-05-14 23:35       ` cgd
2003-05-15  0:07         ` Kevin Buettner
2003-05-15  0:15           ` Daniel Jacobowitz
2003-05-15 22:01     ` Kevin Buettner
2003-05-16  3:24       ` Andrew Cagney
2003-05-16  4:00     ` Andrew Cagney
2003-05-16 17:20       ` Kevin Buettner
     [not found]       ` <mailpost.1053057614.17325@news-sj1-1>
2003-05-16 22:25         ` cgd
     [not found]           ` <mailpost.1053123913.16634@news-sj1-1>
2003-05-16 22:50             ` cgd
2003-05-16 23:05               ` Kevin Buettner
     [not found]                 ` <mailpost.1053126410.17856@news-sj1-1>
2003-05-16 23:24                   ` cgd
2003-05-17  0:41                     ` Kevin Buettner
2003-05-17 20:59                       ` Daniel Jacobowitz
2003-05-20 20:18                         ` Always remote: " Andrew Cagney
2003-05-20 20:26                           ` Daniel Jacobowitz
     [not found]                       ` <mailpost.1053132070.20348@news-sj1-1>
2003-05-20 20:37                         ` cgd
2003-05-20 20:51                           ` Kevin Buettner
2003-05-20 20:52                           ` Andrew Cagney
2003-05-20 21:57                             ` cgd
2003-05-21 15:34                               ` Andrew Cagney
2003-05-21 15:41                                 ` Daniel Jacobowitz
2003-05-21 16:38                                   ` Andrew Cagney
2003-05-21 16:58                                     ` Daniel Jacobowitz
2003-05-21 18:32                                       ` Kevin Buettner
2003-05-21 19:15                                         ` Andrew Cagney
2003-05-21 19:45                                           ` Kevin Buettner
2003-05-22  0:32                                           ` Daniel Jacobowitz
2003-05-23 18:39                                             ` Andrew Cagney
2003-05-23 19:02                                               ` Daniel Jacobowitz
2003-05-23 20:45                                                 ` Andrew Cagney
2003-05-20 20:25               ` Andrew Cagney [this message]
2003-05-20 20:32                 ` cgd
2003-05-21 15:40                   ` Andrew Cagney
2003-06-15  1:44                     ` Andrew Cagney
2003-06-16 18:06                       ` cgd
2003-06-16 18:47                         ` Andrew Cagney
2003-06-15 17:23                   ` Andrew Cagney
2003-06-16 20:06                     ` cgd
2003-06-16 20:41                       ` Andrew Cagney
     [not found]                         ` <mailpost.1055796186.4097@news-sj1-1>
2003-06-17  5:04                           ` cgd
2003-06-17 14:27                             ` Andrew Cagney
     [not found]                               ` <mailpost.1055860052.3406@news-sj1-1>
2003-06-17 16:27                                 ` cgd
2003-05-21 20:58 David Anderson

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