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From: Stafford Horne <shorne@gmail.com>
To: GDB patches <gdb-patches@sourceware.org>,
	GNU Binutils <binutils@sourceware.org>
Cc: Andrey Bacherov <bandvig@mail.ru>,
	Nick Clifton <nickc@redhat.com>,
	Andrew Burgess <andrew.burgess@embecosm.com>,
	Richard Henderson <rth@twiddle.net>,
	Openrisc <openrisc@lists.librecores.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [PATCH v3 04/11] cpu/or1k: Update fpu compare symbols to imply set flag
Date: Sat, 08 Jun 2019 21:32:00 -0000	[thread overview]
Message-ID: <20190608213225.3230-5-shorne@gmail.com> (raw)
In-Reply-To: <20190608213225.3230-1-shorne@gmail.com>

The fpu compare symbols where not including 'sf' in the mnemonic.  So
instead of `lf-sfeq` (implying set flag if operands are equal) we were
having `lf-eq`.   This patch adds the 'sf'.  This helps with making the
generated CGEN documentation consistent and ordered correctly.

cpu/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
---
 cpu/or1korfpx.cpu | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
index 5e33b82a44..f43522f2e6 100644
--- a/cpu/or1korfpx.cpu
+++ b/cpu/or1korfpx.cpu
@@ -268,7 +268,7 @@
 
 (define-pmacro (float-setflag-insn-base mnemonic rtx-mnemonic symantics)
   (begin
-    (dni (.sym lf- mnemonic -s)
+    (dni (.sym lf-sf mnemonic -s)
          (.str "lf.sf" mnemonic ".s reg/reg")
          ((MACH ORFPX32-MACHS))
          (.str "lf.sf" mnemonic ".s $rASF,$rBSF")
@@ -276,7 +276,7 @@
          (symantics rtx-mnemonic SF rASF rBSF)
          ()
          )
-    (dni (.sym lf- mnemonic -d)
+    (dni (.sym lf-sf mnemonic -d)
          (.str "lf.sf" mnemonic ".d reg/reg")
          ((MACH ORFPX64-MACHS))
          (.str "lf.sf" mnemonic ".d $rADF,$rBDF")
@@ -284,7 +284,7 @@
          (symantics rtx-mnemonic DF rADF rBDF)
          ()
          )
-    (dni (.sym lf- mnemonic -d32)
+    (dni (.sym lf-sf mnemonic -d32)
          (.str "lf.sf" mnemonic ".d regpair/regpair")
          ((MACH ORFPX64A32-MACHS))
          (.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
-- 
2.21.0


  parent reply	other threads:[~2019-06-08 21:32 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
2019-06-08 21:32 ` [PATCH v3 02/11] cpu/or1k: Define unordered comparisons Stafford Horne
2019-06-08 21:32 ` Stafford Horne [this message]
2019-06-08 21:32 ` [PATCH v3 01/11] cpu/or1k: Add support for orfp64a32 spec Stafford Horne
2019-06-08 21:32 ` [PATCH v3 03/11] cpu/or1k: Document no branch delay slot architectures and l.adrp Stafford Horne
2019-06-08 21:33 ` [PATCH v3 07/11] sim/common: Wire in df/di conversion Stafford Horne
2019-06-08 21:33 ` [PATCH v3 06/11] sim/or1k: Regenerate sim Stafford Horne
2019-06-08 21:33 ` [PATCH v3 05/11] opcodes/or1k: Regenerate opcodes Stafford Horne
2019-06-08 21:33 ` [PATCH v3 08/11] sim/common: wire up new unordered comparisons Stafford Horne
2019-06-08 21:33 ` [PATCH v3 09/11] sim/testsuite/or1k: Add test for 64-bit fpu operations Stafford Horne
2019-06-10 15:08 ` [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Nick Clifton
2019-06-10 20:51   ` Stafford Horne
2019-06-11 16:03 ` Nick Clifton
2019-06-12 13:12   ` Stafford Horne
2019-06-12 21:25     ` Stafford Horne

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