From: Stafford Horne <shorne@gmail.com>
To: GDB patches <gdb-patches@sourceware.org>,
GNU Binutils <binutils@sourceware.org>
Cc: Andrey Bacherov <bandvig@mail.ru>,
Nick Clifton <nickc@redhat.com>,
Andrew Burgess <andrew.burgess@embecosm.com>,
Richard Henderson <rth@twiddle.net>,
Openrisc <openrisc@lists.librecores.org>,
Stafford Horne <shorne@gmail.com>
Subject: [PATCH v3 02/11] cpu/or1k: Define unordered comparisons
Date: Sat, 08 Jun 2019 21:32:00 -0000 [thread overview]
Message-ID: <20190608213225.3230-3-shorne@gmail.com> (raw)
In-Reply-To: <20190608213225.3230-1-shorne@gmail.com>
Add support for new floating point unordered comparisons. These have been
defined in OpenRISC architecture proposal 7[0] and are now included in the
architecture specification 1.3.
These new instructions provide the ability for floating point comparisons to
detect NaNs.
[0] https://openrisc.io/proposals/lfsf
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S,
SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D,
SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes.
(float-setflag-insn-base): New pmacro based on float-setflag-insn.
(float-setflag-symantics, float-setflag-unordered-cmp-symantics,
float-setflag-unordered-symantics): New pmacro for instruction
symantics.
(float-setflag-insn): Update to use float-setflag-insn-base.
(float-setflag-unordered-insn): New pmacro for generating instructions.
---
cpu/or1korfpx.cpu | 47 +++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
index eb01f1ca66..5e33b82a44 100644
--- a/cpu/or1korfpx.cpu
+++ b/cpu/or1korfpx.cpu
@@ -54,6 +54,20 @@
("SFGE_D" #x1b)
("SFLT_D" #x1c)
("SFLE_D" #x1d)
+ ("SFUEQ_S" #x28)
+ ("SFUNE_S" #x29)
+ ("SFUGT_S" #x2a)
+ ("SFUGE_S" #x2b)
+ ("SFULT_S" #x2c)
+ ("SFULE_S" #x2d)
+ ("SFUN_S" #x2e)
+ ("SFUEQ_D" #x38)
+ ("SFUNE_D" #x39)
+ ("SFUGT_D" #x3a)
+ ("SFUGE_D" #x3b)
+ ("SFULT_D" #x3c)
+ ("SFULE_D" #x3d)
+ ("SFUN_D" #x3e)
("CUST1_S" #xd0)
("CUST1_D" #xe0)
)
@@ -252,14 +266,14 @@
()
)
-(define-pmacro (float-setflag-insn mnemonic)
+(define-pmacro (float-setflag-insn-base mnemonic rtx-mnemonic symantics)
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf.sf" mnemonic ".s reg/reg")
((MACH ORFPX32-MACHS))
(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
- (set BI sys-sr-f (mnemonic SF rASF rBSF))
+ (symantics rtx-mnemonic SF rASF rBSF)
()
)
(dni (.sym lf- mnemonic -d)
@@ -267,7 +281,7 @@
((MACH ORFPX64-MACHS))
(.str "lf.sf" mnemonic ".d $rADF,$rBDF")
(+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
- (set BI sys-sr-f (mnemonic DF rADF rBDF))
+ (symantics rtx-mnemonic DF rADF rBDF)
()
)
(dni (.sym lf- mnemonic -d32)
@@ -275,18 +289,43 @@
((MACH ORFPX64A32-MACHS))
(.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
(+ OPC_FLOAT (f-r1 0) rAD32F rBD32F (f-resv-10-1 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
- (set BI sys-sr-f (mnemonic DF rAD32F rBD32F))
+ (symantics rtx-mnemonic DF rAD32F rBD32F)
()
)
)
)
+(define-pmacro (float-setflag-symantics mnemonic mode r1 r2)
+ (set BI sys-sr-f (mnemonic mode r1 r2)))
+
+(define-pmacro (float-setflag-insn mnemonic)
+ (float-setflag-insn-base mnemonic mnemonic float-setflag-symantics))
+
+(define-pmacro (float-setflag-unordered-cmp-symantics mnemonic mode r1 r2)
+ (set BI sys-sr-f (or (unordered mode r1 r2)
+ (mnemonic mode r1 r2))))
+
+(define-pmacro (float-setflag-unordered-symantics mnemonic mode r1 r2)
+ (set BI sys-sr-f (unordered mode r1 r2)))
+
+(define-pmacro (float-setflag-unordered-insn mnemonic)
+ (float-setflag-insn-base (.str "u" mnemonic)
+ mnemonic
+ float-setflag-unordered-cmp-symantics))
+
(float-setflag-insn eq)
(float-setflag-insn ne)
(float-setflag-insn ge)
(float-setflag-insn gt)
(float-setflag-insn lt)
(float-setflag-insn le)
+(float-setflag-unordered-insn eq)
+(float-setflag-unordered-insn ne)
+(float-setflag-unordered-insn gt)
+(float-setflag-unordered-insn ge)
+(float-setflag-unordered-insn lt)
+(float-setflag-unordered-insn le)
+(float-setflag-insn-base un () float-setflag-unordered-symantics)
(dni lf-madd-s
"lf.madd.s reg/reg/reg"
--
2.21.0
next prev parent reply other threads:[~2019-06-08 21:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
2019-06-08 21:32 ` Stafford Horne [this message]
2019-06-08 21:32 ` [PATCH v3 04/11] cpu/or1k: Update fpu compare symbols to imply set flag Stafford Horne
2019-06-08 21:32 ` [PATCH v3 01/11] cpu/or1k: Add support for orfp64a32 spec Stafford Horne
2019-06-08 21:32 ` [PATCH v3 03/11] cpu/or1k: Document no branch delay slot architectures and l.adrp Stafford Horne
2019-06-08 21:33 ` [PATCH v3 07/11] sim/common: Wire in df/di conversion Stafford Horne
2019-06-08 21:33 ` [PATCH v3 06/11] sim/or1k: Regenerate sim Stafford Horne
2019-06-08 21:33 ` [PATCH v3 05/11] opcodes/or1k: Regenerate opcodes Stafford Horne
2019-06-08 21:33 ` [PATCH v3 08/11] sim/common: wire up new unordered comparisons Stafford Horne
2019-06-08 21:33 ` [PATCH v3 09/11] sim/testsuite/or1k: Add test for 64-bit fpu operations Stafford Horne
2019-06-10 15:08 ` [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Nick Clifton
2019-06-10 20:51 ` Stafford Horne
2019-06-11 16:03 ` Nick Clifton
2019-06-12 13:12 ` Stafford Horne
2019-06-12 21:25 ` Stafford Horne
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