From: Stafford Horne <shorne@gmail.com>
To: GDB patches <gdb-patches@sourceware.org>,
GNU Binutils <binutils@sourceware.org>
Cc: Andrey Bacherov <bandvig@mail.ru>,
Nick Clifton <nickc@redhat.com>,
Andrew Burgess <andrew.burgess@embecosm.com>,
Richard Henderson <rth@twiddle.net>,
Openrisc <openrisc@lists.librecores.org>,
Stafford Horne <shorne@gmail.com>
Subject: [PATCH v3 03/11] cpu/or1k: Document no branch delay slot architectures and l.adrp
Date: Sat, 08 Jun 2019 21:32:00 -0000 [thread overview]
Message-ID: <20190608213225.3230-4-shorne@gmail.com> (raw)
In-Reply-To: <20190608213225.3230-1-shorne@gmail.com>
The 'nd' architectures did not mention what the 'nd' stands for.
Document that these mean 'no brach delay slot'.
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
(l-adrp): Improve comment.
---
cpu/or1k.cpu | 6 +++---
cpu/or1korbis.cpu | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
index e1ae1b8c88..b796862d1b 100644
--- a/cpu/or1k.cpu
+++ b/cpu/or1k.cpu
@@ -77,7 +77,7 @@
(define-mach
(name or32nd)
- (comment "Generic OpenRISC 1000 32-bit CPU")
+ (comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot")
(cpu or1k32bf)
(bfd-name "or1knd")
)
@@ -92,7 +92,7 @@
; OpenRISC 1200 - 32-bit or1k CPU implementation
(define-model
- (name or1200nd) (comment "OpenRISC 1200 model")
+ (name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot")
(attrs NO-DELAY-SLOT)
(mach or32nd)
(unit u-exec "Execution Unit" () 1 1 () () () ())
@@ -120,7 +120,7 @@
(define-mach
(name or64nd)
- (comment "Generic OpenRISC 1000 ND 64-bit CPU")
+ (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot")
(cpu or1k64bf)
(bfd-name "or1k64nd")
)
diff --git a/cpu/or1korbis.cpu b/cpu/or1korbis.cpu
index 308f37861d..3741d4c8f7 100644
--- a/cpu/or1korbis.cpu
+++ b/cpu/or1korbis.cpu
@@ -433,7 +433,7 @@
)
)
-(dni l-adrp "adrp reg/disp21"
+(dni l-adrp "load pc-relative page address"
((MACH ORBIS-MACHS))
"l.adrp $rD,${disp21}"
(+ OPC_ADRP rD disp21)
--
2.21.0
next prev parent reply other threads:[~2019-06-08 21:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-08 21:32 [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Stafford Horne
2019-06-08 21:32 ` Stafford Horne [this message]
2019-06-08 21:32 ` [PATCH v3 01/11] cpu/or1k: Add support for orfp64a32 spec Stafford Horne
2019-06-08 21:32 ` [PATCH v3 04/11] cpu/or1k: Update fpu compare symbols to imply set flag Stafford Horne
2019-06-08 21:32 ` [PATCH v3 02/11] cpu/or1k: Define unordered comparisons Stafford Horne
2019-06-08 21:33 ` [PATCH v3 09/11] sim/testsuite/or1k: Add test for 64-bit fpu operations Stafford Horne
2019-06-08 21:33 ` [PATCH v3 08/11] sim/common: wire up new unordered comparisons Stafford Horne
2019-06-08 21:33 ` [PATCH v3 05/11] opcodes/or1k: Regenerate opcodes Stafford Horne
2019-06-08 21:33 ` [PATCH v3 06/11] sim/or1k: Regenerate sim Stafford Horne
2019-06-08 21:33 ` [PATCH v3 07/11] sim/common: Wire in df/di conversion Stafford Horne
2019-06-10 15:08 ` [PATCH v3 0/11] OpenRISC orfpx64a32 and openrisc spec 1.3 support Nick Clifton
2019-06-10 20:51 ` Stafford Horne
2019-06-11 16:03 ` Nick Clifton
2019-06-12 13:12 ` Stafford Horne
2019-06-12 21:25 ` Stafford Horne
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