* [PATCH] Fix gdb disassemble for power6/power7 instructions
@ 2012-11-13 5:46 Edjunior Barbosa Machado
2012-11-13 23:46 ` Alan Modra
0 siblings, 1 reply; 6+ messages in thread
From: Edjunior Barbosa Machado @ 2012-11-13 5:46 UTC (permalink / raw)
To: gdb-patches; +Cc: binutils, amodra
Hi,
upstream gdb is unable to disassemble power6 and power7 instructions due to a
change on binutils (http://sourceware.org/ml/binutils/2012-03/msg00170.html). It
happens because powerpc_init_dialect() is currently being called before
disassembler_options is configured (it used to be called every time
print_insn_[little|big]_powerpc() was called). The patch below intends to fix
this issue moving the logic to set disassembler_options to
powerpc_init_dialect().
Moreover, with this patch, objdump is also able to disassemble power6 and power7
instructions without the additional parameter -M <option>.
Comments/sugggestions are welcome.
Thanks,
--
Edjunior
gdb/ChangeLog
2012-11-13 Edjunior Machado <emachado@linux.vnet.ibm.com>
* rs6000-tdep.c (gdb_print_insn_powerpc): Move logic to set
info->disassembler_options to binutils' powerpc_init_dialect().
opcodes/ChangeLog
2012-11-13 Edjunior Machado <emachado@linux.vnet.ibm.com>
* ppc-dis.c (powerpc_init_dialect): If not defined, set
info->disassembler_options to "any" or, if debugging an E500 binary,
to "e500x2".
---
gdb/rs6000-tdep.c | 15 ---------------
opcodes/ppc-dis.c | 15 +++++++++++++++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 1797cc5..07b81bc 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -3084,21 +3084,6 @@ find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
static int
gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
{
- if (!info->disassembler_options)
- {
- /* When debugging E500 binaries and disassembling code containing
- E500-specific (SPE) instructions, one sometimes sees AltiVec
- instructions instead. The opcode spaces for SPE instructions
- and AltiVec instructions overlap, and specifiying the "any" cpu
- looks for AltiVec instructions first. If we know we're
- debugging an E500 binary, however, we can specify the "e500x2"
- cpu and get much more sane disassembly output. */
- if (info->mach == bfd_mach_ppc_e500)
- info->disassembler_options = "e500x2";
- else
- info->disassembler_options = "any";
- }
-
if (info->endian == BFD_ENDIAN_BIG)
return print_insn_big_powerpc (memaddr, info);
else
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 03b3160..63b71e5 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -251,6 +251,21 @@ powerpc_init_dialect (struct disassemble_info *info)
if (priv == NULL)
priv = &private;
+ if (!info->disassembler_options)
+ {
+ /* When debugging E500 binaries and disassembling code containing
+ E500-specific (SPE) instructions, one sometimes sees AltiVec
+ instructions instead. The opcode spaces for SPE instructions
+ and AltiVec instructions overlap, and specifiying the "any" cpu
+ looks for AltiVec instructions first. If we know we're
+ debugging an E500 binary, however, we can specify the "e500x2"
+ cpu and get much more sane disassembly output. */
+ if (info->mach == bfd_mach_ppc_e500)
+ info->disassembler_options = "e500x2";
+ else
+ info->disassembler_options = "any";
+ }
+
arg = info->disassembler_options;
while (arg != NULL)
{
--
1.7.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Fix gdb disassemble for power6/power7 instructions
2012-11-13 5:46 [PATCH] Fix gdb disassemble for power6/power7 instructions Edjunior Barbosa Machado
@ 2012-11-13 23:46 ` Alan Modra
2012-11-23 3:29 ` Alan Modra
0 siblings, 1 reply; 6+ messages in thread
From: Alan Modra @ 2012-11-13 23:46 UTC (permalink / raw)
To: Edjunior Barbosa Machado; +Cc: gdb-patches, binutils
On Tue, Nov 13, 2012 at 03:45:40AM -0200, Edjunior Barbosa Machado wrote:
> * ppc-dis.c (powerpc_init_dialect): If not defined, set
> info->disassembler_options to "any" or, if debugging an E500 binary,
> to "e500x2".
I don't like this change as it effectively disables later code that
tries to select a default, in particular breaking vle. The problem is
that the default code is somewhat lacking to say the least, and broken
in the way PPC_OPCODE_64 is handled.
What I think should happen is that the default handling, ie. the block
that starts with
if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
should be deleted and a switch on info->mach setting up dialect added
before we parse disassembler_options. That way -m32 and -m64 can
override the default as they are supposed to. See bfd/archures.c for
values of bfd_mach_ppc_*.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Fix gdb disassemble for power6/power7 instructions
2012-11-13 23:46 ` Alan Modra
@ 2012-11-23 3:29 ` Alan Modra
2012-11-23 17:07 ` Edjunior Barbosa Machado
0 siblings, 1 reply; 6+ messages in thread
From: Alan Modra @ 2012-11-23 3:29 UTC (permalink / raw)
To: Edjunior Barbosa Machado, gdb-patches, binutils
On Wed, Nov 14, 2012 at 10:16:38AM +1030, Alan Modra wrote:
> What I think should happen is that the default handling, ie. the block
> that starts with
> if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
> should be deleted and a switch on info->mach setting up dialect added
> before we parse disassembler_options. That way -m32 and -m64 can
> override the default as they are supposed to. See bfd/archures.c for
> values of bfd_mach_ppc_*.
Well that idea didn't turn out to be simple. If we want to bring the
default up to something more up-to-date than the current ppc601, then
you run into difficulty with "retain_mask" in ppc_parse_cpu. Choosing
any of the bits in that mask as a default, eg. PPC_OPCODE_VSX, results
in not being able to get rid of those bits.
Now the idea of "retain_mask" was to cover cases where people pass
something like -mppc -maltivec (or even -maltivec -mppc) to the
assembler. Historically that has resulted in both PPC_OPCODE_PPC and
PPC_OPCODE_ALTIVEC being set; Some options accumulate. So I've
redone code handling these sticky options to just keep track of the
bits selected by ppc_opts.sticky. Any default selection won't make
these bits sticky, you'll only get that effect from -maltivec, -many,
-mspe, -mvle and -mvsx on the command line or in .machine directives
(and similarly for the corresponding -M disassembler options). I'm
not sure why PPC_OPCODE_PMR was ever in "retain_mask". People
interested in VLE might need to investigate that.
One of the effects of updating to a power7 default is that conditional
branch hints are displayed for "at" style hints rather than the older
"y" hints. When using "y" hints the disassembler always showed the
hint, eg. "bne-" or "bne+". Now you'll see "bne" most times. This
meant updating the testsuite. I made one gas test disassemble for
plain ppc just to ensure the older "y" hints continue to be available.
Committed.
include/opcode/
* ppc.h (ppc_parse_cpu): Update prototype.
opcodes/
* ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits
set from ppc_opts.sticky in it. Delete "retain_mask".
(powerpc_init_dialect): Choose default dialect from info->mach
before parsing -M options. Handle more bfd_mach_ppc variants.
Update common default to power7.
gas/
* config/tc-ppc.c (sticky): New var.
(md_parse_option, ppc_machine): Update ppc_parse_cpu calls.
gas/testsuite/
* gas/ppc/astest2.d: Pass -Mppc to objdump.
ld/testsuite/
* ld-powerpc/plt1.d: Update for default "at" branch hints.
* ld-powerpc/tlsexe.d: Likewise.
* ld-powerpc/tlsexetoc.d: Likewise.
* ld-powerpc/tlsopt1.d: Likewise.
* ld-powerpc/tlsopt1_32.d: Likewise.
* ld-powerpc/tlsopt2.d: Likewise.
* ld-powerpc/tlsopt2_32.d: Likewise.
* ld-powerpc/tlsopt4.d: Likewise.
* ld-powerpc/tlsopt4_32.d: Likewise.
* ld-powerpc/tlsso.d: Likewise.
* ld-powerpc/tlstocso.d: Likewise.
Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.44
diff -u -p -r1.44 ppc.h
--- include/opcode/ppc.h 14 May 2012 19:45:27 -0000 1.44
+++ include/opcode/ppc.h 22 Nov 2012 22:45:18 -0000
@@ -400,6 +400,6 @@ struct powerpc_macro
extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;
-extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
+extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
#endif /* PPC_H */
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.60
diff -u -p -r1.60 ppc-dis.c
--- opcodes/ppc-dis.c 5 Oct 2012 14:06:20 -0000 1.60
+++ opcodes/ppc-dis.c 22 Nov 2012 22:45:19 -0000
@@ -211,13 +211,8 @@ get_powerpc_dialect (struct disassemble_
/* Handle -m and -M options that set cpu type, and .machine arg. */
ppc_cpu_t
-ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
+ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
{
- const ppc_cpu_t retain_mask = (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
- | PPC_OPCODE_SPE | PPC_OPCODE_ANY
- | PPC_OPCODE_VLE | PPC_OPCODE_PMR);
- /* Sticky bits. */
- ppc_cpu_t retain_flags = ppc_cpu & retain_mask;
unsigned int i;
for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
@@ -225,8 +220,8 @@ ppc_parse_cpu (ppc_cpu_t ppc_cpu, const
{
if (ppc_opts[i].sticky)
{
- retain_flags |= ppc_opts[i].sticky;
- if ((ppc_cpu & ~retain_mask) != 0)
+ *sticky |= ppc_opts[i].sticky;
+ if ((ppc_cpu & ~*sticky) != 0)
break;
}
ppc_cpu = ppc_opts[i].cpu;
@@ -235,7 +230,7 @@ ppc_parse_cpu (ppc_cpu_t ppc_cpu, const
if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
return 0;
- ppc_cpu |= retain_flags;
+ ppc_cpu |= *sticky;
return ppc_cpu;
}
@@ -245,12 +240,75 @@ static void
powerpc_init_dialect (struct disassemble_info *info)
{
ppc_cpu_t dialect = 0;
+ ppc_cpu_t sticky = 0;
char *arg;
struct dis_private *priv = calloc (sizeof (*priv), 1);
if (priv == NULL)
priv = &private;
+ switch (info->mach)
+ {
+ case bfd_mach_ppc_403:
+ case bfd_mach_ppc_403gc:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403);
+ break;
+ case bfd_mach_ppc_405:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405);
+ break;
+ case bfd_mach_ppc_601:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_601);
+ break;
+ case bfd_mach_ppc_a35:
+ case bfd_mach_ppc_rs64ii:
+ case bfd_mach_ppc_rs64iii:
+ dialect = (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_64);
+ break;
+ case bfd_mach_ppc_e500:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
+ | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500);
+ break;
+ case bfd_mach_ppc_e500mc:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500MC);
+ break;
+ case bfd_mach_ppc_e500mc64:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
+ | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
+ break;
+ case bfd_mach_ppc_e5500:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7);
+ break;
+ case bfd_mach_ppc_e6500:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
+ | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
+ break;
+ case bfd_mach_ppc_titan:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
+ | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN);
+ break;
+ case bfd_mach_ppc_vle:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE);
+ break;
+ default:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
+ | PPC_OPCODE_ANY);
+ }
+
arg = info->disassembler_options;
while (arg != NULL)
{
@@ -260,7 +318,7 @@ powerpc_init_dialect (struct disassemble
if (end != NULL)
*end = 0;
- if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
+ if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
dialect = new_cpu;
else if (strcmp (arg, "32") == 0)
dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
@@ -274,20 +332,6 @@ powerpc_init_dialect (struct disassemble
arg = end;
}
- if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
- {
- if (info->mach == bfd_mach_ppc64)
- dialect |= PPC_OPCODE_64;
- else
- dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
- if (info->mach == bfd_mach_ppc_vle)
- dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE;
- else
- /* Choose a reasonable default. */
- dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
- | PPC_OPCODE_ALTIVEC);
- }
-
info->private_data = priv;
POWERPC_DIALECT(info) = dialect;
}
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.191
diff -u -p -r1.191 tc-ppc.c
--- gas/config/tc-ppc.c 14 Nov 2012 13:44:44 -0000 1.191
+++ gas/config/tc-ppc.c 22 Nov 2012 22:45:16 -0000
@@ -223,6 +223,7 @@ unsigned long nop_limit = 4;
/* The type of processor we are assembling for. This is one or more
of the PPC_OPCODE flags defined in opcode/ppc.h. */
ppc_cpu_t ppc_cpu = 0;
+ppc_cpu_t sticky = 0;
/* Flags set on encountering toc relocs. */
enum {
@@ -1160,7 +1161,7 @@ md_parse_option (int c, char *arg)
break;
case 'm':
- new_cpu = ppc_parse_cpu (ppc_cpu, arg);
+ new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg);
if (new_cpu != 0)
{
ppc_cpu = new_cpu;
@@ -4863,7 +4864,7 @@ ppc_machine (int ignore ATTRIBUTE_UNUSED
else
ppc_cpu = cpu_history[--curr_hist];
}
- else if ((new_cpu = ppc_parse_cpu (ppc_cpu, cpu_string)) != 0)
+ else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0)
ppc_cpu = new_cpu;
else
as_bad (_("invalid machine `%s'"), cpu_string);
Index: gas/testsuite/gas/ppc/astest2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/astest2.d,v
retrieving revision 1.8
diff -u -p -r1.8 astest2.d
--- gas/testsuite/gas/ppc/astest2.d 14 Nov 2012 13:44:45 -0000 1.8
+++ gas/testsuite/gas/ppc/astest2.d 23 Nov 2012 01:22:29 -0000
@@ -1,4 +1,4 @@
-#objdump: -Dr
+#objdump: -Dr -Mppc
#name: PowerPC test 2
.*
Index: ld/testsuite/ld-powerpc/plt1.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/plt1.d,v
retrieving revision 1.2
diff -u -p -r1.2 plt1.d
--- ld/testsuite/ld-powerpc/plt1.d 29 Oct 2012 09:25:53 -0000 1.2
+++ ld/testsuite/ld-powerpc/plt1.d 22 Nov 2012 23:52:02 -0000
@@ -8,7 +8,7 @@
Disassembly of section .text:
0+ <_start>:
- 0: (42 9f 00 05|05 00 9f 42) bcl- 20,4\*cr7\+so,4 .*
+ 0: (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,4 .*
4: (7f c8 02 a6|a6 02 c8 7f) mflr r30
8: (3f de 00 00|00 00 de 3f) addis r30,r30,0
(a|8): R_PPC_REL16_HA _GLOBAL_OFFSET_TABLE_\+0x(6|4)
Index: ld/testsuite/ld-powerpc/tlsexe.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsexe.d,v
retrieving revision 1.11
diff -u -p -r1.11 tlsexe.d
--- ld/testsuite/ld-powerpc/tlsexe.d 29 Oct 2012 09:25:53 -0000 1.11
+++ ld/testsuite/ld-powerpc/tlsexe.d 22 Nov 2012 23:52:02 -0000
@@ -71,7 +71,7 @@ Disassembly of section \.text:
.* (00 01 02 00|00 00 00 00) .*
.* <__glink_PLTresolve>:
.* (7d 88 02 a6|a6 02 88 7d) mflr r12
-.* (42 9f 00 05|05 00 9f 42) bcl- 20,4\*cr7\+so,.*
+.* (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.*
.* (7d 68 02 a6|a6 02 68 7d) mflr r11
.* (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
.* (7d 88 03 a6|a6 03 88 7d) mtlr r12
Index: ld/testsuite/ld-powerpc/tlsexetoc.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsexetoc.d,v
retrieving revision 1.12
diff -u -p -r1.12 tlsexetoc.d
--- ld/testsuite/ld-powerpc/tlsexetoc.d 29 Oct 2012 09:25:53 -0000 1.12
+++ ld/testsuite/ld-powerpc/tlsexetoc.d 22 Nov 2012 23:52:02 -0000
@@ -55,7 +55,7 @@ Disassembly of section \.text:
.* (00 01 02 28|00 00 00 00) .*
.* <__glink_PLTresolve>:
.* (7d 88 02 a6|a6 02 88 7d) mflr r12
-.* (42 9f 00 05|05 00 9f 42) bcl- 20,4\*cr7\+so,.*
+.* (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.*
.* (7d 68 02 a6|a6 02 68 7d) mflr r11
.* (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
.* (7d 88 03 a6|a6 03 88 7d) mtlr r12
Index: ld/testsuite/ld-powerpc/tlsopt1.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsopt1.d,v
retrieving revision 1.2
diff -u -p -r1.2 tlsopt1.d
--- ld/testsuite/ld-powerpc/tlsopt1.d 29 Oct 2012 09:25:53 -0000 1.2
+++ ld/testsuite/ld-powerpc/tlsopt1.d 22 Nov 2012 23:52:02 -0000
@@ -17,7 +17,7 @@ Disassembly of section \.no_opt1:
0+100000ec <\.no_opt1>:
.*: (38 62 80 08|08 80 62 38) addi r3,r2,-32760
.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
-.*: (41 82 00 10|10 00 82 41) beq- .*
+.*: (41 82 00 10|10 00 82 41) beq .*
.*: (4b ff ff f1|f1 ff ff 4b) bl 100000e8 <\.__tls_get_addr>
.*: (60 00 00 00|00 00 00 60) nop
.*: (48 00 00 0c|0c 00 00 48) b .*
Index: ld/testsuite/ld-powerpc/tlsopt1_32.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsopt1_32.d,v
retrieving revision 1.2
diff -u -p -r1.2 tlsopt1_32.d
--- ld/testsuite/ld-powerpc/tlsopt1_32.d 29 Oct 2012 09:25:53 -0000 1.2
+++ ld/testsuite/ld-powerpc/tlsopt1_32.d 22 Nov 2012 23:52:02 -0000
@@ -17,7 +17,7 @@ Disassembly of section \.no_opt1:
0+1800098 <\.no_opt1>:
.*: (38 6d ff f4|f4 ff 6d 38) addi r3,r13,-12
.*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
-.*: (41 82 00 0c|0c 00 82 41) beq- .*
+.*: (41 82 00 0c|0c 00 82 41) beq .*
.*: (4b ff ff f1|f1 ff ff 4b) bl 1800094 <__tls_get_addr>
.*: (48 00 00 08|08 00 00 48) b .*
.*: (4b ff ff e9|e9 ff ff 4b) bl 1800094 <__tls_get_addr>
Index: ld/testsuite/ld-powerpc/tlsopt2.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsopt2.d,v
retrieving revision 1.2
diff -u -p -r1.2 tlsopt2.d
--- ld/testsuite/ld-powerpc/tlsopt2.d 29 Oct 2012 09:25:53 -0000 1.2
+++ ld/testsuite/ld-powerpc/tlsopt2.d 22 Nov 2012 23:52:02 -0000
@@ -17,7 +17,7 @@ Disassembly of section \.no_opt2:
0+100000ec <\.no_opt2>:
.*: (38 62 80 08|08 80 62 38) addi r3,r2,-32760
.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
-.*: (41 82 00 08|08 00 82 41) beq- .*
+.*: (41 82 00 08|08 00 82 41) beq .*
.*: (38 62 80 08|08 80 62 38) addi r3,r2,-32760
.*: (4b ff ff ed|ed ff ff 4b) bl 100000e8 <\.__tls_get_addr>
.*: (60 00 00 00|00 00 00 60) nop
Index: ld/testsuite/ld-powerpc/tlsopt2_32.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsopt2_32.d,v
retrieving revision 1.2
diff -u -p -r1.2 tlsopt2_32.d
--- ld/testsuite/ld-powerpc/tlsopt2_32.d 29 Oct 2012 09:25:53 -0000 1.2
+++ ld/testsuite/ld-powerpc/tlsopt2_32.d 22 Nov 2012 23:52:02 -0000
@@ -17,7 +17,7 @@ Disassembly of section \.no_opt2:
0+1800098 <\.no_opt2>:
.*: (38 6d ff f4|f4 ff 6d 38) addi r3,r13,-12
.*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
-.*: (41 82 00 08|08 00 82 41) beq- .*
+.*: (41 82 00 08|08 00 82 41) beq .*
.*: (38 6d ff f4|f4 ff 6d 38) addi r3,r13,-12
.*: (4b ff ff ed|ed ff ff 4b) bl 1800094 <__tls_get_addr>
#pass
Index: ld/testsuite/ld-powerpc/tlsopt4.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsopt4.d,v
retrieving revision 1.2
diff -u -p -r1.2 tlsopt4.d
--- ld/testsuite/ld-powerpc/tlsopt4.d 29 Oct 2012 09:25:53 -0000 1.2
+++ ld/testsuite/ld-powerpc/tlsopt4.d 22 Nov 2012 23:52:02 -0000
@@ -17,7 +17,7 @@ Disassembly of section \.opt1:
0+100000ec <\.opt1>:
.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
-.*: (41 82 00 10|10 00 82 41) beq- .*
+.*: (41 82 00 10|10 00 82 41) beq .*
.*: (60 00 00 00|00 00 00 60) nop
.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
.*: (48 00 00 0c|0c 00 00 48) b .*
@@ -29,7 +29,7 @@ Disassembly of section \.opt2:
0+1000010c <\.opt2>:
.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
-.*: (41 82 00 08|08 00 82 41) beq- .*
+.*: (41 82 00 08|08 00 82 41) beq .*
.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
.*: (60 00 00 00|00 00 00 60) nop
.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
Index: ld/testsuite/ld-powerpc/tlsopt4_32.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsopt4_32.d,v
retrieving revision 1.2
diff -u -p -r1.2 tlsopt4_32.d
--- ld/testsuite/ld-powerpc/tlsopt4_32.d 29 Oct 2012 09:25:53 -0000 1.2
+++ ld/testsuite/ld-powerpc/tlsopt4_32.d 22 Nov 2012 23:52:02 -0000
@@ -17,7 +17,7 @@ Disassembly of section \.opt1:
0+1800098 <\.opt1>:
.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
.*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
-.*: (41 82 00 0c|0c 00 82 41) beq- .*
+.*: (41 82 00 0c|0c 00 82 41) beq .*
.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
.*: (48 00 00 08|08 00 00 48) b .*
.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
@@ -27,7 +27,7 @@ Disassembly of section \.opt2:
0+18000b0 <\.opt2>:
.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
.*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
-.*: (41 82 00 08|08 00 82 41) beq- .*
+.*: (41 82 00 08|08 00 82 41) beq .*
.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
Index: ld/testsuite/ld-powerpc/tlsso.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlsso.d,v
retrieving revision 1.11
diff -u -p -r1.11 tlsso.d
--- ld/testsuite/ld-powerpc/tlsso.d 29 Oct 2012 09:25:53 -0000 1.11
+++ ld/testsuite/ld-powerpc/tlsso.d 22 Nov 2012 23:52:02 -0000
@@ -59,7 +59,7 @@ Disassembly of section \.text:
.* (00 01 02 20|00 00 00 00) .*
.* <__glink_PLTresolve>:
.* (7d 88 02 a6|a6 02 88 7d) mflr r12
-.* (42 9f 00 05|05 00 9f 42) bcl- 20,4\*cr7\+so,.*
+.* (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.*
.* (7d 68 02 a6|a6 02 68 7d) mflr r11
.* (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
.* (7d 88 03 a6|a6 03 88 7d) mtlr r12
Index: ld/testsuite/ld-powerpc/tlstocso.d
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/tlstocso.d,v
retrieving revision 1.10
diff -u -p -r1.10 tlstocso.d
--- ld/testsuite/ld-powerpc/tlstocso.d 29 Oct 2012 09:25:53 -0000 1.10
+++ ld/testsuite/ld-powerpc/tlstocso.d 22 Nov 2012 23:52:02 -0000
@@ -43,7 +43,7 @@ Disassembly of section \.text:
.* (00 01 02 18|00 00 00 00) .*
.* <__glink_PLTresolve>:
.* (7d 88 02 a6|a6 02 88 7d) mflr r12
-.* (42 9f 00 05|05 00 9f 42) bcl- 20,4\*cr7\+so,.*
+.* (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.*
.* (7d 68 02 a6|a6 02 68 7d) mflr r11
.* (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
.* (7d 88 03 a6|a6 03 88 7d) mtlr r12
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Fix gdb disassemble for power6/power7 instructions
2012-11-23 3:29 ` Alan Modra
@ 2012-11-23 17:07 ` Edjunior Barbosa Machado
2012-11-28 18:38 ` Ulrich Weigand
0 siblings, 1 reply; 6+ messages in thread
From: Edjunior Barbosa Machado @ 2012-11-23 17:07 UTC (permalink / raw)
To: Alan Modra; +Cc: gdb-patches, binutils
On 11/23/2012 01:28 AM, Alan Modra wrote:
> One of the effects of updating to a power7 default is that conditional
> branch hints are displayed for "at" style hints rather than the older
> "y" hints. When using "y" hints the disassembler always showed the
> hint, eg. "bne-" or "bne+". Now you'll see "bne" most times. This
> meant updating the testsuite. I made one gas test disassemble for
> plain ppc just to ensure the older "y" hints continue to be available.
>
> Committed.
Thanks a lot for the patch, Alan. This also fixes the issues with gdb
disassemble for power6 and power7 instructions.
With these changes on powerpc_init_dialect(), I'd suggest to remove the info->mach
checking from gdb. Ok?
--
Edjunior
2012-11-23 Edjunior Machado <emachado@linux.vnet.ibm.com>
* rs6000-tdep.c (gdb_print_insn_powerpc): Remove info->mach checking,
since now it is being done in binutils' powerpc_init_dialect().
---
gdb/rs6000-tdep.c | 15 ---------------
1 files changed, 0 insertions(+), 15 deletions(-)
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 1797cc5..07b81bc 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -3084,21 +3084,6 @@ find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
static int
gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
{
- if (!info->disassembler_options)
- {
- /* When debugging E500 binaries and disassembling code containing
- E500-specific (SPE) instructions, one sometimes sees AltiVec
- instructions instead. The opcode spaces for SPE instructions
- and AltiVec instructions overlap, and specifiying the "any" cpu
- looks for AltiVec instructions first. If we know we're
- debugging an E500 binary, however, we can specify the "e500x2"
- cpu and get much more sane disassembly output. */
- if (info->mach == bfd_mach_ppc_e500)
- info->disassembler_options = "e500x2";
- else
- info->disassembler_options = "any";
- }
-
if (info->endian == BFD_ENDIAN_BIG)
return print_insn_big_powerpc (memaddr, info);
else
--
1.7.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Fix gdb disassemble for power6/power7 instructions
2012-11-23 17:07 ` Edjunior Barbosa Machado
@ 2012-11-28 18:38 ` Ulrich Weigand
2012-11-28 20:17 ` Edjunior Barbosa Machado
0 siblings, 1 reply; 6+ messages in thread
From: Ulrich Weigand @ 2012-11-28 18:38 UTC (permalink / raw)
To: Edjunior Barbosa Machado; +Cc: Alan Modra, gdb-patches, binutils
Edjunior Machado wrote:
> * rs6000-tdep.c (gdb_print_insn_powerpc): Remove info->mach checking,
> since now it is being done in binutils' powerpc_init_dialect().
This is OK.
Thanks,
Ulrich
--
Dr. Ulrich Weigand
GNU Toolchain for Linux on System z and Cell BE
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Fix gdb disassemble for power6/power7 instructions
2012-11-28 18:38 ` Ulrich Weigand
@ 2012-11-28 20:17 ` Edjunior Barbosa Machado
0 siblings, 0 replies; 6+ messages in thread
From: Edjunior Barbosa Machado @ 2012-11-28 20:17 UTC (permalink / raw)
To: Ulrich Weigand; +Cc: Alan Modra, gdb-patches, binutils
On 11/28/2012 04:38 PM, Ulrich Weigand wrote:
> Edjunior Machado wrote:
>
>> * rs6000-tdep.c (gdb_print_insn_powerpc): Remove info->mach checking,
>> since now it is being done in binutils' powerpc_init_dialect().
>
> This is OK.
Thanks for the feedback, Ulrich. I've just checked in:
http://sourceware.org/ml/gdb-cvs/2012-11/msg00185.html
Thanks,
--
Edjunior Barbosa Machado
IBM Linux Technology Center
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-11-28 20:17 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-11-13 5:46 [PATCH] Fix gdb disassemble for power6/power7 instructions Edjunior Barbosa Machado
2012-11-13 23:46 ` Alan Modra
2012-11-23 3:29 ` Alan Modra
2012-11-23 17:07 ` Edjunior Barbosa Machado
2012-11-28 18:38 ` Ulrich Weigand
2012-11-28 20:17 ` Edjunior Barbosa Machado
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