Re: PATCH RFA: Fix simulator handling of floating point absolute value

[Daniel Jacobowitz <drow@false.org>]

On Fri, Jul 08, 2005 at 10:51:11AM -0700, Ian Lance Taylor wrote:
> > I have no references for this concern, but could you check that this
> > change is appropriate for at least MN10300 and SH64, since they share
> > ths code?
> 
> I think I'll need a little help to fully satisfy this request.  The
> issue is how the fabs instruction on the MN10300 and SH handle NaNs.
> This is something that can only be determined via a detailed processor
> manual or by testing on real hardware.
> 
> The manual for the SH4a is, fortunately, clear: the fabs instruction
> is described as "FRn & H'7FFF FFFF -> FRn."  So for the SH4a, at
> least, my proposed patch is correct.
> 
> I found a processor manual for the MN10300 AM33 on the web, but all it
> says about the fabs instruction is "This takes an absolute value of
> the register (FSm), and stores the result in the register (FSn)."
> 
> A hardware designer implementing the floating point absolute
> instruction has a choice.  He or she can implement a simple
> instruction which clears the sign bit.  Or he or she can implement an
> instruction which checks for NaN input, and, in that case, does not
> clear the sign bit.  Since sim-fpu.c is intended to be for generic
> use, I think it is reasonable to bet on the simple implementation, and
> force a simulator for a processor which takes the complex
> implementation to do something different.  Especially since it is
> correct for at least two out of three processors.

That's good enough for me; thank you, Ian.  Patch is OK.

-- 
Daniel Jacobowitz
CodeSourcery, LLC