Re: [PATCH] Aarch64-SIM: BLR opcode does not support XLR register properly.

[Carlo Bramini <carlo.bramix@libero.it>]

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Hello,
please excuse me, I just discovered that there are multiple ChangeLog files and probably I have to provide an entry for the right one. Sorry for my mistake in previous message.

Sincerely.

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./sim/aarch64/ChangeLog:

2020-02-05 Carlo Bramini <carlo_bramini@users.sourceforge.net>

* simulator.c: Fix BLR opcode for supporting XLR register as source operand.

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> ---------- Messaggio originale ----------Da: Carlo Bramini <carlo.bramix@libero.it>A: gdb-patches@sourceware.org
> Data: 5 febbraio 2020 alle 18.14Oggetto: Re: [PATCH] Aarch64-SIM: BLR opcode does not support XLR register properly.
> Hello,thank you very much for your quick reply.I made a new patch, which includes just the fix to BLR opcode. I'm also adding an entry for the ChangeLog file, as you requested.
> Sincerely.
> ---
> ./ChangeLog:
> 2020-02-05 Carlo Bramini <carlo_bramini@users.sourceforge.net>
> * sim/aarch64/simulator.c: Fix BLR opcode for supporting XLR register as source operand.
> 
> ---
> > Il 5 febbraio 2020 alle 12.39 Luis Machado <luis.machado@linaro.org> ha scritto:
> > 
> > Hi Carlo,
> > Thanks for the patch.
> > I'd include just the fix itself and not any other cosmetic changes tothe code, like moving/removing return statements. The statements areuseless, but it makes the patch cleaner that way.
> > It would also make it clear it is a reasonably obvious fix, which can bepushed without a FSF assignment. Though it would be nice to have one inplace for further contributions.
> > Other than that, it is missing a ChangeLog entry, but it is not a bigdeal for this particular change as one can quickly write one.
> > Luis
> > On 2/5/20 8:21 AM, Carlo Bramini wrote:> After a suggestion received at your bugzilla, I'm posting here a patch. Detailed explanation can be found here:
> > > https://sourceware.org/bugzilla/show_bug.cgi?id=25318
> > > 
> > > Thank you very much for your time and your support.Sincerely.

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diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 84919d6b1f..715a7f4b6b 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -13437,13 +13437,13 @@ br (sim_cpu *cpu)
 static void
 blr (sim_cpu *cpu)
 {
-  unsigned rn = INSTR (9, 5);
+  uint64_t target = aarch64_get_reg_u64 (cpu, INSTR (9, 5), NO_SP);
 
   TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
   /* The pseudo code in the spec says we update LR before fetching.
      the value from the rn.  */
   aarch64_save_LR (cpu);
-  aarch64_set_next_PC (cpu, aarch64_get_reg_u64 (cpu, rn, NO_SP));
+  aarch64_set_next_PC (cpu, target);
 
   if (TRACE_BRANCH_P (cpu))
     {