[PATCH] Aarch64-SIM: BLR opcode does not support XLR register properly.

[Carlo Bramini <carlo.bramix@libero.it>]

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After a suggestion received at your bugzilla, I'm posting here a patch. Detailed explanation can be found here:

https://sourceware.org/bugzilla/show_bug.cgi?id=25318

Thank you very much for your time and your support.
Sincerely.

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diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 60972976fc..0b8dd8a146 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -1174,7 +1174,7 @@ ldrsw_abs (sim_cpu *cpu, uint32_t offset)
   val = aarch64_get_mem_s32 (cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
 			     + SCALE (offset, 32));
   /* The target register may not be SP but the source may be.  */
-  return aarch64_set_reg_s64 (cpu, rt, NO_SP, val);
+  aarch64_set_reg_s64 (cpu, rt, NO_SP, val);
 }
 
 /* 64 bit load sign-extended 32 bit unscaled signed 9 bit
@@ -13437,13 +13437,13 @@ br (sim_cpu *cpu)
 static void
 blr (sim_cpu *cpu)
 {
-  unsigned rn = INSTR (9, 5);
+  uint64_t target = aarch64_get_reg_u64 (cpu, INSTR (9, 5), NO_SP);
 
   TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
   /* The pseudo code in the spec says we update LR before fetching.
      the value from the rn.  */
   aarch64_save_LR (cpu);
-  aarch64_set_next_PC (cpu, aarch64_get_reg_u64 (cpu, rn, NO_SP));
+  aarch64_set_next_PC (cpu, target);
 
   if (TRACE_BRANCH_P (cpu))
     {
@@ -14222,7 +14222,8 @@ dexBr (sim_cpu *cpu)
   switch (group2)
     {
     case BR_IMM_000:
-      return dexBranchImmediate (cpu);
+      dexBranchImmediate (cpu);
+      return;
 
     case BR_IMMCMP_001:
       /* Compare has bit 25 clear while test has it set.  */