From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 86979 invoked by alias); 5 Feb 2020 17:25:45 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 84609 invoked by uid 89); 5 Feb 2020 17:25:45 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL,BAYES_00,FOREIGN_BODY1,FREEMAIL_FROM,GIT_PATCH_2,LIBERO,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=no version=3.3.1 spammy=H*c:PHrt, HImportance:Normal, sincerely, H*c:HHHHHHHH X-HELO: libero.it Received: from smtp-35-i2.italiaonline.it (HELO libero.it) (213.209.12.35) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 05 Feb 2020 17:25:39 +0000 Received: from oxapps-12-071.iol.local ([10.101.8.81]) by smtp-35.iol.local with ESMTPA id zOQiiSG05MAUpzOQiixLoD; Wed, 05 Feb 2020 18:25:37 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1580923537; bh=dCpwKAc8lr8RK+Zc4v6qgZUcDWntSqrXQfJvIWB1lg4=; h=Date:From:To:In-Reply-To:References:Subject; b=uArmrzVYcpoxMo0lpa5OzdSamuMFHW/3ecwx9SsfhoqSDHeGaULr8pF9Q+4j7udbj qjCD/UJj/Wo1w58fADHEmE925MSdZZwJvwS5vmGK4bHdU/7ZRkGqUzVGdJ9UoZ4Pky AHFCINJBLa/OYFls54e7lv2wDhXsFfYxZHzGE5JNpYuOqowSowCspUSC1qA9tUXqBS LgL9snP/RB869upsepT1TIdtSSL/nXvKTqwAN0hQBb9ZhtQ8ITIuY00gApaBdew0db jIpHkcjTHRe8wnkYxvmVtjoaSkPrkUmLe3bjQVnlq7K0ILM7KSMBTHOOn81mArgfA6 zXKqFJA7swL9w== Date: Wed, 05 Feb 2020 17:25:00 -0000 From: Carlo Bramini To: gdb-patches@sourceware.org Message-ID: <1213380262.792613.1580923536993@mail1.libero.it> In-Reply-To: <1071809675.829947.1580922883716@mail1.libero.it> References: <2054623523.792939.1580901671145@mail1.libero.it> <9c6afb97-dabc-3d2f-4980-db387930a8e6@linaro.org> <1071809675.829947.1580922883716@mail1.libero.it> Subject: Re: [PATCH] Aarch64-SIM: BLR opcode does not support XLR register properly. MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_792612_14782775.1580923536992" X-SW-Source: 2020-02/txt/msg00106.txt.bz2 ------=_Part_792612_14782775.1580923536992 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-length: 1924 Hello, please excuse me, I just discovered that there are multiple ChangeLog files and probably I have to provide an entry for the right one. Sorry for my mistake in previous message. Sincerely. --- ./sim/aarch64/ChangeLog: 2020-02-05 Carlo Bramini * simulator.c: Fix BLR opcode for supporting XLR register as source operand. --- > ---------- Messaggio originale ----------Da: Carlo Bramini A: gdb-patches@sourceware.org > Data: 5 febbraio 2020 alle 18.14Oggetto: Re: [PATCH] Aarch64-SIM: BLR opcode does not support XLR register properly. > Hello,thank you very much for your quick reply.I made a new patch, which includes just the fix to BLR opcode. I'm also adding an entry for the ChangeLog file, as you requested. > Sincerely. > --- > ./ChangeLog: > 2020-02-05 Carlo Bramini > * sim/aarch64/simulator.c: Fix BLR opcode for supporting XLR register as source operand. > > --- > > Il 5 febbraio 2020 alle 12.39 Luis Machado ha scritto: > > > > Hi Carlo, > > Thanks for the patch. > > I'd include just the fix itself and not any other cosmetic changes tothe code, like moving/removing return statements. The statements areuseless, but it makes the patch cleaner that way. > > It would also make it clear it is a reasonably obvious fix, which can bepushed without a FSF assignment. Though it would be nice to have one inplace for further contributions. > > Other than that, it is missing a ChangeLog entry, but it is not a bigdeal for this particular change as one can quickly write one. > > Luis > > On 2/5/20 8:21 AM, Carlo Bramini wrote:> After a suggestion received at your bugzilla, I'm posting here a patch. Detailed explanation can be found here: > > > https://sourceware.org/bugzilla/show_bug.cgi?id=25318 > > > > > > Thank you very much for your time and your support.Sincerely. ------=_Part_792612_14782775.1580923536992 Content-Type: application/octet-stream; name=sim_aarch64.patch Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename=sim_aarch64.patch X-Part-Id: 1093a839ad724673be5e909e1bd1352a Content-length: 907 ZGlmZiAtLWdpdCBhL3NpbS9hYXJjaDY0L3NpbXVsYXRvci5jIGIvc2ltL2Fh cmNoNjQvc2ltdWxhdG9yLmMKaW5kZXggODQ5MTlkNmIxZi4uNzE1YTdmNGI2 YiAxMDA2NDQKLS0tIGEvc2ltL2FhcmNoNjQvc2ltdWxhdG9yLmMKKysrIGIv c2ltL2FhcmNoNjQvc2ltdWxhdG9yLmMKQEAgLTEzNDM3LDEzICsxMzQzNywx MyBAQCBiciAoc2ltX2NwdSAqY3B1KQogc3RhdGljIHZvaWQKIGJsciAoc2lt X2NwdSAqY3B1KQogewotICB1bnNpZ25lZCBybiA9IElOU1RSICg5LCA1KTsK KyAgdWludDY0X3QgdGFyZ2V0ID0gYWFyY2g2NF9nZXRfcmVnX3U2NCAoY3B1 LCBJTlNUUiAoOSwgNSksIE5PX1NQKTsKIAogICBUUkFDRV9ERUNPREUgKGNw dSwgImVtdWxhdGVkIGF0IGxpbmUgJWQiLCBfX0xJTkVfXyk7CiAgIC8qIFRo ZSBwc2V1ZG8gY29kZSBpbiB0aGUgc3BlYyBzYXlzIHdlIHVwZGF0ZSBMUiBi ZWZvcmUgZmV0Y2hpbmcuCiAgICAgIHRoZSB2YWx1ZSBmcm9tIHRoZSBybi4g ICovCiAgIGFhcmNoNjRfc2F2ZV9MUiAoY3B1KTsKLSAgYWFyY2g2NF9zZXRf bmV4dF9QQyAoY3B1LCBhYXJjaDY0X2dldF9yZWdfdTY0IChjcHUsIHJuLCBO T19TUCkpOworICBhYXJjaDY0X3NldF9uZXh0X1BDIChjcHUsIHRhcmdldCk7 CiAKICAgaWYgKFRSQUNFX0JSQU5DSF9QIChjcHUpKQogICAgIHsK ------=_Part_792612_14782775.1580923536992--