[ltt-dev] [PATCH 00/11] Simplify system dependent URCU code

[ltt-dev] [PATCH 00/11] Simplify system dependent URCU code

[Paolo Bonzini]

This patch series simplifies the system dependent code in the
userspace RCU library by removing redundant definitions and
moving them to common code.  The common code is then less
subject to bitrotting because it can be tested on x86 too.

Patches 1 and 2 are simple Makefile cleanups.

Patches 3 and 4 take care of urcu/arch_*.  Definitions for
rmb/wmb/mc/rmc/wmc can often be omitted, and even mb can
for example defer to the compiler-provided __sync_synchronize.

Patch 5 removes a redundant definition that is probably
a residual of libatomicops, and so does patch 6.

Patches 7 to 9 take care of urcu/uatomic_arch_*, by defining
fallbacks using __sync_* builtins.  S390 can use them completely
without basically changing the generated code, while other
architectures still require a little help.

Patches 10 and 11 show how this helps by supporting
compilation to unknown architectures that support GCC
builtins (MIPS and IA64 are serviced nicely for example),
and by supporting Alpha (obviously chosen as an example of
read_barrier_depends) with ~20 lines of non-comment code.

Patch 12 is not meant to be committed, but was used to test
the atomic op implementations on x86_64.  It is not counted
in the diffstat below.

HTH,

Paolo

Paolo Bonzini (11+1):
  use kernel style makefile output
  use autoconf symbolic linking
  add urcu/arch_defaults.h
  define sync_core for x86 PIC
  __SIZEOF_LONG__ is always defined by GCC
  remove compat_uatomic_cmpxchg #define from non-x86
  add uatomic_gcc.h, use it for default definitions
  use uatomic_gcc.h
  move whether atomic byte/short exists to uatomic_arch_*.h
  add Alpha support
  support compiling on unknown architectures
  test uatomic_gcc.h

 Makefile.am                 |   14 +-
 configure.ac                |   15 ++-
 tests/test_uatomic.c        |   15 +-
 urcu/arch_alpha.h           |   49 +++++
 urcu/arch_defaults.h        |  109 ++++++++++
 urcu/arch_ppc.h             |   50 +-----
 urcu/arch_s390.h            |   46 +----
 urcu/arch_sparc64.h         |   51 +-----
 urcu/arch_x86.h             |   68 +------
 urcu/uatomic_arch_alpha.h   |   32 +++
 urcu/uatomic_arch_ppc.h     |  143 +-------------
 urcu/uatomic_arch_s390.h    |  193 +------------------
 urcu/uatomic_arch_sparc64.h |  109 +----------
 urcu/uatomic_arch_x86.h     |   37 ++----
 urcu/uatomic_gcc.h          |  293 +++++++++++++++++++++++++++++++++++++++++++
 15 files changed, 538 insertions(+), 686 deletions(-)
 create mode 100644 urcu/arch_alpha.h
 create mode 100644 urcu/arch_defaults.h
 create mode 100644 urcu/uatomic_arch_alpha.h
 create mode 100644 urcu/uatomic_gcc.h

[ltt-dev] [PATCH 01/11] use kernel style makefile output

[Paolo Bonzini]

A breath of fresh air.  Requires Automake 1.11, but the
patch degrades gracefully.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 configure.ac |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/configure.ac b/configure.ac
index 48f906d..c797831 100644
--- a/configure.ac
+++ b/configure.ac
@@ -7,6 +7,8 @@ AC_CONFIG_AUX_DIR([config])
 AC_CANONICAL_TARGET
 AC_CANONICAL_HOST
 AM_INIT_AUTOMAKE([foreign dist-bzip2 no-dist-gzip])
+m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
+
 AC_CONFIG_SRCDIR([urcu.h])
 AM_PROG_MKDIR_P
 
-- 
1.6.6

[ltt-dev] [PATCH 01/11] use kernel style makefile output

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> A breath of fresh air.  Requires Automake 1.11, but the
> patch degrades gracefully.
> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>

Acked-by: Mathieu Desnoyers <mathieu.desnoyers at efficios.com>

> ---
>  configure.ac |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index 48f906d..c797831 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -7,6 +7,8 @@ AC_CONFIG_AUX_DIR([config])
>  AC_CANONICAL_TARGET
>  AC_CANONICAL_HOST
>  AM_INIT_AUTOMAKE([foreign dist-bzip2 no-dist-gzip])
> +m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
> +
>  AC_CONFIG_SRCDIR([urcu.h])
>  AM_PROG_MKDIR_P
>  
> -- 
> 1.6.6
> 
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 02/11] use autoconf symbolic linking

[Paolo Bonzini]

Instead of copying.  This is less error-prone while developing and
lets Automake handle more stuff.  The definition of the two variables
in configure.ac is changed later.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 Makefile.am  |    8 --------
 configure.ac |    6 ++++++
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/Makefile.am b/Makefile.am
index 4f915e1..3e0e164 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -38,16 +38,3 @@ liburcu_signal_la_CFLAGS = -DRCU_SIGNAL
 liburcu_bp_la_SOURCES = urcu-bp.c urcu-pointer.c $(COMPAT)
 
 liburcu_defer_la_SOURCES = urcu-defer.c $(COMPAT)
-
-$(top_srcdir)/*.h $(top_srcdir)/*.c: urcu/arch.h urcu/uatomic_arch.h
-
-urcu/arch.h: $(top_srcdir)/urcu/arch_ at ARCHTYPE@.h
-	$(mkdir_p) $(top_builddir)/urcu
-	cp -f $(top_srcdir)/urcu/arch_ at ARCHTYPE@.h $(top_builddir)/urcu/arch.h
-
-urcu/uatomic_arch.h: $(top_srcdir)/urcu/uatomic_arch_ at ARCHTYPE@.h
-	$(mkdir_p) $(top_builddir)/urcu
-	cp -f $(top_srcdir)/urcu/uatomic_arch_ at ARCHTYPE@.h $(top_builddir)/urcu/uatomic_arch.h
-
-clean-local:
-	rm -f urcu/arch.h urcu/uatomic_arch.h
diff --git a/configure.ac b/configure.ac
index c797831..4580f38 100644
--- a/configure.ac
+++ b/configure.ac
@@ -56,6 +56,8 @@ esac
 if test "$ARCHTYPE" = "unknown"; then
 	AC_MSG_ERROR([Unable to detect the architecture.])
 fi
+UATOMICSRC=urcu/uatomic_arch_$ARCHTYPE.h
+ARCHSRC=urcu/arch_$ARCHTYPE.h
 AC_SUBST(ARCHTYPE)
 AC_SUBST(SUBARCHTYPE)
 
@@ -204,6 +206,10 @@ AC_CHECK_FUNCS(
 
 CFLAGS=$saved_CFLAGS
 
+AC_CONFIG_LINKS([
+	urcu/arch.h:$ARCHSRC
+	urcu/uatomic_arch.h:$UATOMICSRC
+])
 AC_CONFIG_FILES([
 	Makefile
 	tests/Makefile
-- 
1.6.6

[ltt-dev] [PATCH 02/11] use autoconf symbolic linking

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> Instead of copying.  This is less error-prone while developing and
> lets Automake handle more stuff.  The definition of the two variables
> in configure.ac is changed later.
> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>

Acked-by: Mathieu Desnoyers <mathieu.desnoyers at efficios.com>

> ---
>  Makefile.am  |    8 --------
>  configure.ac |    6 ++++++
>  2 files changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/Makefile.am b/Makefile.am
> index 4f915e1..3e0e164 100644
> --- a/Makefile.am
> +++ b/Makefile.am
> @@ -38,16 +38,3 @@ liburcu_signal_la_CFLAGS = -DRCU_SIGNAL
>  liburcu_bp_la_SOURCES = urcu-bp.c urcu-pointer.c $(COMPAT)
>  
>  liburcu_defer_la_SOURCES = urcu-defer.c $(COMPAT)
> -
> -$(top_srcdir)/*.h $(top_srcdir)/*.c: urcu/arch.h urcu/uatomic_arch.h
> -
> -urcu/arch.h: $(top_srcdir)/urcu/arch_ at ARCHTYPE@.h
> -	$(mkdir_p) $(top_builddir)/urcu
> -	cp -f $(top_srcdir)/urcu/arch_ at ARCHTYPE@.h $(top_builddir)/urcu/arch.h
> -
> -urcu/uatomic_arch.h: $(top_srcdir)/urcu/uatomic_arch_ at ARCHTYPE@.h
> -	$(mkdir_p) $(top_builddir)/urcu
> -	cp -f $(top_srcdir)/urcu/uatomic_arch_ at ARCHTYPE@.h $(top_builddir)/urcu/uatomic_arch.h
> -
> -clean-local:
> -	rm -f urcu/arch.h urcu/uatomic_arch.h
> diff --git a/configure.ac b/configure.ac
> index c797831..4580f38 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -56,6 +56,8 @@ esac
>  if test "$ARCHTYPE" = "unknown"; then
>  	AC_MSG_ERROR([Unable to detect the architecture.])
>  fi
> +UATOMICSRC=urcu/uatomic_arch_$ARCHTYPE.h
> +ARCHSRC=urcu/arch_$ARCHTYPE.h
>  AC_SUBST(ARCHTYPE)
>  AC_SUBST(SUBARCHTYPE)
>  
> @@ -204,6 +206,10 @@ AC_CHECK_FUNCS(
>  
>  CFLAGS=$saved_CFLAGS
>  
> +AC_CONFIG_LINKS([
> +	urcu/arch.h:$ARCHSRC
> +	urcu/uatomic_arch.h:$UATOMICSRC
> +])
>  AC_CONFIG_FILES([
>  	Makefile
>  	tests/Makefile
> -- 
> 1.6.6
> 
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 03/11] add urcu/arch_defaults.h

[Paolo Bonzini]

Most of the memory barrier definitions are shared between all
architectures, especially smp_* and mc/rmc/wmc.  Put them in
a common file.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/arch_defaults.h |  109 ++++++++++++++++++++++++++++++++++++++++++++++++++
 urcu/arch_ppc.h      |   50 +---------------------
 urcu/arch_s390.h     |   38 +----------------
 urcu/arch_sparc64.h  |   51 +----------------------
 urcu/arch_x86.h      |   64 +++--------------------------
 5 files changed, 122 insertions(+), 190 deletions(-)
 create mode 100644 urcu/arch_defaults.h

diff --git a/urcu/arch_defaults.h b/urcu/arch_defaults.h
new file mode 100644
index 0000000..0cc659e
--- /dev/null
+++ b/urcu/arch_defaults.h
@@ -0,0 +1,121 @@
+#ifndef _URCU_ARCH_DEFAULTS_H
+#define _URCU_ARCH_DEFAULTS_H
+
+/*
+ * arch_defaults.h: common definitions for multiple architectures.
+ *
+ * Copyright (c) 2010 Paolo Bonzini <pbonzini at redhat.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+*
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef CACHE_LINE_SIZE
+#define CACHE_LINE_SIZE	64
+#endif
+
+#if !defined mc && !defined rmc && !defined wmc
+#define CONFIG_HAVE_MEM_COHERENCY
+
+#ifndef mb
+#define mb()    __sync_synchronize()
+#endif
+
+#ifndef rmb
+#define rmb()    mb()
+#endif
+
+#ifndef wmb
+#define wmb()    mb()
+#endif
+
+#define mc()	 barrier()
+#define rmc()	 barrier()
+#define wmc()	 barrier()
+#else
+/*
+ * Architectures without cache coherency need something like the following:
+ *
+ * #define mb()	mc()
+ * #define rmb()	rmc()
+ * #define wmb()	wmc()
+ * #define mc()	arch_cache_flush()        // mandatory
+ * #define rmc()	arch_cache_flush_read()
+ * #define wmc()	arch_cache_flush_write()
+ */
+
+#ifndef mb
+#define mb()    mc()
+#endif
+
+#ifndef rmb
+#define rmb()    rmc()
+#endif
+
+#ifndef wmb
+#define wmb()    wmc()
+#endif
+
+#ifndef rmc
+#define rmc()    mc()
+#endif
+
+#ifndef wmc
+#define wmc()    mc()
+#endif
+#endif
+
+/* Nop everywhere except on alpha. */
+#ifndef read_barrier_depends
+#define read_barrier_depends()
+#endif
+
+#ifdef CONFIG_RCU_SMP
+#define smp_mb()	mb()
+#define smp_rmb()	rmb()
+#define smp_wmb()	wmb()
+#define smp_mc()	mc()
+#define smp_rmc()	rmc()
+#define smp_wmc()	wmc()
+#define smp_read_barrier_depends()	read_barrier_depends()
+#else
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#define smp_mc()	barrier()
+#define smp_rmc()	barrier()
+#define smp_wmc()	barrier()
+#define smp_read_barrier_depends()
+#endif
+
+#ifndef cpu_relax
+#define cpu_relax()	 barrier()
+#endif
+
+#ifndef sync_core
+#define sync_core()	 mb()
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _URCU_ARCH_DEFAULTS_H */
diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h
index c1762ae..f925d07 100644
--- a/urcu/arch_ppc.h
+++ b/urcu/arch_ppc.h
@@ -29,8 +29,6 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 /* Include size of POWER5+ L3 cache lines: 256 bytes */
 #define CACHE_LINE_SIZE	256
 
@@ -39,55 +37,11 @@ extern "C" {
 #endif
 
 #define mb()    asm volatile("sync":::"memory")
-#define rmb()   asm volatile("sync":::"memory")
-#define wmb()   asm volatile("sync"::: "memory")
-
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_RCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-	barrier();
-}
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
  */
-static inline void sync_core()
-{
-	asm volatile("isync" : : : "memory");
-}
+#define sync_core()	asm volatile("isync" : : : "memory")
 
 #define mftbl()						\
 	({ 						\
@@ -123,4 +77,6 @@ static inline cycles_t get_cycles (void)
 }
 #endif
 
+#include <urcu/arch_defaults.h>
+
 #endif /* _URCU_ARCH_PPC_H */
diff --git a/urcu/arch_s390.h b/urcu/arch_s390.h
index 22a1853..0982112 100644
--- a/urcu/arch_s390.h
+++ b/urcu/arch_s390.h
@@ -35,8 +35,6 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 #define CACHE_LINE_SIZE	128
 
 #ifndef __SIZEOF_LONG__
@@ -52,40 +50,6 @@ extern "C" {
 #endif
 
 #define mb()    __asm__ __volatile__("bcr 15,0" : : : "memory")
-#define rmb()   __asm__ __volatile__("bcr 15,0" : : : "memory")
-#define wmb()   __asm__ __volatile__("bcr 15,0" : : : "memory")
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_RCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-	barrier();
-}
-
-static inline void sync_core()
-{
-	__asm__ __volatile__("bcr 15,0" : : : "memory");
-}
 
 typedef unsigned long long cycles_t;
 
@@ -102,4 +66,6 @@ static inline cycles_t get_cycles (void)
 }
 #endif
 
+#include <urcu/arch_defaults.h>
+
 #endif /* _URCU_ARCH_S390_H */
diff --git a/urcu/arch_sparc64.h b/urcu/arch_sparc64.h
index 54c4c3c..c906168 100644
--- a/urcu/arch_sparc64.h
+++ b/urcu/arch_sparc64.h
@@ -29,8 +29,6 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 #define CACHE_LINE_SIZE	256
 
 #ifndef BITS_PER_LONG
@@ -50,53 +48,6 @@ __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"	\
 #define rmb()    membar_safe("#LoadLoad")
 #define wmb()    membar_safe("#StoreStore")
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_RCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-	barrier();
-}
-
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-static inline void sync_core()
-{
-	mb();
-}
-
 typedef unsigned long long cycles_t;
 
 static inline cycles_t get_cycles (void)
@@ -108,4 +59,6 @@ static inline cycles_t get_cycles (void)
 }
 #endif
 
+#include <urcu/arch_defaults.h>
+
 #endif /* _URCU_ARCH_SPARC64_H */
diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index 4abac2b..bc03379 100644
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -29,8 +29,6 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 #define CACHE_LINE_SIZE	128
 
 #ifdef CONFIG_RCU_HAVE_FENCE
@@ -47,68 +45,16 @@ extern "C" {
 #define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_RCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void rep_nop(void)
-{
-	asm volatile("rep; nop" : : : "memory");
-}
-
-static inline void cpu_relax(void)
-{
-	rep_nop();
-}
+#define cpu_relax()	asm volatile("rep; nop" : : : "memory");
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-#ifdef __PIC__
-/*
- * Cannot use cpuid because it clobbers the ebx register and clashes
- * with -fPIC :
+ * Cannot use cpuid on PIC because it clobbers the ebx register;
  * error: PIC register 'ebx' clobbered in 'asm'
  */
-static inline void sync_core(void)
-{
-	mb();
-}
-#else
-static inline void sync_core(void)
-{
+#ifndef __PIC__
+#define sync_core()							  \
 	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-}
 #endif
 
 #define rdtscll(val)							  \
@@ -133,4 +79,6 @@ static inline cycles_t get_cycles(void)
 }
 #endif
 
+#include <urcu/arch_defaults.h>
+
 #endif /* _URCU_ARCH_X86_H */
-- 
1.6.6

[ltt-dev] [PATCH 03/11] add urcu/arch_defaults.h

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> Most of the memory barrier definitions are shared between all
> architectures, especially smp_* and mc/rmc/wmc.  Put them in
> a common file.
> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
> ---
>  urcu/arch_defaults.h |  109 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  urcu/arch_ppc.h      |   50 +---------------------
>  urcu/arch_s390.h     |   38 +----------------
>  urcu/arch_sparc64.h  |   51 +----------------------
>  urcu/arch_x86.h      |   64 +++--------------------------
>  5 files changed, 122 insertions(+), 190 deletions(-)
>  create mode 100644 urcu/arch_defaults.h
> 
> diff --git a/urcu/arch_defaults.h b/urcu/arch_defaults.h
> new file mode 100644
> index 0000000..0cc659e
> --- /dev/null
> +++ b/urcu/arch_defaults.h
> @@ -0,0 +1,121 @@
> +#ifndef _URCU_ARCH_DEFAULTS_H
> +#define _URCU_ARCH_DEFAULTS_H
> +
> +/*
> + * arch_defaults.h: common definitions for multiple architectures.
> + *
> + * Copyright (c) 2010 Paolo Bonzini <pbonzini at redhat.com>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> +*
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <urcu/compiler.h>
> +#include <urcu/config.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#ifndef CACHE_LINE_SIZE
> +#define CACHE_LINE_SIZE	64
> +#endif
> +
> +#if !defined mc && !defined rmc && !defined wmc

+#if !defined(mc) && !defined(rmc) && !defined(wmc)

instead ?

> +#define CONFIG_HAVE_MEM_COHERENCY
> +
> +#ifndef mb
> +#define mb()    __sync_synchronize()
> +#endif
> +
> +#ifndef rmb
> +#define rmb()    mb()
> +#endif
> +
> +#ifndef wmb
> +#define wmb()    mb()
> +#endif
> +
> +#define mc()	 barrier()
> +#define rmc()	 barrier()
> +#define wmc()	 barrier()
> +#else
> +/*
> + * Architectures without cache coherency need something like the following:
> + *
> + * #define mb()	mc()
> + * #define rmb()	rmc()
> + * #define wmb()	wmc()
> + * #define mc()	arch_cache_flush()        // mandatory

The // comment style should be avoided. (Following Linux kernel
guide-lines)

The rest of this patch looks good.

Thanks,

Mathieu

> + * #define rmc()	arch_cache_flush_read()
> + * #define wmc()	arch_cache_flush_write()
> + */
> +
> +#ifndef mb
> +#define mb()    mc()
> +#endif
> +
> +#ifndef rmb
> +#define rmb()    rmc()
> +#endif
> +
> +#ifndef wmb
> +#define wmb()    wmc()
> +#endif
> +
> +#ifndef rmc
> +#define rmc()    mc()
> +#endif
> +
> +#ifndef wmc
> +#define wmc()    mc()
> +#endif
> +#endif
> +
> +/* Nop everywhere except on alpha. */
> +#ifndef read_barrier_depends
> +#define read_barrier_depends()
> +#endif
> +
> +#ifdef CONFIG_RCU_SMP
> +#define smp_mb()	mb()
> +#define smp_rmb()	rmb()
> +#define smp_wmb()	wmb()
> +#define smp_mc()	mc()
> +#define smp_rmc()	rmc()
> +#define smp_wmc()	wmc()
> +#define smp_read_barrier_depends()	read_barrier_depends()
> +#else
> +#define smp_mb()	barrier()
> +#define smp_rmb()	barrier()
> +#define smp_wmb()	barrier()
> +#define smp_mc()	barrier()
> +#define smp_rmc()	barrier()
> +#define smp_wmc()	barrier()
> +#define smp_read_barrier_depends()
> +#endif
> +
> +#ifndef cpu_relax
> +#define cpu_relax()	 barrier()
> +#endif
> +
> +#ifndef sync_core
> +#define sync_core()	 mb()
> +#endif
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* _URCU_ARCH_DEFAULTS_H */
> diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h
> index c1762ae..f925d07 100644
> --- a/urcu/arch_ppc.h
> +++ b/urcu/arch_ppc.h
> @@ -29,8 +29,6 @@
>  extern "C" {
>  #endif 
>  
> -#define CONFIG_HAVE_MEM_COHERENCY
> -
>  /* Include size of POWER5+ L3 cache lines: 256 bytes */
>  #define CACHE_LINE_SIZE	256
>  
> @@ -39,55 +37,11 @@ extern "C" {
>  #endif
>  
>  #define mb()    asm volatile("sync":::"memory")
> -#define rmb()   asm volatile("sync":::"memory")
> -#define wmb()   asm volatile("sync"::: "memory")
> -
> -/*
> - * Architectures without cache coherency need something like the following:
> - *
> - * #define mb()		mc()
> - * #define rmb()	rmc()
> - * #define wmb()	wmc()
> - * #define mc()		arch_cache_flush()
> - * #define rmc()	arch_cache_flush_read()
> - * #define wmc()	arch_cache_flush_write()
> - */
> -
> -#define mc()	barrier()
> -#define rmc()	barrier()
> -#define wmc()	barrier()
> -
> -#ifdef CONFIG_RCU_SMP
> -#define smp_mb()	mb()
> -#define smp_rmb()	rmb()
> -#define smp_wmb()	wmb()
> -#define smp_mc()	mc()
> -#define smp_rmc()	rmc()
> -#define smp_wmc()	wmc()
> -#else
> -#define smp_mb()	barrier()
> -#define smp_rmb()	barrier()
> -#define smp_wmb()	barrier()
> -#define smp_mc()	barrier()
> -#define smp_rmc()	barrier()
> -#define smp_wmc()	barrier()
> -#endif
> -
> -/* Nop everywhere except on alpha. */
> -#define smp_read_barrier_depends()
> -
> -static inline void cpu_relax(void)
> -{
> -	barrier();
> -}
>  
>  /*
>   * Serialize core instruction execution. Also acts as a compiler barrier.
>   */
> -static inline void sync_core()
> -{
> -	asm volatile("isync" : : : "memory");
> -}
> +#define sync_core()	asm volatile("isync" : : : "memory")
>  
>  #define mftbl()						\
>  	({ 						\
> @@ -123,4 +77,6 @@ static inline cycles_t get_cycles (void)
>  }
>  #endif
>  
> +#include <urcu/arch_defaults.h>
> +
>  #endif /* _URCU_ARCH_PPC_H */
> diff --git a/urcu/arch_s390.h b/urcu/arch_s390.h
> index 22a1853..0982112 100644
> --- a/urcu/arch_s390.h
> +++ b/urcu/arch_s390.h
> @@ -35,8 +35,6 @@
>  extern "C" {
>  #endif 
>  
> -#define CONFIG_HAVE_MEM_COHERENCY
> -
>  #define CACHE_LINE_SIZE	128
>  
>  #ifndef __SIZEOF_LONG__
> @@ -52,40 +50,6 @@ extern "C" {
>  #endif
>  
>  #define mb()    __asm__ __volatile__("bcr 15,0" : : : "memory")
> -#define rmb()   __asm__ __volatile__("bcr 15,0" : : : "memory")
> -#define wmb()   __asm__ __volatile__("bcr 15,0" : : : "memory")
> -#define mc()	barrier()
> -#define rmc()	barrier()
> -#define wmc()	barrier()
> -
> -#ifdef CONFIG_RCU_SMP
> -#define smp_mb()	mb()
> -#define smp_rmb()	rmb()
> -#define smp_wmb()	wmb()
> -#define smp_mc()	mc()
> -#define smp_rmc()	rmc()
> -#define smp_wmc()	wmc()
> -#else
> -#define smp_mb()	barrier()
> -#define smp_rmb()	barrier()
> -#define smp_wmb()	barrier()
> -#define smp_mc()	barrier()
> -#define smp_rmc()	barrier()
> -#define smp_wmc()	barrier()
> -#endif
> -
> -/* Nop everywhere except on alpha. */
> -#define smp_read_barrier_depends()
> -
> -static inline void cpu_relax(void)
> -{
> -	barrier();
> -}
> -
> -static inline void sync_core()
> -{
> -	__asm__ __volatile__("bcr 15,0" : : : "memory");
> -}
>  
>  typedef unsigned long long cycles_t;
>  
> @@ -102,4 +66,6 @@ static inline cycles_t get_cycles (void)
>  }
>  #endif
>  
> +#include <urcu/arch_defaults.h>
> +
>  #endif /* _URCU_ARCH_S390_H */
> diff --git a/urcu/arch_sparc64.h b/urcu/arch_sparc64.h
> index 54c4c3c..c906168 100644
> --- a/urcu/arch_sparc64.h
> +++ b/urcu/arch_sparc64.h
> @@ -29,8 +29,6 @@
>  extern "C" {
>  #endif 
>  
> -#define CONFIG_HAVE_MEM_COHERENCY
> -
>  #define CACHE_LINE_SIZE	256
>  
>  #ifndef BITS_PER_LONG
> @@ -50,53 +48,6 @@ __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"	\
>  #define rmb()    membar_safe("#LoadLoad")
>  #define wmb()    membar_safe("#StoreStore")
>  
> -/*
> - * Architectures without cache coherency need something like the following:
> - *
> - * #define mb()		mc()
> - * #define rmb()	rmc()
> - * #define wmb()	wmc()
> - * #define mc()		arch_cache_flush()
> - * #define rmc()	arch_cache_flush_read()
> - * #define wmc()	arch_cache_flush_write()
> - */
> -
> -#define mc()	barrier()
> -#define rmc()	barrier()
> -#define wmc()	barrier()
> -
> -#ifdef CONFIG_RCU_SMP
> -#define smp_mb()	mb()
> -#define smp_rmb()	rmb()
> -#define smp_wmb()	wmb()
> -#define smp_mc()	mc()
> -#define smp_rmc()	rmc()
> -#define smp_wmc()	wmc()
> -#else
> -#define smp_mb()	barrier()
> -#define smp_rmb()	barrier()
> -#define smp_wmb()	barrier()
> -#define smp_mc()	barrier()
> -#define smp_rmc()	barrier()
> -#define smp_wmc()	barrier()
> -#endif
> -
> -/* Nop everywhere except on alpha. */
> -#define smp_read_barrier_depends()
> -
> -static inline void cpu_relax(void)
> -{
> -	barrier();
> -}
> -
> -/*
> - * Serialize core instruction execution. Also acts as a compiler barrier.
> - */
> -static inline void sync_core()
> -{
> -	mb();
> -}
> -
>  typedef unsigned long long cycles_t;
>  
>  static inline cycles_t get_cycles (void)
> @@ -108,4 +59,6 @@ static inline cycles_t get_cycles (void)
>  }
>  #endif
>  
> +#include <urcu/arch_defaults.h>
> +
>  #endif /* _URCU_ARCH_SPARC64_H */
> diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
> index 4abac2b..bc03379 100644
> --- a/urcu/arch_x86.h
> +++ b/urcu/arch_x86.h
> @@ -29,8 +29,6 @@
>  extern "C" {
>  #endif 
>  
> -#define CONFIG_HAVE_MEM_COHERENCY
> -
>  #define CACHE_LINE_SIZE	128
>  
>  #ifdef CONFIG_RCU_HAVE_FENCE
> @@ -47,68 +45,16 @@ extern "C" {
>  #define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
>  #endif
>  
> -/*
> - * Architectures without cache coherency need something like the following:
> - *
> - * #define mb()		mc()
> - * #define rmb()	rmc()
> - * #define wmb()	wmc()
> - * #define mc()		arch_cache_flush()
> - * #define rmc()	arch_cache_flush_read()
> - * #define wmc()	arch_cache_flush_write()
> - */
> -
> -#define mc()	barrier()
> -#define rmc()	barrier()
> -#define wmc()	barrier()
> -
> -#ifdef CONFIG_RCU_SMP
> -#define smp_mb()	mb()
> -#define smp_rmb()	rmb()
> -#define smp_wmb()	wmb()
> -#define smp_mc()	mc()
> -#define smp_rmc()	rmc()
> -#define smp_wmc()	wmc()
> -#else
> -#define smp_mb()	barrier()
> -#define smp_rmb()	barrier()
> -#define smp_wmb()	barrier()
> -#define smp_mc()	barrier()
> -#define smp_rmc()	barrier()
> -#define smp_wmc()	barrier()
> -#endif
> -
> -/* Nop everywhere except on alpha. */
> -#define smp_read_barrier_depends()
> -
> -static inline void rep_nop(void)
> -{
> -	asm volatile("rep; nop" : : : "memory");
> -}
> -
> -static inline void cpu_relax(void)
> -{
> -	rep_nop();
> -}
> +#define cpu_relax()	asm volatile("rep; nop" : : : "memory");
>  
>  /*
>   * Serialize core instruction execution. Also acts as a compiler barrier.
> - */
> -#ifdef __PIC__
> -/*
> - * Cannot use cpuid because it clobbers the ebx register and clashes
> - * with -fPIC :
> + * Cannot use cpuid on PIC because it clobbers the ebx register;
>   * error: PIC register 'ebx' clobbered in 'asm'
>   */
> -static inline void sync_core(void)
> -{
> -	mb();
> -}
> -#else
> -static inline void sync_core(void)
> -{
> +#ifndef __PIC__
> +#define sync_core()							  \
>  	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
> -}
>  #endif
>  
>  #define rdtscll(val)							  \
> @@ -133,4 +79,6 @@ static inline cycles_t get_cycles(void)
>  }
>  #endif
>  
> +#include <urcu/arch_defaults.h>
> +
>  #endif /* _URCU_ARCH_X86_H */
> -- 
> 1.6.6
> 
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 03/11] add urcu/arch_defaults.h

[Paolo Bonzini]

On 02/14/2010 03:34 PM, Mathieu Desnoyers wrote:
> +#if !defined(mc)&&  !defined(rmc)&&  !defined(wmc)
>
> instead ?

Ok.

>> >  +/*
>> >  + * Architectures without cache coherency need something like the following:
>> >  + *
>> >  + * #define mb()	mc()
>> >  + * #define rmb()	rmc()
>> >  + * #define wmb()	wmc()
>> >  + * #define mc()	arch_cache_flush()        // mandatory
>
> The // comment style should be avoided. (Following Linux kernel
> guide-lines)

Note that this is within a comment; I used it reluctantly because C 
comments do not nest.  I could replace it with "<-- mandatory" but I 
think // is better in this case.

Paolo

[ltt-dev] [PATCH 03/11] add urcu/arch_defaults.h

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> On 02/14/2010 03:34 PM, Mathieu Desnoyers wrote:
>> +#if !defined(mc)&&  !defined(rmc)&&  !defined(wmc)
>>
>> instead ?
>
> Ok.
>
>>> >  +/*
>>> >  + * Architectures without cache coherency need something like the following:
>>> >  + *
>>> >  + * #define mb()	mc()
>>> >  + * #define rmb()	rmc()
>>> >  + * #define wmb()	wmc()
>>> >  + * #define mc()	arch_cache_flush()        // mandatory
>>
>> The // comment style should be avoided. (Following Linux kernel
>> guide-lines)
>
> Note that this is within a comment; I used it reluctantly because C  
> comments do not nest.  I could replace it with "<-- mandatory" but I  
> think // is better in this case.

I'm not quite sure what this "mandatory" comment implies. I think
expressing it more verbosely in a sentence above the defines would be
better.

Thanks,

Mathieu

>
> Paolo
>

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 04/11] define sync_core for x86 PIC

[Paolo Bonzini]

Pushing/popping the reserved ebx register is surely less expensive
than a memory barrier.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/arch_x86.h |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index bc03379..07f2ac8 100644
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -49,9 +49,13 @@ extern "C" {
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
- * Cannot use cpuid on PIC because it clobbers the ebx register;
- * error: PIC register 'ebx' clobbered in 'asm'
+ * On PIC ebx cannot be clobbered
  */
+#ifdef __PIC__
+#define sync_core()							  \
+	asm volatile("push %%ebx; cpuid; pop %%ebx"			  \
+		     : : : "memory", "eax", "ecx", "edx");
+#endif
 #ifndef __PIC__
 #define sync_core()							  \
 	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-- 
1.6.6

[ltt-dev] [PATCH 04/11] define sync_core for x86 PIC

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> Pushing/popping the reserved ebx register is surely less expensive
> than a memory barrier.

Please add a note saying that it also works in the presence of signal
handlers, because we are not using the ebx value returned by cpuid.

It would not be correct to use this with signals enabled if we cared
about the ebx value returned by cpuid.

Thanks,

Mathieu

> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
> ---
>  urcu/arch_x86.h |    8 ++++++--
>  1 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
> index bc03379..07f2ac8 100644
> --- a/urcu/arch_x86.h
> +++ b/urcu/arch_x86.h
> @@ -49,9 +49,13 @@ extern "C" {
>  
>  /*
>   * Serialize core instruction execution. Also acts as a compiler barrier.
> - * Cannot use cpuid on PIC because it clobbers the ebx register;
> - * error: PIC register 'ebx' clobbered in 'asm'
> + * On PIC ebx cannot be clobbered
>   */
> +#ifdef __PIC__
> +#define sync_core()							  \
> +	asm volatile("push %%ebx; cpuid; pop %%ebx"			  \
> +		     : : : "memory", "eax", "ecx", "edx");
> +#endif
>  #ifndef __PIC__
>  #define sync_core()							  \
>  	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
> -- 
> 1.6.6
> 
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 04/11] define sync_core for x86 PIC

[Paolo Bonzini]

On 02/14/2010 03:37 PM, Mathieu Desnoyers wrote:
> Please add a note saying that it also works in the presence of signal
> handlers, because we are not using the ebx value returned by cpuid.
>
> It would not be correct to use this with signals enabled if we cared
> about the ebx value returned by cpuid.

It would, because %ebx is callee-save and the signal handler would have 
to reinitialize it (since each shared library for example has its own 
GOT, it doesn't know if the caller had the same GOT).  In general, 
functions that are not static or hidden, or that have their address 
taken need to rebuild the GOT pointer.  Signal handlers fall obviously 
in the latter category.

Paolo

[ltt-dev] [PATCH 04/11] define sync_core for x86 PIC

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> On 02/14/2010 03:37 PM, Mathieu Desnoyers wrote:
>> Please add a note saying that it also works in the presence of signal
>> handlers, because we are not using the ebx value returned by cpuid.
>>
>> It would not be correct to use this with signals enabled if we cared
>> about the ebx value returned by cpuid.
>
> It would, because %ebx is callee-save and the signal handler would have  
> to reinitialize it (since each shared library for example has its own  
> GOT, it doesn't know if the caller had the same GOT).  In general,  
> functions that are not static or hidden, or that have their address  
> taken need to rebuild the GOT pointer.  Signal handlers fall obviously  
> in the latter category.

OK, that makes perfect sense. Thanks for the explanation. It could be
good to add a few words explaining this in your patch.

Mathieu

>
> Paolo
>

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 05/11] __SIZEOF_LONG__ is always defined by GCC

[Paolo Bonzini]

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/arch_s390.h            |    8 --------
 urcu/uatomic_arch_ppc.h     |    8 --------
 urcu/uatomic_arch_s390.h    |    8 --------
 urcu/uatomic_arch_sparc64.h |    8 --------
 urcu/uatomic_arch_x86.h     |    8 --------
 5 files changed, 0 insertions(+), 40 deletions(-)

diff --git a/urcu/arch_s390.h b/urcu/arch_s390.h
index 0982112..2171ffa 100644
--- a/urcu/arch_s390.h
+++ b/urcu/arch_s390.h
@@ -37,14 +37,6 @@ extern "C" {
 
 #define CACHE_LINE_SIZE	128
 
-#ifndef __SIZEOF_LONG__
-#ifdef __s390x__
-#define __SIZEOF_LONG__ 8
-#else
-#define __SIZEOF_LONG__ 4
-#endif
-#endif
-
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
 #endif
diff --git a/urcu/uatomic_arch_ppc.h b/urcu/uatomic_arch_ppc.h
index 2322c97..e0a06b8 100644
--- a/urcu/uatomic_arch_ppc.h
+++ b/urcu/uatomic_arch_ppc.h
@@ -27,14 +27,6 @@
 extern "C" {
 #endif 
 
-#ifndef __SIZEOF_LONG__
-#ifdef __powerpc64__
-#define __SIZEOF_LONG__ 8
-#else
-#define __SIZEOF_LONG__ 4
-#endif
-#endif
-
 #ifdef __NO_LWSYNC__
 #define LWSYNC_OPCODE	"sync\n"
 #else
diff --git a/urcu/uatomic_arch_s390.h b/urcu/uatomic_arch_s390.h
index fdfabfd..ee88795 100644
--- a/urcu/uatomic_arch_s390.h
+++ b/urcu/uatomic_arch_s390.h
@@ -36,14 +36,6 @@
 extern "C" {
 #endif 
 
-#ifndef __SIZEOF_LONG__
-#ifdef __s390x__
-#define __SIZEOF_LONG__ 8
-#else
-#define __SIZEOF_LONG__ 4
-#endif
-#endif
-
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
 #endif
diff --git a/urcu/uatomic_arch_sparc64.h b/urcu/uatomic_arch_sparc64.h
index 3aa3b7d..6978490 100644
--- a/urcu/uatomic_arch_sparc64.h
+++ b/urcu/uatomic_arch_sparc64.h
@@ -27,14 +27,6 @@
 extern "C" {
 #endif 
 
-#ifndef __SIZEOF_LONG__
-#ifdef __LP64__
-#define __SIZEOF_LONG__ 8
-#else
-#define __SIZEOF_LONG__ 4
-#endif
-#endif
-
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
 #endif
diff --git a/urcu/uatomic_arch_x86.h b/urcu/uatomic_arch_x86.h
index 3bfe86d..34f5f87 100644
--- a/urcu/uatomic_arch_x86.h
+++ b/urcu/uatomic_arch_x86.h
@@ -27,14 +27,6 @@
 extern "C" {
 #endif 
 
-#ifndef __SIZEOF_LONG__
-#if defined(__x86_64__) || defined(__amd64__)
-#define __SIZEOF_LONG__ 8
-#else
-#define __SIZEOF_LONG__ 4
-#endif
-#endif
-
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
 #endif
-- 
1.6.6

[ltt-dev] [PATCH 05/11] __SIZEOF_LONG__ is always defined by GCC

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> 

Which gcc versions have you tested on ?

Mathieu

> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
> ---
>  urcu/arch_s390.h            |    8 --------
>  urcu/uatomic_arch_ppc.h     |    8 --------
>  urcu/uatomic_arch_s390.h    |    8 --------
>  urcu/uatomic_arch_sparc64.h |    8 --------
>  urcu/uatomic_arch_x86.h     |    8 --------
>  5 files changed, 0 insertions(+), 40 deletions(-)
> 
> diff --git a/urcu/arch_s390.h b/urcu/arch_s390.h
> index 0982112..2171ffa 100644
> --- a/urcu/arch_s390.h
> +++ b/urcu/arch_s390.h
> @@ -37,14 +37,6 @@ extern "C" {
>  
>  #define CACHE_LINE_SIZE	128
>  
> -#ifndef __SIZEOF_LONG__
> -#ifdef __s390x__
> -#define __SIZEOF_LONG__ 8
> -#else
> -#define __SIZEOF_LONG__ 4
> -#endif
> -#endif
> -
>  #ifndef BITS_PER_LONG
>  #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
>  #endif
> diff --git a/urcu/uatomic_arch_ppc.h b/urcu/uatomic_arch_ppc.h
> index 2322c97..e0a06b8 100644
> --- a/urcu/uatomic_arch_ppc.h
> +++ b/urcu/uatomic_arch_ppc.h
> @@ -27,14 +27,6 @@
>  extern "C" {
>  #endif 
>  
> -#ifndef __SIZEOF_LONG__
> -#ifdef __powerpc64__
> -#define __SIZEOF_LONG__ 8
> -#else
> -#define __SIZEOF_LONG__ 4
> -#endif
> -#endif
> -
>  #ifdef __NO_LWSYNC__
>  #define LWSYNC_OPCODE	"sync\n"
>  #else
> diff --git a/urcu/uatomic_arch_s390.h b/urcu/uatomic_arch_s390.h
> index fdfabfd..ee88795 100644
> --- a/urcu/uatomic_arch_s390.h
> +++ b/urcu/uatomic_arch_s390.h
> @@ -36,14 +36,6 @@
>  extern "C" {
>  #endif 
>  
> -#ifndef __SIZEOF_LONG__
> -#ifdef __s390x__
> -#define __SIZEOF_LONG__ 8
> -#else
> -#define __SIZEOF_LONG__ 4
> -#endif
> -#endif
> -
>  #ifndef BITS_PER_LONG
>  #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
>  #endif
> diff --git a/urcu/uatomic_arch_sparc64.h b/urcu/uatomic_arch_sparc64.h
> index 3aa3b7d..6978490 100644
> --- a/urcu/uatomic_arch_sparc64.h
> +++ b/urcu/uatomic_arch_sparc64.h
> @@ -27,14 +27,6 @@
>  extern "C" {
>  #endif 
>  
> -#ifndef __SIZEOF_LONG__
> -#ifdef __LP64__
> -#define __SIZEOF_LONG__ 8
> -#else
> -#define __SIZEOF_LONG__ 4
> -#endif
> -#endif
> -
>  #ifndef BITS_PER_LONG
>  #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
>  #endif
> diff --git a/urcu/uatomic_arch_x86.h b/urcu/uatomic_arch_x86.h
> index 3bfe86d..34f5f87 100644
> --- a/urcu/uatomic_arch_x86.h
> +++ b/urcu/uatomic_arch_x86.h
> @@ -27,14 +27,6 @@
>  extern "C" {
>  #endif 
>  
> -#ifndef __SIZEOF_LONG__
> -#if defined(__x86_64__) || defined(__amd64__)
> -#define __SIZEOF_LONG__ 8
> -#else
> -#define __SIZEOF_LONG__ 4
> -#endif
> -#endif
> -
>  #ifndef BITS_PER_LONG
>  #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
>  #endif
> -- 
> 1.6.6
> 
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 05/11] __SIZEOF_LONG__ is always defined by GCC

[Paolo Bonzini]

On 02/14/2010 03:38 PM, Mathieu Desnoyers wrote:
> * Paolo Bonzini (pbonzini at redhat.com) wrote:
>>
>
> Which gcc versions have you tested on ?

Nevermind, I thought it was much older but it went in first for 4.3. 
I'll change this patch to use _LP64 which is present in 3.4.

Paolo

[ltt-dev] [PATCH 06/11] remove compat_uatomic_cmpxchg #define from non-x86

[Paolo Bonzini]

This is unused everywhere except on x86.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/uatomic_arch_ppc.h     |    2 --
 urcu/uatomic_arch_s390.h    |    2 --
 urcu/uatomic_arch_sparc64.h |    2 --
 3 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/urcu/uatomic_arch_ppc.h b/urcu/uatomic_arch_ppc.h
index e0a06b8..7106b99 100644
--- a/urcu/uatomic_arch_ppc.h
+++ b/urcu/uatomic_arch_ppc.h
@@ -227,8 +227,6 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val,
 #define uatomic_inc(addr)		uatomic_add((addr), 1)
 #define uatomic_dec(addr)		uatomic_add((addr), -1)
 
-#define compat_uatomic_cmpxchg(ptr, old, _new)	uatomic_cmpxchg(ptr, old, _new)
-
 #ifdef __cplusplus 
 }
 #endif
diff --git a/urcu/uatomic_arch_s390.h b/urcu/uatomic_arch_s390.h
index ee88795..6247601 100644
--- a/urcu/uatomic_arch_s390.h
+++ b/urcu/uatomic_arch_s390.h
@@ -210,8 +210,6 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
 #define uatomic_inc(addr)		uatomic_add((addr), 1)
 #define uatomic_dec(addr)		uatomic_add((addr), -1)
 
-#define compat_uatomic_cmpxchg(ptr, old, _new)	uatomic_cmpxchg(ptr, old, _new)
-
 #ifdef __cplusplus 
 }
 #endif
diff --git a/urcu/uatomic_arch_sparc64.h b/urcu/uatomic_arch_sparc64.h
index 6978490..e984986 100644
--- a/urcu/uatomic_arch_sparc64.h
+++ b/urcu/uatomic_arch_sparc64.h
@@ -171,8 +171,6 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
 #define uatomic_inc(addr)		uatomic_add((addr), 1)
 #define uatomic_dec(addr)		uatomic_add((addr), -1)
 
-#define compat_uatomic_cmpxchg(ptr, old, _new)	uatomic_cmpxchg(ptr, old, _new)
-
 #ifdef __cplusplus 
 }
 #endif
-- 
1.6.6

[ltt-dev] [PATCH 06/11] remove compat_uatomic_cmpxchg #define from non-x86

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> This is unused everywhere except on x86.

Acked-by: Mathieu Desnoyers <mathieu.desnoyers at efficios.com>

> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
> ---
>  urcu/uatomic_arch_ppc.h     |    2 --
>  urcu/uatomic_arch_s390.h    |    2 --
>  urcu/uatomic_arch_sparc64.h |    2 --
>  3 files changed, 0 insertions(+), 6 deletions(-)
> 
> diff --git a/urcu/uatomic_arch_ppc.h b/urcu/uatomic_arch_ppc.h
> index e0a06b8..7106b99 100644
> --- a/urcu/uatomic_arch_ppc.h
> +++ b/urcu/uatomic_arch_ppc.h
> @@ -227,8 +227,6 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val,
>  #define uatomic_inc(addr)		uatomic_add((addr), 1)
>  #define uatomic_dec(addr)		uatomic_add((addr), -1)
>  
> -#define compat_uatomic_cmpxchg(ptr, old, _new)	uatomic_cmpxchg(ptr, old, _new)
> -
>  #ifdef __cplusplus 
>  }
>  #endif
> diff --git a/urcu/uatomic_arch_s390.h b/urcu/uatomic_arch_s390.h
> index ee88795..6247601 100644
> --- a/urcu/uatomic_arch_s390.h
> +++ b/urcu/uatomic_arch_s390.h
> @@ -210,8 +210,6 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
>  #define uatomic_inc(addr)		uatomic_add((addr), 1)
>  #define uatomic_dec(addr)		uatomic_add((addr), -1)
>  
> -#define compat_uatomic_cmpxchg(ptr, old, _new)	uatomic_cmpxchg(ptr, old, _new)
> -
>  #ifdef __cplusplus 
>  }
>  #endif
> diff --git a/urcu/uatomic_arch_sparc64.h b/urcu/uatomic_arch_sparc64.h
> index 6978490..e984986 100644
> --- a/urcu/uatomic_arch_sparc64.h
> +++ b/urcu/uatomic_arch_sparc64.h
> @@ -171,8 +171,6 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
>  #define uatomic_inc(addr)		uatomic_add((addr), 1)
>  #define uatomic_dec(addr)		uatomic_add((addr), -1)
>  
> -#define compat_uatomic_cmpxchg(ptr, old, _new)	uatomic_cmpxchg(ptr, old, _new)
> -
>  #ifdef __cplusplus 
>  }
>  #endif
> -- 
> 1.6.6
> 
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Paolo Bonzini]

From most of the architectures, we can derive the implementation
of xchg and add_return from cmpxchg:

- if cmpxchg is present, use it to implement xchg and add_return;

- if it is not present, implement all three using __sync_* builtins

The hunk in tests/test_uatomic.c is only needed for bisectability
and will be removed later.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 Makefile.am                 |    2 +-
 tests/test_uatomic.c        |    2 +
 urcu/uatomic_arch_ppc.h     |   15 +---
 urcu/uatomic_arch_s390.h    |   15 +---
 urcu/uatomic_arch_sparc64.h |   15 +---
 urcu/uatomic_arch_x86.h     |   26 ++----
 urcu/uatomic_gcc.h          |  221 +++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 239 insertions(+), 57 deletions(-)
 create mode 100644 urcu/uatomic_gcc.h

diff --git a/Makefile.am b/Makefile.am
index 57e9299..d6ee789 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -6,7 +6,7 @@ SUBDIRS = . tests
 
 include_HEADERS = urcu.h $(top_srcdir)/urcu-*.h
 nobase_dist_include_HEADERS = urcu/compiler.h urcu/hlist.h urcu/list.h \
-		urcu/rculist.h urcu/system.h urcu/urcu-futex.h
+		urcu/rculist.h urcu/system.h urcu/urcu-futex.h urcu/uatomic_gcc.h
 nobase_nodist_include_HEADERS = urcu/arch.h urcu/uatomic_arch.h urcu/config.h
 
 EXTRA_DIST = $(top_srcdir)/urcu/arch_*.h $(top_srcdir)/urcu/uatomic_arch_*.h \
diff --git a/tests/test_uatomic.c b/tests/test_uatomic.c
index 68cb6df..c0f36fe 100644
--- a/tests/test_uatomic.c
+++ b/tests/test_uatomic.c
@@ -1,5 +1,7 @@
 #include <stdio.h>
 #include <assert.h>
+
+#define UATOMIC_NO_LINK_ERROR
 #include <urcu/uatomic_arch.h>
 
 #if (defined(__i386__) || defined(__x86_64__))
diff --git a/urcu/uatomic_arch_ppc.h b/urcu/uatomic_arch_ppc.h
index 7106b99..c611c7a 100644
--- a/urcu/uatomic_arch_ppc.h
+++ b/urcu/uatomic_arch_ppc.h
@@ -39,9 +39,6 @@ extern "C" {
 
 #define ILLEGAL_INSTR	".long	0xd00d00"
 
-#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
-#define uatomic_read(addr)	LOAD_SHARED(*(addr))
-
 /*
  * Using a isync as second barrier for exchange to provide acquire semantic.
  * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
@@ -217,18 +214,10 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val,
 						  (unsigned long)(v),	\
 						  sizeof(*(addr))))
 
-/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
-
-#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))
-
-#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
-#define uatomic_sub(addr, v)		(void)uatomic_sub_return((addr), (v))
-
-#define uatomic_inc(addr)		uatomic_add((addr), 1)
-#define uatomic_dec(addr)		uatomic_add((addr), -1)
-
 #ifdef __cplusplus 
 }
 #endif
 
+#include <urcu/uatomic_gcc.h>
+
 #endif /* _URCU_ARCH_UATOMIC_PPC_H */
diff --git a/urcu/uatomic_arch_s390.h b/urcu/uatomic_arch_s390.h
index 6247601..9d4b74e 100644
--- a/urcu/uatomic_arch_s390.h
+++ b/urcu/uatomic_arch_s390.h
@@ -70,9 +70,6 @@ struct __uatomic_dummy {
 };
 #define __hp(x)	((struct __uatomic_dummy *)(x))
 
-#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
-#define uatomic_read(addr)	LOAD_SHARED(*(addr))
-
 /* xchg */
 
 static inline __attribute__((always_inline))
@@ -200,18 +197,10 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
 						  (unsigned long)(v),	\
 						  sizeof(*(addr))))
 
-/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
-
-#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))
-
-#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
-#define uatomic_sub(addr, v)		(void)uatomic_sub_return((addr), (v))
-
-#define uatomic_inc(addr)		uatomic_add((addr), 1)
-#define uatomic_dec(addr)		uatomic_add((addr), -1)
-
 #ifdef __cplusplus 
 }
 #endif
 
+#include <urcu/uatomic_gcc.h>
+
 #endif /* _URCU_UATOMIC_ARCH_S390_H */
diff --git a/urcu/uatomic_arch_sparc64.h b/urcu/uatomic_arch_sparc64.h
index e984986..d21d73c 100644
--- a/urcu/uatomic_arch_sparc64.h
+++ b/urcu/uatomic_arch_sparc64.h
@@ -31,9 +31,6 @@ extern "C" {
 #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
 #endif
 
-#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
-#define uatomic_read(addr)	LOAD_SHARED(*(addr))
-
 /* cmpxchg */
 
 static inline __attribute__((always_inline))
@@ -161,18 +158,10 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
 						  (unsigned long)(v),	\
 						  sizeof(*(addr))))
 
-/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
-
-#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))
-
-#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
-#define uatomic_sub(addr, v)		(void)uatomic_sub_return((addr), (v))
-
-#define uatomic_inc(addr)		uatomic_add((addr), 1)
-#define uatomic_dec(addr)		uatomic_add((addr), -1)
-
 #ifdef __cplusplus 
 }
 #endif
 
+#include <urcu/uatomic_gcc.h>
+
 #endif /* _URCU_ARCH_UATOMIC_PPC_H */
diff --git a/urcu/uatomic_arch_x86.h b/urcu/uatomic_arch_x86.h
index 34f5f87..0aadbd5 100644
--- a/urcu/uatomic_arch_x86.h
+++ b/urcu/uatomic_arch_x86.h
@@ -41,7 +41,11 @@ struct __uatomic_dummy {
 #define __hp(x)	((struct __uatomic_dummy *)(x))
 
 #define _uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
+
+#if 0
+/* Read is atomic even in compat mode */
 #define _uatomic_read(addr)	LOAD_SHARED(*(addr))
+#endif
 
 /* cmpxchg */
 
@@ -168,7 +172,7 @@ unsigned long __uatomic_exchange(void *addr, unsigned long val, int len)
 	((__typeof__(*(addr))) __uatomic_exchange((addr), (unsigned long)(v), \
 						sizeof(*(addr))))
 
-/* uatomic_add_return, uatomic_sub_return */
+/* uatomic_add_return */
 
 static inline __attribute__((always_inline))
 unsigned long __uatomic_add_return(void *addr, unsigned long val,
@@ -233,9 +237,7 @@ unsigned long __uatomic_add_return(void *addr, unsigned long val,
 						  (unsigned long)(v),	\
 						  sizeof(*(addr))))
 
-#define _uatomic_sub_return(addr, v)	_uatomic_add_return((addr), -(v))
-
-/* uatomic_add, uatomic_sub */
+/* uatomic_add */
 
 static inline __attribute__((always_inline))
 void __uatomic_add(void *addr, unsigned long val, int len)
@@ -289,8 +291,6 @@ void __uatomic_add(void *addr, unsigned long val, int len)
 #define _uatomic_add(addr, v)						   \
 	(__uatomic_add((addr), (unsigned long)(v), sizeof(*(addr))))
 
-#define _uatomic_sub(addr, v)	_uatomic_add((addr), -(v))
-
 
 /* uatomic_inc */
 
@@ -441,24 +441,17 @@ extern unsigned long _compat_uatomic_xchg(void *addr,
 						(unsigned long)(v), 	       \
 						sizeof(*(addr))))
 
-#define compat_uatomic_sub_return(addr, v)				       \
-		compat_uatomic_add_return((addr), -(v))
 #define compat_uatomic_add(addr, v)					       \
 		((void)compat_uatomic_add_return((addr), (v)))
-#define compat_uatomic_sub(addr, v)					       \
-		((void)compat_uatomic_sub_return((addr), (v)))
 #define compat_uatomic_inc(addr)					       \
 		(compat_uatomic_add((addr), 1))
 #define compat_uatomic_dec(addr)					       \
-		(compat_uatomic_sub((addr), 1))
+		(compat_uatomic_add((addr), -1))
 
 #else
 #define UATOMIC_COMPAT(insn)	(_uatomic_##insn)
 #endif
 
-/* Read is atomic even in compat mode */
-#define uatomic_read(addr)	_uatomic_read(addr)
-
 #define uatomic_set(addr, v)			\
 		UATOMIC_COMPAT(set(addr, v))
 #define uatomic_cmpxchg(addr, old, _new)	\
@@ -467,10 +460,7 @@ extern unsigned long _compat_uatomic_xchg(void *addr,
 		UATOMIC_COMPAT(xchg(addr, v))
 #define uatomic_add_return(addr, v)		\
 		UATOMIC_COMPAT(add_return(addr, v))
-#define uatomic_sub_return(addr, v)		\
-		UATOMIC_COMPAT(sub_return(addr, v))
 #define uatomic_add(addr, v)	UATOMIC_COMPAT(add(addr, v))
-#define uatomic_sub(addr, v)	UATOMIC_COMPAT(sub(addr, v))
 #define uatomic_inc(addr)	UATOMIC_COMPAT(inc(addr))
 #define uatomic_dec(addr)	UATOMIC_COMPAT(dec(addr))
 
@@ -478,4 +468,6 @@ extern unsigned long _compat_uatomic_xchg(void *addr,
 }
 #endif
 
+#include <urcu/uatomic_gcc.h>
+
 #endif /* _URCU_ARCH_UATOMIC_X86_H */
diff --git a/urcu/uatomic_gcc.h b/urcu/uatomic_gcc.h
new file mode 100644
index 0000000..28f6d71
--- /dev/null
+++ b/urcu/uatomic_gcc.h
@@ -0,0 +1,223 @@
+#ifndef _URCU_UATOMIC_GCC_H
+#define _URCU_UATOMIC_GCC_H
+
+/*
+ * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
+ * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
+ * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2009      Mathieu Desnoyers
+ * Copyright (c) 2010      Paolo Bonzini
+ *
+ * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
+ * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
+ *
+ * Permission is hereby granted to use or copy this program
+ * for any purpose,  provided the above notices are retained on all copies.
+ * Permission to modify the code and to distribute modified code is granted,
+ * provided the above notices are retained, and a notice that the code was
+ * modified is included with the above copyright notice.
+ *
+ * Code inspired from libuatomic_ops-1.2, inherited in part from the
+ * Boehm-Demers-Weiser conservative garbage collector.
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef BITS_PER_LONG
+#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
+#endif
+
+#ifndef uatomic_set
+#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
+#endif
+
+#ifndef uatomic_read
+#define uatomic_read(addr)	LOAD_SHARED(*(addr))
+#endif
+
+#if !defined __OPTIMIZE__  || defined UATOMIC_NO_LINK_ERROR
+static inline __attribute__((always_inline))
+void _uatomic_link_error()
+{
+#ifdef ILLEGAL_INSTR
+	/* generate an illegal instruction. Cannot catch this with linker tricks
+	 * when optimizations are disabled. */
+	__asm__ __volatile__(ILLEGAL_INSTR);
+#else
+	__builtin_trap ();
+#endif
+}
+#else
+extern void _uatomic_link_error ();
+#endif
+
+/* cmpxchg */
+
+#ifndef uatomic_cmpxchg
+static inline __attribute__((always_inline))
+unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
+			      unsigned long _new, int len)
+{
+	switch (len) {
+	case 4:
+		return __sync_val_compare_and_swap_4(addr, old, _new);
+#if (BITS_PER_LONG == 64)
+	case 8:
+		return __sync_val_compare_and_swap_8(addr, old, _new);
+#endif
+	}
+	_uatomic_link_error();
+	return 0;
+}
+
+
+#define uatomic_cmpxchg(addr, old, _new)				    \
+	((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
+						(unsigned long)(_new), 	    \
+						sizeof(*(addr))))
+
+
+/* uatomic_add_return */
+
+#ifndef uatomic_add_return
+static inline __attribute__((always_inline))
+unsigned long _uatomic_add_return(void *addr, unsigned long val,
+				 int len)
+{
+	switch (len) {
+	case 4:
+		return __sync_add_and_fetch_4(addr, val);
+#if (BITS_PER_LONG == 64)
+	case 8:
+		return __sync_add_and_fetch_8(addr, val);
+#endif
+	}
+	_uatomic_link_error();
+	return 0;
+}
+
+
+#define uatomic_add_return(addr, v)					\
+	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
+						  (unsigned long)(v),	\
+						  sizeof(*(addr))))
+#endif
+
+#else
+
+#ifndef uatomic_add_return
+/* uatomic_add_return */
+
+static inline __attribute__((always_inline))
+unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
+{
+	switch (len) {
+	case 4:
+	{
+		unsigned int old, oldt;
+
+		oldt = uatomic_read((unsigned int *)addr);
+		do {
+			old = oldt;
+			oldt = _uatomic_cmpxchg(addr, old, old + val, 4);
+		} while (oldt != old);
+
+		return old + val;
+	}
+#if (BITS_PER_LONG == 64)
+	case 8:
+	{
+		unsigned long old, oldt;
+
+		oldt = uatomic_read((unsigned long *)addr);
+		do {
+			old = oldt;
+			oldt = _uatomic_cmpxchg(addr, old, old + val, 8);
+		} while (oldt != old);
+
+		return old + val;
+	}
+#endif
+	}
+	_uatomic_link_error();
+	return 0;
+}
+
+#define uatomic_add_return(addr, v)					\
+	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
+						  (unsigned long)(v),	\
+						  sizeof(*(addr))))
+#endif
+
+#endif
+
+#ifndef uatomic_xchg
+/* xchg */
+
+static inline __attribute__((always_inline))
+unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
+{
+	switch (len) {
+	case 4:
+	{
+		unsigned int old, oldt;
+
+		oldt = uatomic_read((unsigned int *)addr);
+		do {
+			old = oldt;
+			oldt = _uatomic_cmpxchg(addr, old, val, 4);
+		} while (oldt != old);
+
+		return old;
+	}
+#if (BITS_PER_LONG == 64)
+	case 8:
+	{
+		unsigned long old, oldt;
+
+		oldt = uatomic_read((unsigned long *)addr);
+		do {
+			old = oldt;
+			oldt = _uatomic_cmpxchg(addr, old, val, 8);
+		} while (oldt != old);
+
+		return old;
+	}
+#endif
+	}
+	_uatomic_link_error();
+	return 0;
+}
+
+#define uatomic_xchg(addr, v)						    \
+	((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
+						sizeof(*(addr))))
+#endif
+
+/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
+
+#ifndef uatomic_add
+#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
+#endif
+
+#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))
+#define uatomic_sub(addr, v)		uatomic_add((addr), -(v))
+
+#ifndef uatomic_inc
+#define uatomic_inc(addr)		uatomic_add((addr), 1)
+#endif
+
+#ifndef uatomic_dec
+#define uatomic_dec(addr)		uatomic_add((addr), -1)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _URCU_UATOMIC_GCC_H */
-- 
1.6.6

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> From most of the architectures, we can derive the implementation
> of xchg and add_return from cmpxchg:
> 
> - if cmpxchg is present, use it to implement xchg and add_return;

Not sure I understand this comment, and not sure it matches the patch.
x86 has xchg() which is faster than a cmpxchg-based fallback, and you
seem to leave the code as-is. Can you elaborate ?

> 
> - if it is not present, implement all three using __sync_* builtins
> 

Starting from which gcc versions does these __sync_* builtins work ?
(question applies for the builtin memory barrier too).

Thanks,

Mathieu

> The hunk in tests/test_uatomic.c is only needed for bisectability
> and will be removed later.
> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
> ---
>  Makefile.am                 |    2 +-
>  tests/test_uatomic.c        |    2 +
>  urcu/uatomic_arch_ppc.h     |   15 +---
>  urcu/uatomic_arch_s390.h    |   15 +---
>  urcu/uatomic_arch_sparc64.h |   15 +---
>  urcu/uatomic_arch_x86.h     |   26 ++----
>  urcu/uatomic_gcc.h          |  221 +++++++++++++++++++++++++++++++++++++++++++
>  7 files changed, 239 insertions(+), 57 deletions(-)
>  create mode 100644 urcu/uatomic_gcc.h
> 
> diff --git a/Makefile.am b/Makefile.am
> index 57e9299..d6ee789 100644
> --- a/Makefile.am
> +++ b/Makefile.am
> @@ -6,7 +6,7 @@ SUBDIRS = . tests
>  
>  include_HEADERS = urcu.h $(top_srcdir)/urcu-*.h
>  nobase_dist_include_HEADERS = urcu/compiler.h urcu/hlist.h urcu/list.h \
> -		urcu/rculist.h urcu/system.h urcu/urcu-futex.h
> +		urcu/rculist.h urcu/system.h urcu/urcu-futex.h urcu/uatomic_gcc.h
>  nobase_nodist_include_HEADERS = urcu/arch.h urcu/uatomic_arch.h urcu/config.h
>  
>  EXTRA_DIST = $(top_srcdir)/urcu/arch_*.h $(top_srcdir)/urcu/uatomic_arch_*.h \
> diff --git a/tests/test_uatomic.c b/tests/test_uatomic.c
> index 68cb6df..c0f36fe 100644
> --- a/tests/test_uatomic.c
> +++ b/tests/test_uatomic.c
> @@ -1,5 +1,7 @@
>  #include <stdio.h>
>  #include <assert.h>
> +
> +#define UATOMIC_NO_LINK_ERROR
>  #include <urcu/uatomic_arch.h>
>  
>  #if (defined(__i386__) || defined(__x86_64__))
> diff --git a/urcu/uatomic_arch_ppc.h b/urcu/uatomic_arch_ppc.h
> index 7106b99..c611c7a 100644
> --- a/urcu/uatomic_arch_ppc.h
> +++ b/urcu/uatomic_arch_ppc.h
> @@ -39,9 +39,6 @@ extern "C" {
>  
>  #define ILLEGAL_INSTR	".long	0xd00d00"
>  
> -#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
> -#define uatomic_read(addr)	LOAD_SHARED(*(addr))
> -
>  /*
>   * Using a isync as second barrier for exchange to provide acquire semantic.
>   * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
> @@ -217,18 +214,10 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val,
>  						  (unsigned long)(v),	\
>  						  sizeof(*(addr))))
>  
> -/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
> -
> -#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))
> -
> -#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
> -#define uatomic_sub(addr, v)		(void)uatomic_sub_return((addr), (v))
> -
> -#define uatomic_inc(addr)		uatomic_add((addr), 1)
> -#define uatomic_dec(addr)		uatomic_add((addr), -1)
> -
>  #ifdef __cplusplus 
>  }
>  #endif
>  
> +#include <urcu/uatomic_gcc.h>
> +
>  #endif /* _URCU_ARCH_UATOMIC_PPC_H */
> diff --git a/urcu/uatomic_arch_s390.h b/urcu/uatomic_arch_s390.h
> index 6247601..9d4b74e 100644
> --- a/urcu/uatomic_arch_s390.h
> +++ b/urcu/uatomic_arch_s390.h
> @@ -70,9 +70,6 @@ struct __uatomic_dummy {
>  };
>  #define __hp(x)	((struct __uatomic_dummy *)(x))
>  
> -#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
> -#define uatomic_read(addr)	LOAD_SHARED(*(addr))
> -
>  /* xchg */
>  
>  static inline __attribute__((always_inline))
> @@ -200,18 +197,10 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
>  						  (unsigned long)(v),	\
>  						  sizeof(*(addr))))
>  
> -/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
> -
> -#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))
> -
> -#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
> -#define uatomic_sub(addr, v)		(void)uatomic_sub_return((addr), (v))
> -
> -#define uatomic_inc(addr)		uatomic_add((addr), 1)
> -#define uatomic_dec(addr)		uatomic_add((addr), -1)
> -
>  #ifdef __cplusplus 
>  }
>  #endif
>  
> +#include <urcu/uatomic_gcc.h>
> +
>  #endif /* _URCU_UATOMIC_ARCH_S390_H */
> diff --git a/urcu/uatomic_arch_sparc64.h b/urcu/uatomic_arch_sparc64.h
> index e984986..d21d73c 100644
> --- a/urcu/uatomic_arch_sparc64.h
> +++ b/urcu/uatomic_arch_sparc64.h
> @@ -31,9 +31,6 @@ extern "C" {
>  #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
>  #endif
>  
> -#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
> -#define uatomic_read(addr)	LOAD_SHARED(*(addr))
> -
>  /* cmpxchg */
>  
>  static inline __attribute__((always_inline))
> @@ -161,18 +158,10 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
>  						  (unsigned long)(v),	\
>  						  sizeof(*(addr))))
>  
> -/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
> -
> -#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))
> -
> -#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
> -#define uatomic_sub(addr, v)		(void)uatomic_sub_return((addr), (v))
> -
> -#define uatomic_inc(addr)		uatomic_add((addr), 1)
> -#define uatomic_dec(addr)		uatomic_add((addr), -1)
> -
>  #ifdef __cplusplus 
>  }
>  #endif
>  
> +#include <urcu/uatomic_gcc.h>
> +
>  #endif /* _URCU_ARCH_UATOMIC_PPC_H */
> diff --git a/urcu/uatomic_arch_x86.h b/urcu/uatomic_arch_x86.h
> index 34f5f87..0aadbd5 100644
> --- a/urcu/uatomic_arch_x86.h
> +++ b/urcu/uatomic_arch_x86.h
> @@ -41,7 +41,11 @@ struct __uatomic_dummy {
>  #define __hp(x)	((struct __uatomic_dummy *)(x))
>  
>  #define _uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
> +
> +#if 0
> +/* Read is atomic even in compat mode */
>  #define _uatomic_read(addr)	LOAD_SHARED(*(addr))
> +#endif
>  
>  /* cmpxchg */
>  
> @@ -168,7 +172,7 @@ unsigned long __uatomic_exchange(void *addr, unsigned long val, int len)
>  	((__typeof__(*(addr))) __uatomic_exchange((addr), (unsigned long)(v), \
>  						sizeof(*(addr))))
>  
> -/* uatomic_add_return, uatomic_sub_return */
> +/* uatomic_add_return */
>  
>  static inline __attribute__((always_inline))
>  unsigned long __uatomic_add_return(void *addr, unsigned long val,
> @@ -233,9 +237,7 @@ unsigned long __uatomic_add_return(void *addr, unsigned long val,
>  						  (unsigned long)(v),	\
>  						  sizeof(*(addr))))
>  
> -#define _uatomic_sub_return(addr, v)	_uatomic_add_return((addr), -(v))
> -
> -/* uatomic_add, uatomic_sub */
> +/* uatomic_add */
>  
>  static inline __attribute__((always_inline))
>  void __uatomic_add(void *addr, unsigned long val, int len)
> @@ -289,8 +291,6 @@ void __uatomic_add(void *addr, unsigned long val, int len)
>  #define _uatomic_add(addr, v)						   \
>  	(__uatomic_add((addr), (unsigned long)(v), sizeof(*(addr))))
>  
> -#define _uatomic_sub(addr, v)	_uatomic_add((addr), -(v))
> -
>  
>  /* uatomic_inc */
>  
> @@ -441,24 +441,17 @@ extern unsigned long _compat_uatomic_xchg(void *addr,
>  						(unsigned long)(v), 	       \
>  						sizeof(*(addr))))
>  
> -#define compat_uatomic_sub_return(addr, v)				       \
> -		compat_uatomic_add_return((addr), -(v))
>  #define compat_uatomic_add(addr, v)					       \
>  		((void)compat_uatomic_add_return((addr), (v)))
> -#define compat_uatomic_sub(addr, v)					       \
> -		((void)compat_uatomic_sub_return((addr), (v)))
>  #define compat_uatomic_inc(addr)					       \
>  		(compat_uatomic_add((addr), 1))
>  #define compat_uatomic_dec(addr)					       \
> -		(compat_uatomic_sub((addr), 1))
> +		(compat_uatomic_add((addr), -1))
>  
>  #else
>  #define UATOMIC_COMPAT(insn)	(_uatomic_##insn)
>  #endif
>  
> -/* Read is atomic even in compat mode */
> -#define uatomic_read(addr)	_uatomic_read(addr)
> -
>  #define uatomic_set(addr, v)			\
>  		UATOMIC_COMPAT(set(addr, v))
>  #define uatomic_cmpxchg(addr, old, _new)	\
> @@ -467,10 +460,7 @@ extern unsigned long _compat_uatomic_xchg(void *addr,
>  		UATOMIC_COMPAT(xchg(addr, v))
>  #define uatomic_add_return(addr, v)		\
>  		UATOMIC_COMPAT(add_return(addr, v))
> -#define uatomic_sub_return(addr, v)		\
> -		UATOMIC_COMPAT(sub_return(addr, v))
>  #define uatomic_add(addr, v)	UATOMIC_COMPAT(add(addr, v))
> -#define uatomic_sub(addr, v)	UATOMIC_COMPAT(sub(addr, v))
>  #define uatomic_inc(addr)	UATOMIC_COMPAT(inc(addr))
>  #define uatomic_dec(addr)	UATOMIC_COMPAT(dec(addr))
>  
> @@ -478,4 +468,6 @@ extern unsigned long _compat_uatomic_xchg(void *addr,
>  }
>  #endif
>  
> +#include <urcu/uatomic_gcc.h>
> +
>  #endif /* _URCU_ARCH_UATOMIC_X86_H */
> diff --git a/urcu/uatomic_gcc.h b/urcu/uatomic_gcc.h
> new file mode 100644
> index 0000000..28f6d71
> --- /dev/null
> +++ b/urcu/uatomic_gcc.h
> @@ -0,0 +1,223 @@
> +#ifndef _URCU_UATOMIC_GCC_H
> +#define _URCU_UATOMIC_GCC_H
> +
> +/*
> + * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
> + * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
> + * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
> + * Copyright (c) 2009      Mathieu Desnoyers
> + * Copyright (c) 2010      Paolo Bonzini
> + *
> + * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
> + * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
> + *
> + * Permission is hereby granted to use or copy this program
> + * for any purpose,  provided the above notices are retained on all copies.
> + * Permission to modify the code and to distribute modified code is granted,
> + * provided the above notices are retained, and a notice that the code was
> + * modified is included with the above copyright notice.
> + *
> + * Code inspired from libuatomic_ops-1.2, inherited in part from the
> + * Boehm-Demers-Weiser conservative garbage collector.
> + */
> +
> +#include <urcu/compiler.h>
> +#include <urcu/system.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#ifndef BITS_PER_LONG
> +#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
> +#endif
> +
> +#ifndef uatomic_set
> +#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
> +#endif
> +
> +#ifndef uatomic_read
> +#define uatomic_read(addr)	LOAD_SHARED(*(addr))
> +#endif
> +
> +#if !defined __OPTIMIZE__  || defined UATOMIC_NO_LINK_ERROR
> +static inline __attribute__((always_inline))
> +void _uatomic_link_error()
> +{
> +#ifdef ILLEGAL_INSTR
> +	/* generate an illegal instruction. Cannot catch this with linker tricks
> +	 * when optimizations are disabled. */
> +	__asm__ __volatile__(ILLEGAL_INSTR);
> +#else
> +	__builtin_trap ();
> +#endif
> +}
> +#else
> +extern void _uatomic_link_error ();
> +#endif
> +
> +/* cmpxchg */
> +
> +#ifndef uatomic_cmpxchg
> +static inline __attribute__((always_inline))
> +unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
> +			      unsigned long _new, int len)
> +{
> +	switch (len) {
> +	case 4:
> +		return __sync_val_compare_and_swap_4(addr, old, _new);
> +#if (BITS_PER_LONG == 64)
> +	case 8:
> +		return __sync_val_compare_and_swap_8(addr, old, _new);
> +#endif
> +	}
> +	_uatomic_link_error();
> +	return 0;
> +}
> +
> +
> +#define uatomic_cmpxchg(addr, old, _new)				    \
> +	((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
> +						(unsigned long)(_new), 	    \
> +						sizeof(*(addr))))
> +
> +
> +/* uatomic_add_return */
> +
> +#ifndef uatomic_add_return
> +static inline __attribute__((always_inline))
> +unsigned long _uatomic_add_return(void *addr, unsigned long val,
> +				 int len)
> +{
> +	switch (len) {
> +	case 4:
> +		return __sync_add_and_fetch_4(addr, val);
> +#if (BITS_PER_LONG == 64)
> +	case 8:
> +		return __sync_add_and_fetch_8(addr, val);
> +#endif
> +	}
> +	_uatomic_link_error();
> +	return 0;
> +}
> +
> +
> +#define uatomic_add_return(addr, v)					\
> +	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
> +						  (unsigned long)(v),	\
> +						  sizeof(*(addr))))
> +#endif
> +
> +#else
> +
> +#ifndef uatomic_add_return
> +/* uatomic_add_return */
> +
> +static inline __attribute__((always_inline))
> +unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
> +{
> +	switch (len) {
> +	case 4:
> +	{
> +		unsigned int old, oldt;
> +
> +		oldt = uatomic_read((unsigned int *)addr);
> +		do {
> +			old = oldt;
> +			oldt = _uatomic_cmpxchg(addr, old, old + val, 4);
> +		} while (oldt != old);
> +
> +		return old + val;
> +	}
> +#if (BITS_PER_LONG == 64)
> +	case 8:
> +	{
> +		unsigned long old, oldt;
> +
> +		oldt = uatomic_read((unsigned long *)addr);
> +		do {
> +			old = oldt;
> +			oldt = _uatomic_cmpxchg(addr, old, old + val, 8);
> +		} while (oldt != old);
> +
> +		return old + val;
> +	}
> +#endif
> +	}
> +	_uatomic_link_error();
> +	return 0;
> +}
> +
> +#define uatomic_add_return(addr, v)					\
> +	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
> +						  (unsigned long)(v),	\
> +						  sizeof(*(addr))))
> +#endif
> +
> +#endif
> +
> +#ifndef uatomic_xchg
> +/* xchg */
> +
> +static inline __attribute__((always_inline))
> +unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
> +{
> +	switch (len) {
> +	case 4:
> +	{
> +		unsigned int old, oldt;
> +
> +		oldt = uatomic_read((unsigned int *)addr);
> +		do {
> +			old = oldt;
> +			oldt = _uatomic_cmpxchg(addr, old, val, 4);
> +		} while (oldt != old);
> +
> +		return old;
> +	}
> +#if (BITS_PER_LONG == 64)
> +	case 8:
> +	{
> +		unsigned long old, oldt;
> +
> +		oldt = uatomic_read((unsigned long *)addr);
> +		do {
> +			old = oldt;
> +			oldt = _uatomic_cmpxchg(addr, old, val, 8);
> +		} while (oldt != old);
> +
> +		return old;
> +	}
> +#endif
> +	}
> +	_uatomic_link_error();
> +	return 0;
> +}
> +
> +#define uatomic_xchg(addr, v)						    \
> +	((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
> +						sizeof(*(addr))))
> +#endif
> +
> +/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
> +
> +#ifndef uatomic_add
> +#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
> +#endif
> +
> +#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))
> +#define uatomic_sub(addr, v)		uatomic_add((addr), -(v))
> +
> +#ifndef uatomic_inc
> +#define uatomic_inc(addr)		uatomic_add((addr), 1)
> +#endif
> +
> +#ifndef uatomic_dec
> +#define uatomic_dec(addr)		uatomic_add((addr), -1)
> +#endif
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* _URCU_UATOMIC_GCC_H */
> -- 
> 1.6.6
> 
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Paolo Bonzini]

On 02/14/2010 03:45 PM, Mathieu Desnoyers wrote:
>> >  - if cmpxchg is present, use it to implement xchg and add_return;
>
> Not sure I understand this comment, and not sure it matches the patch.
> x86 has xchg() which is faster than a cmpxchg-based fallback, and you
> seem to leave the code as-is. Can you elaborate ?

Each per-architecture file can provide its own xchg and add_return which 
are then used instead of the defaults.  For example, x86 uses entirely 
custom code, and PPC uses its own implementation of xchg (since it is 
also much faster than cmpxchg on ll/sc machines).

Basically, in this case uatomic_gcc.h is using the approach of 
uatomic_arch_sparc64.h.

>> >  - if it is not present, implement all three using __sync_* builtins
>
> Starting from which gcc versions does these __sync_* builtins work ?
> (question applies for the builtin memory barrier too).

The builtins appeared in 4.2, but they were backported to 4.1 by some 
vendors.

Note that on SPARC64 and S390 they were already needed to build the 
library because the tests used them.urcu-bp-static.h.  However the 
clients of liburcu did not need the compiler to have __sync builtins.

After this patch, a new compiler is necessary on S390 and PPC to use the 
following files:

urcu-bp-static.h:#include <urcu/uatomic_arch.h>
urcu-defer-static.h:#include <urcu/uatomic_arch.h>
urcu-pointer-static.h:#include <urcu/uatomic_arch.h>
urcu-pointer.h:#include <urcu/uatomic_arch.h>
urcu-qsbr-static.h:#include <urcu/uatomic_arch.h>
urcu-static.h:#include <urcu/uatomic_arch.h>

I'll test a patch to remove the inclusion from urcu-pointer.h since it 
seems unnecessary to me.

After this, a client that is interested in using an older GCC can thus 
use _LGPL_SOURCE if it finds a compiler that is not new enough.  I can 
also make this automatic if you prefer.

Paolo

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> On 02/14/2010 03:45 PM, Mathieu Desnoyers wrote:
>>> >  - if cmpxchg is present, use it to implement xchg and add_return;
>>
>> Not sure I understand this comment, and not sure it matches the patch.
>> x86 has xchg() which is faster than a cmpxchg-based fallback, and you
>> seem to leave the code as-is. Can you elaborate ?
>
> Each per-architecture file can provide its own xchg and add_return which  
> are then used instead of the defaults.  For example, x86 uses entirely  
> custom code, and PPC uses its own implementation of xchg (since it is  
> also much faster than cmpxchg on ll/sc machines).

OK. Please update the changelog comment with the information above.

>
> Basically, in this case uatomic_gcc.h is using the approach of  
> uatomic_arch_sparc64.h.
>
>>> >  - if it is not present, implement all three using __sync_* builtins
>>
>> Starting from which gcc versions does these __sync_* builtins work ?
>> (question applies for the builtin memory barrier too).
>
> The builtins appeared in 4.2, but they were backported to 4.1 by some  
> vendors.
>
> Note that on SPARC64 and S390 they were already needed to build the  
> library because the tests used them.urcu-bp-static.h.  However the  
> clients of liburcu did not need the compiler to have __sync builtins.

For __builtin_trap() I suspect. This could be changed if needed.

>
> After this patch, a new compiler is necessary on S390 and PPC to use the  
> following files:
>
> urcu-bp-static.h:#include <urcu/uatomic_arch.h>
> urcu-defer-static.h:#include <urcu/uatomic_arch.h>
> urcu-pointer-static.h:#include <urcu/uatomic_arch.h>
> urcu-pointer.h:#include <urcu/uatomic_arch.h>
> urcu-qsbr-static.h:#include <urcu/uatomic_arch.h>
> urcu-static.h:#include <urcu/uatomic_arch.h>
>
> I'll test a patch to remove the inclusion from urcu-pointer.h since it  
> seems unnecessary to me.

How do you plan to let people publish and dereference RCU data then ?

>
> After this, a client that is interested in using an older GCC can thus  
> use _LGPL_SOURCE if it finds a compiler that is not new enough.  I can  
> also make this automatic if you prefer.

Hrm, that's a problem. We cannot just say "hey, update the test systems
you are working with to newer compilers" to people who often only borrow
these systems and have to deal with the very often deprecated toolchains
available. This is the case for a 64-core POWER5+ we are doing testing
on: we're stuck with an old gcc.

Paul, what's the oldest gcc versions you think would be sane to support ?

Thanks,

Mathieu

>
> Paolo
>

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Paolo Bonzini]

On 02/15/2010 03:55 PM, Mathieu Desnoyers wrote:
> * Paolo Bonzini (pbonzini at redhat.com) wrote:
>> On 02/14/2010 03:45 PM, Mathieu Desnoyers wrote:
>>>>>   - if cmpxchg is present, use it to implement xchg and add_return;
>>>
>>> Not sure I understand this comment, and not sure it matches the patch.
>>> x86 has xchg() which is faster than a cmpxchg-based fallback, and you
>>> seem to leave the code as-is. Can you elaborate ?
>>
>> Each per-architecture file can provide its own xchg and add_return which
>> are then used instead of the defaults.  For example, x86 uses entirely
>> custom code, and PPC uses its own implementation of xchg (since it is
>> also much faster than cmpxchg on ll/sc machines).
>
> OK. Please update the changelog comment with the information above.

Will do.

>>> Starting from which gcc versions does these __sync_* builtins work ?
>>> (question applies for the builtin memory barrier too).
>>
>> The builtins appeared in 4.2, but they were backported to 4.1 by some
>> vendors.
>>
>> Note that on SPARC64 and S390 they were already needed to build the
>> library because the tests used them.
>
> For __builtin_trap() I suspect. This could be changed if needed.

No, for api_gcc.h.

>> After this, a client that is interested in using an older GCC can thus
>> use _LGPL_SOURCE if it finds a compiler that is not new enough.  I can
>> also make this automatic if you prefer.
>
> Hrm, that's a problem. We cannot just say "hey, update the test systems
> you are working with to newer compilers" to people who often only borrow
> these systems and have to deal with the very often deprecated toolchains
> available. This is the case for a 64-core POWER5+ we are doing testing
> on: we're stuck with an old gcc.

Ok, I won't update PPC then.

Paolo

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> On 02/15/2010 03:55 PM, Mathieu Desnoyers wrote:
>> * Paolo Bonzini (pbonzini at redhat.com) wrote:
>>> On 02/14/2010 03:45 PM, Mathieu Desnoyers wrote:
>>>>>>   - if cmpxchg is present, use it to implement xchg and add_return;
>>>>
>>>> Not sure I understand this comment, and not sure it matches the patch.
>>>> x86 has xchg() which is faster than a cmpxchg-based fallback, and you
>>>> seem to leave the code as-is. Can you elaborate ?
>>>
>>> Each per-architecture file can provide its own xchg and add_return which
>>> are then used instead of the defaults.  For example, x86 uses entirely
>>> custom code, and PPC uses its own implementation of xchg (since it is
>>> also much faster than cmpxchg on ll/sc machines).
>>
>> OK. Please update the changelog comment with the information above.
>
> Will do.
>
>>>> Starting from which gcc versions does these __sync_* builtins work ?
>>>> (question applies for the builtin memory barrier too).
>>>
>>> The builtins appeared in 4.2, but they were backported to 4.1 by some
>>> vendors.
>>>
>>> Note that on SPARC64 and S390 they were already needed to build the
>>> library because the tests used them.
>>
>> For __builtin_trap() I suspect. This could be changed if needed.
>
> No, for api_gcc.h.

Well, api_gcc is only used for some of the library internal tests. It
should not be considered as one of the "public" headers. I'm afraid I
don't see which builtins you refer to. Could you be more specific ?

>
>>> After this, a client that is interested in using an older GCC can thus
>>> use _LGPL_SOURCE if it finds a compiler that is not new enough.  I can
>>> also make this automatic if you prefer.
>>
>> Hrm, that's a problem. We cannot just say "hey, update the test systems
>> you are working with to newer compilers" to people who often only borrow
>> these systems and have to deal with the very often deprecated toolchains
>> available. This is the case for a 64-core POWER5+ we are doing testing
>> on: we're stuck with an old gcc.
>
> Ok, I won't update PPC then.

Well, the fact that we personally test on a POWER machine with an old
compiler is irrelevant. This question is broader than that.

Either:

1) We choose to discard support for old compilers on all architectures.
  + simple/clean code
  + easier to maintain
  + less error-prone, using widely tested gcc builtins.
  - liburcu become incompatible with lots of systems still being used today.

2) We choose to stick to custom per-architecture macros (only).
  - more complex code.
  - more code to maintain.
  - more testing needed because we are not using gcc builtins.
  - requires an initial effort to port liburcu to new architectures.
  + provides support for gcc compilers back to early 3.x versions.
  + test suites covers all gcc versions (no special-cases for old vs new
    versions). Ensures that the code does not get bitrotten by not being
    tested.

3) We choose to stick to custom per-arch macros, and use gcc builtins for
   architectures for new architectures we want to support.
   Same +/- as (2), with this distinction:
   + diminish initial port effort, because we can provide support for
     new architectures (except for old compilers) quickly by using builtins.

4) Detect compiler versions with the precompiler. Use builtins for new
   compilers, and explicit declarations for old compilers.
  - more complex code.
  - more code to maintain.
  - more testing needed because we are not using gcc builtins.
  - requires an initial effort to port liburcu to new architectures.
  - test suites have to test for many compiler versions. Chances are
    that the "old compiler compatibility" code will get much less
    tested. This is, IMHO, a recipe for a disaster, as bugs will creap
    in and testing will be hard.
  + provides support for gcc compilers back to early 3.x versions.

The current approach for liburcu is (2), but I think it's good to move
to (3). However, I really dislike (4) because it makes testing much
harder, and (1) is, I think, a no-go for a library meant to be usable on
the large ecosystem of systems we have today (some with old compilers).

Thoughts ?

Mathieu


>
> Paolo
>

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Paolo Bonzini]

On 02/15/2010 05:23 PM, Mathieu Desnoyers wrote:
> 1) We choose to discard support for old compilers on all architectures.
>    + simple/clean code
>    + easier to maintain
>    + less error-prone, using widely tested gcc builtins.
>    - liburcu become incompatible with lots of systems still being used today.

This is v1 of my patchset, and I understand it's too much.  (To be 
precise v1 was a bit less strict, as x86 and SPARC64 would remain 
compatible with old compilers).

It is too aggressive considering the other possibilities.

> 2) We choose to stick to custom per-architecture macros (only).
>    - more complex code.
>    - more code to maintain.
>    - more testing needed because we are not using gcc builtins.
>    - requires an initial effort to port liburcu to new architectures.
>    + provides support for gcc compilers back to early 3.x versions.
>    + test suites covers all gcc versions (no special-cases for old vs new
>      versions). Ensures that the code does not get bitrotten by not being
>      tested.

This is the status quo, besides the fact that S390 and SPARC64 are 
already using GCC builtins in non-public headers.

> 3) We choose to stick to custom per-arch macros, and use gcc builtins for
>     architectures for new architectures we want to support.
>     Same ? as (2), with this distinction:
>     + diminish initial port effort, because we can provide support for
>       new architectures (except for old compilers) quickly by using builtins.
>
> 4) Detect compiler versions with the precompiler. Use builtins for new
>     compilers, and explicit declarations for old compilers.
>    - more complex code.
>    - more code to maintain.
>    - more testing needed because we are not using gcc builtins.
>    - requires an initial effort to port liburcu to new architectures.
>    - test suites have to test for many compiler versions. Chances are
>      that the "old compiler compatibility" code will get much less
>      tested. This is, IMHO, a recipe for a disaster, as bugs will creap
>      in and testing will be hard.
>    + provides support for gcc compilers back to early 3.x versions.

(5) We choose to discard support for old compilers on all architectures, 
but fallback to non-_LGPL_SOURCE on all compilers
     + simple/clean code
     + easier to maintain
     + less error-prone (even though it's not really possible to use GCC
       builtins everywhere)
    - liburcu becomes less efficient on lots of systems in use today

> The current approach for liburcu is (2), but I think it's good to move
> to (3). However, I really dislike (4) because it makes testing much
> harder, and (1) is, I think, a no-go for a library meant to be usable on
> the large ecosystem of systems we have today (some with old compilers).

Exactly.

(3) is the most balanced and reasonable as things stand now.

(4) is definitely going to bitrot sooner than later (it would cost just 
an #ifdef...#endif around what we have now, but the problem of course is 
what goes inside the #ifdef).

I was thinking of doing (3) with the additional twist that S390 would 
count as a "new architecture".  On it, GCC is providing really 
everything that is needed and furthermore, unlike PPC, your testers 
surely have a new-enough GCC because they're using api_gcc.h.

Switching from (3) to (5) can be done later, after evaluating more 
carefully the pros and cons.  What do you think?

Paolo

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> On 02/15/2010 05:23 PM, Mathieu Desnoyers wrote:
>> 1) We choose to discard support for old compilers on all architectures.
>>    + simple/clean code
>>    + easier to maintain
>>    + less error-prone, using widely tested gcc builtins.
>>    - liburcu become incompatible with lots of systems still being used today.
>
> This is v1 of my patchset, and I understand it's too much.  (To be  
> precise v1 was a bit less strict, as x86 and SPARC64 would remain  
> compatible with old compilers).
>
> It is too aggressive considering the other possibilities.
>
>> 2) We choose to stick to custom per-architecture macros (only).
>>    - more complex code.
>>    - more code to maintain.
>>    - more testing needed because we are not using gcc builtins.
>>    - requires an initial effort to port liburcu to new architectures.
>>    + provides support for gcc compilers back to early 3.x versions.
>>    + test suites covers all gcc versions (no special-cases for old vs new
>>      versions). Ensures that the code does not get bitrotten by not being
>>      tested.
>
> This is the status quo, besides the fact that S390 and SPARC64 are  
> already using GCC builtins in non-public headers.

These non-public headers could possibly be changed to remove the builtin
dependencies.

>
>> 3) We choose to stick to custom per-arch macros, and use gcc builtins for
>>     architectures for new architectures we want to support.
>>     Same ? as (2), with this distinction:
>>     + diminish initial port effort, because we can provide support for
>>       new architectures (except for old compilers) quickly by using builtins.
>>
>> 4) Detect compiler versions with the precompiler. Use builtins for new
>>     compilers, and explicit declarations for old compilers.
>>    - more complex code.
>>    - more code to maintain.
>>    - more testing needed because we are not using gcc builtins.
>>    - requires an initial effort to port liburcu to new architectures.
>>    - test suites have to test for many compiler versions. Chances are
>>      that the "old compiler compatibility" code will get much less
>>      tested. This is, IMHO, a recipe for a disaster, as bugs will creap
>>      in and testing will be hard.
>>    + provides support for gcc compilers back to early 3.x versions.
>
> (5) We choose to discard support for old compilers on all architectures,  
> but fallback to non-_LGPL_SOURCE on all compilers
>     + simple/clean code
>     + easier to maintain
>     + less error-prone (even though it's not really possible to use GCC
>       builtins everywhere)
>    - liburcu becomes less efficient on lots of systems in use today

Well, a supplementary problem with this approach is that people who need
to build their libraries themself for architectures where gcc is not
up-to-date will hit a wall. Not everyone has the luxury of using
pre-packaged and pre-built versions of the libraries, especially in the
embedded field.

>
>> The current approach for liburcu is (2), but I think it's good to move
>> to (3). However, I really dislike (4) because it makes testing much
>> harder, and (1) is, I think, a no-go for a library meant to be usable on
>> the large ecosystem of systems we have today (some with old compilers).
>
> Exactly.
>
> (3) is the most balanced and reasonable as things stand now.
>
> (4) is definitely going to bitrot sooner than later (it would cost just  
> an #ifdef...#endif around what we have now, but the problem of course is  
> what goes inside the #ifdef).
>
> I was thinking of doing (3) with the additional twist that S390 would  
> count as a "new architecture".  On it, GCC is providing really  
> everything that is needed and furthermore, unlike PPC, your testers  
> surely have a new-enough GCC because they're using api_gcc.h.

Hrm. As things stand, I would recommend plainly going with (3), using
gcc builtins only for the new architectures which are not supported at
the moment, being ready to merge compatibility code for these
architectures if we see the need for it at some point.

From this point of view, moving s390 from the custom operations to gcc
builtins seems like a step backward. I'd prefer to look into the
api_gcc.h issues and fix those so we can ensure that sparc64 and s390
are OK with older gcc.

We should also put a statement in the README file stating which
compilers we target.

>
> Switching from (3) to (5) can be done later, after evaluating more  
> carefully the pros and cons.  What do you think?

As I pointed out above, the problem with (5) is that embedded developers
who build their own libraries will run into toolchain version issues.

Thanks,

Mathieu

>
> Paolo
>

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Paolo Bonzini]

On 02/15/2010 05:51 PM, Mathieu Desnoyers wrote:
>>>
>>> I was thinking of doing (3) with the additional twist that S390
>>> would count as a "new architecture".  On it, GCC is providing
>>> really everything that is needed and furthermore, unlike PPC,
>>> your testers surely have a new-enough GCC because they're using
>>> api_gcc.h.
> Hrm. As things stand, I would recommend plainly going with (3),
> using gcc builtins only for the new architectures which are not
> supported at the moment, being ready to merge compatibility code for
> these architectures if we see the need for it at some point.
>
> From this point of view, moving s390 from the custom operations to
> gcc builtins seems like a step backward.

Fine, will adjust.

> I'd prefer to look into the api_gcc.h issues and fix those so we can
> ensure that sparc64 and s390 are OK with older gcc.

Requiring GCC for testing purposes doesn't seem too bad, but I guess 
this latest paragraph was a kind of "patches are welcome" thing. :-)

Paolo

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> On 02/15/2010 05:51 PM, Mathieu Desnoyers wrote:
>>>>
>>>> I was thinking of doing (3) with the additional twist that S390
>>>> would count as a "new architecture".  On it, GCC is providing
>>>> really everything that is needed and furthermore, unlike PPC,
>>>> your testers surely have a new-enough GCC because they're using
>>>> api_gcc.h.
>> Hrm. As things stand, I would recommend plainly going with (3),
>> using gcc builtins only for the new architectures which are not
>> supported at the moment, being ready to merge compatibility code for
>> these architectures if we see the need for it at some point.
>>
>> From this point of view, moving s390 from the custom operations to
>> gcc builtins seems like a step backward.
>
> Fine, will adjust.
>
>> I'd prefer to look into the api_gcc.h issues and fix those so we can
>> ensure that sparc64 and s390 are OK with older gcc.
>
> Requiring GCC for testing purposes doesn't seem too bad, but I guess  
> this latest paragraph was a kind of "patches are welcome" thing. :-)

Exactly ;)

Thanks,

Mathieu

>
> Paolo
>

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [PATCH 07/11] add uatomic_gcc.h, use it for default definitions

[Paolo Bonzini]

On 02/14/2010 03:45 PM, Mathieu Desnoyers wrote:
>> >  - if cmpxchg is present, use it to implement xchg and add_return;
>
> Not sure I understand this comment, and not sure it matches the patch.
> x86 has xchg() which is faster than a cmpxchg-based fallback, and you
> seem to leave the code as-is. Can you elaborate ?

Each per-architecture file can provide its own xchg and add_return which 
are then used instead of the defaults.  For example, x86 uses entirely 
custom code, and PPC uses its own implementation of xchg (since it is 
also much faster than cmpxchg on ll/sc machines).

Basically, in this case uatomic_gcc.h is using the approach of 
uatomic_arch_sparc64.h.

>> >  - if it is not present, implement all three using __sync_* builtins
>
> Starting from which gcc versions does these __sync_* builtins work ?
> (question applies for the builtin memory barrier too).

The builtins appeared in 4.2, but they were backported to 4.1 by some 
vendors.

Note that on SPARC64 and S390 they were already needed to build the 
library because the tests used them.urcu-bp-static.h.  However the 
clients of liburcu did not need the compiler to have __sync builtins.

After this patch, a new compiler is necessary on S390 and PPC to use the 
following files:

urcu-bp-static.h:#include <urcu/uatomic_arch.h>
urcu-defer-static.h:#include <urcu/uatomic_arch.h>
urcu-pointer-static.h:#include <urcu/uatomic_arch.h>
urcu-pointer.h:#include <urcu/uatomic_arch.h>
urcu-qsbr-static.h:#include <urcu/uatomic_arch.h>
urcu-static.h:#include <urcu/uatomic_arch.h>

I'll test a patch to remove the inclusion from urcu-pointer.h since it 
seems unnecessary to me.

After this, a client that is interested in using an older GCC can thus 
use _LGPL_SOURCE if it finds a compiler that is not new enough.  It's 
not really good to make this automatic because if someone for example 
cares about x86 only, they are fine using _LGPL_SOURCE with any compiler 
version.

Paolo

[ltt-dev] [PATCH 08/11] use uatomic_gcc.h

[Paolo Bonzini]

And now, really remove the code for PPC/S390/SPARC, just use GCC
builtins on those architectures.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/uatomic_arch_ppc.h     |  118 ------------------------------
 urcu/uatomic_arch_s390.h    |  170 -------------------------------------------
 urcu/uatomic_arch_sparc64.h |   84 +---------------------
 3 files changed, 1 insertions(+), 371 deletions(-)

diff --git a/urcu/uatomic_arch_ppc.h b/urcu/uatomic_arch_ppc.h
index c611c7a..c1eb0f5 100644
--- a/urcu/uatomic_arch_ppc.h
+++ b/urcu/uatomic_arch_ppc.h
@@ -96,124 +96,6 @@ unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
 #define uatomic_xchg(addr, v)						    \
 	((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
 						sizeof(*(addr))))
-/* cmpxchg */
-
-static inline __attribute__((always_inline))
-unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
-			      unsigned long _new, int len)
-{
-	switch (len) {
-	case 4:
-	{
-		unsigned int old_val;
-
-		__asm__ __volatile__(
-			LWSYNC_OPCODE
-		"1:\t"	"lwarx %0,0,%1\n"	/* load and reserve */
-			"cmpd %0,%3\n"		/* if load is not equal to */
-			"bne 2f\n"		/* old, fail */
-			"stwcx. %2,0,%1\n"	/* else store conditional */
-			"bne- 1b\n"	 	/* retry if lost reservation */
-			"isync\n"
-		"2:\n"
-				: "=&r"(old_val)
-				: "r"(addr), "r"((unsigned int)_new),
-				  "r"((unsigned int)old)
-				: "memory", "cc");
-
-		return old_val;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long old_val;
-
-		__asm__ __volatile__(
-			LWSYNC_OPCODE
-		"1:\t"	"ldarx %0,0,%1\n"	/* load and reserve */
-			"cmpd %0,%3\n"		/* if load is not equal to */
-			"bne 2f\n"		/* old, fail */
-			"stdcx. %2,0,%1\n"	/* else store conditional */
-			"bne- 1b\n"	 	/* retry if lost reservation */
-			"isync\n"
-		"2:\n"
-				: "=&r"(old_val),
-				: "r"(addr), "r"((unsigned long)_new),
-				  "r"((unsigned long)old)
-				: "memory", "cc");
-
-		return old_val;
-	}
-#endif
-	}
-	/* generate an illegal instruction. Cannot catch this with linker tricks
-	 * when optimizations are disabled. */
-	__asm__ __volatile__(ILLEGAL_INSTR);
-	return 0;
-}
-
-
-#define uatomic_cmpxchg(addr, old, _new)				    \
-	((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
-						(unsigned long)(_new), 	    \
-						sizeof(*(addr))))
-
-/* uatomic_add_return */
-
-static inline __attribute__((always_inline))
-unsigned long _uatomic_add_return(void *addr, unsigned long val,
-				 int len)
-{
-	switch (len) {
-	case 4:
-	{
-		unsigned int result;
-
-		__asm__ __volatile__(
-			LWSYNC_OPCODE
-		"1:\t"	"lwarx %0,0,%1\n"	/* load and reserve */
-			"add %0,%2,%0\n"	/* add val to value loaded */
-			"stwcx. %0,0,%1\n"	/* store conditional */
-			"bne- 1b\n"	 	/* retry if lost reservation */
-			"isync\n"
-				: "=&r"(result)
-				: "r"(addr), "r"(val)
-				: "memory", "cc");
-
-		return result;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long result;
-
-		__asm__ __volatile__(
-			LWSYNC_OPCODE
-		"1:\t"	"ldarx %0,0,%1\n"	/* load and reserve */
-			"add %0,%2,%0\n"	/* add val to value loaded */
-			"stdcx. %0,0,%1\n"	/* store conditional */
-			"bne- 1b\n"	 	/* retry if lost reservation */
-			"isync\n"
-				: "=&r"(result)
-				: "r"(addr), "r"(val)
-				: "memory", "cc");
-
-		return result;
-	}
-#endif
-	}
-	/* generate an illegal instruction. Cannot catch this with linker tricks
-	 * when optimizations are disabled. */
-	__asm__ __volatile__(ILLEGAL_INSTR);
-	return 0;
-}
-
-
-#define uatomic_add_return(addr, v)					\
-	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
-						  (unsigned long)(v),	\
-						  sizeof(*(addr))))
-
 #ifdef __cplusplus 
 }
 #endif
diff --git a/urcu/uatomic_arch_s390.h b/urcu/uatomic_arch_s390.h
index 9d4b74e..cb0269b 100644
--- a/urcu/uatomic_arch_s390.h
+++ b/urcu/uatomic_arch_s390.h
@@ -31,176 +31,6 @@
 
 #include <urcu/compiler.h>
 #include <urcu/system.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
-#endif
-
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-#define COMPILER_HAVE_SHORT_MEM_OPERAND
-#endif
-
-/*
- * MEMOP assembler operand rules:
- * - op refer to MEMOP_IN operand
- * - MEMOP_IN can expand to more than a single operand. Use it at the end of
- *   operand list only.
- */
-
-#ifdef COMPILER_HAVE_SHORT_MEM_OPERAND
-
-#define MEMOP_OUT(addr)	"=Q" (*(addr))
-#define MEMOP_IN(addr)	"Q" (*(addr))
-#define MEMOP_REF(op)	#op		/* op refer to MEMOP_IN operand */
-
-#else /* !COMPILER_HAVE_SHORT_MEM_OPERAND */
-
-#define MEMOP_OUT(addr)	"=m" (*(addr))
-#define MEMOP_IN(addr)	"a" (addr), "m" (*(addr))
-#define MEMOP_REF(op)	"0(" #op ")"	/* op refer to MEMOP_IN operand */
-
-#endif /* !COMPILER_HAVE_SHORT_MEM_OPERAND */
-
-struct __uatomic_dummy {
-	unsigned long v[10];
-};
-#define __hp(x)	((struct __uatomic_dummy *)(x))
-
-/* xchg */
-
-static inline __attribute__((always_inline))
-unsigned long _uatomic_exchange(volatile void *addr, unsigned long val, int len)
-{
-	switch (len) {
-	case 4:
-	{
-		unsigned int old_val;
-
-		__asm__ __volatile__(
-			"0:	cs %0,%2," MEMOP_REF(%3) "\n"
-			"	brc 4,0b\n"
-			: "=&r" (old_val), MEMOP_OUT (__hp(addr))
-			: "r" (val), MEMOP_IN (__hp(addr))
-			: "memory", "cc");
-		return old_val;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long old_val;
-
-		__asm__ __volatile__(
-			"0:	csg %0,%2," MEMOP_REF(%3) "\n"
-			"	brc 4,0b\n"
-			: "=&r" (old_val), MEMOP_OUT (__hp(addr))
-			: "r" (val), MEMOP_IN (__hp(addr))
-			: "memory", "cc");
-		return old_val;
-	}
-#endif
-	default:
-		__asm__ __volatile__(".long	0xd00d00");
-	}
-
-	return 0;
-}
-
-#define uatomic_xchg(addr, v)						    \
-	(__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
-					       sizeof(*(addr)))
-
-/* cmpxchg */
-
-static inline __attribute__((always_inline))
-unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
-			       unsigned long _new, int len)
-{
-	switch (len) {
-	case 4:
-	{
-		unsigned int old_val = (unsigned int)old;
-
-		__asm__ __volatile__(
-			"	cs %0,%2," MEMOP_REF(%3) "\n"
-			: "+r" (old_val), MEMOP_OUT (__hp(addr))
-			: "r" (_new), MEMOP_IN (__hp(addr))
-			: "memory", "cc");
-		return old_val;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		__asm__ __volatile__(
-			"	csg %0,%2," MEMOP_REF(%3) "\n"
-			: "+r" (old), MEMOP_OUT (__hp(addr))
-			: "r" (_new), MEMOP_IN (__hp(addr))
-			: "memory", "cc");
-		return old;
-	}
-#endif
-	default:
-		__asm__ __volatile__(".long	0xd00d00");
-	}
-
-	return 0;
-}
-
-#define uatomic_cmpxchg(addr, old, _new)				\
-	(__typeof__(*(addr))) _uatomic_cmpxchg((addr),			\
-					       (unsigned long)(old),	\
-					       (unsigned long)(_new),	\
-					       sizeof(*(addr)))
-
-/* uatomic_add_return */
-
-static inline __attribute__((always_inline))
-unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
-{
-	switch (len) {
-	case 4:
-	{
-		unsigned int old, oldt;
-
-		oldt = uatomic_read((unsigned int *)addr);
-		do {
-			old = oldt;
-			oldt = _uatomic_cmpxchg(addr, old, old + val, 4);
-		} while (oldt != old);
-
-		return old + val;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long old, oldt;
-
-		oldt = uatomic_read((unsigned long *)addr);
-		do {
-			old = oldt;
-			oldt = _uatomic_cmpxchg(addr, old, old + val, 8);
-		} while (oldt != old);
-
-		return old + val;
-	}
-#endif
-	}
-	__builtin_trap();
-	return 0;
-}
-
-#define uatomic_add_return(addr, v)					\
-	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
-						  (unsigned long)(v),	\
-						  sizeof(*(addr))))
-
-#ifdef __cplusplus 
-}
-#endif
-
 #include <urcu/uatomic_gcc.h>
 
 #endif /* _URCU_UATOMIC_ARCH_S390_H */
diff --git a/urcu/uatomic_arch_sparc64.h b/urcu/uatomic_arch_sparc64.h
index d21d73c..6169447 100644
--- a/urcu/uatomic_arch_sparc64.h
+++ b/urcu/uatomic_arch_sparc64.h
@@ -33,6 +33,7 @@ extern "C" {
 
 /* cmpxchg */
 
+/* GCC only places a memory barrier before.  */
 static inline __attribute__((always_inline))
 unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
 			      unsigned long _new, int len)
@@ -75,89 +76,6 @@ unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
 						(unsigned long)(_new), 	    \
 						sizeof(*(addr))))
 
-/* xchg */
-
-static inline __attribute__((always_inline))
-unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
-{
-	switch (len) {
-	case 4:
-	{
-		unsigned int old, oldt;
-
-		oldt = uatomic_read((unsigned int *)addr);
-		do {
-			old = oldt;
-			oldt = _uatomic_cmpxchg(addr, old, val, 4);
-		} while (oldt != old);
-
-		return old;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long old, oldt;
-
-		oldt = uatomic_read((unsigned long *)addr);
-		do {
-			old = oldt;
-			oldt = _uatomic_cmpxchg(addr, old, val, 8);
-		} while (oldt != old);
-
-		return old;
-	}
-#endif
-	}
-	__builtin_trap();
-	return 0;
-}
-
-#define uatomic_xchg(addr, v)						    \
-	((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
-						sizeof(*(addr))))
-
-/* uatomic_add_return */
-
-static inline __attribute__((always_inline))
-unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
-{
-	switch (len) {
-	case 4:
-	{
-		unsigned int old, oldt;
-
-		oldt = uatomic_read((unsigned int *)addr);
-		do {
-			old = oldt;
-			oldt = _uatomic_cmpxchg(addr, old, old + val, 4);
-		} while (oldt != old);
-
-		return old + val;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long old, oldt;
-
-		oldt = uatomic_read((unsigned long *)addr);
-		do {
-			old = oldt;
-			oldt = _uatomic_cmpxchg(addr, old, old + val, 8);
-		} while (oldt != old);
-
-		return old + val;
-	}
-#endif
-	}
-	__builtin_trap();
-	return 0;
-}
-
-#define uatomic_add_return(addr, v)					\
-	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
-						  (unsigned long)(v),	\
-						  sizeof(*(addr))))
-
 #ifdef __cplusplus 
 }
 #endif
-- 
1.6.6

[ltt-dev] [PATCH 09/11] move whether atomic byte/short exists to uatomic_arch_*.h

[Paolo Bonzini]

Just a small cleanup that could be used in the future, for example
if i386 was separated from i486+ and x86_64.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 tests/test_uatomic.c    |   13 +-------
 urcu/uatomic_arch_x86.h |    3 ++
 urcu/uatomic_gcc.h      |   72 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 77 insertions(+), 11 deletions(-)

diff --git a/tests/test_uatomic.c b/tests/test_uatomic.c
index c0f36fe..2e04c43 100644
--- a/tests/test_uatomic.c
+++ b/tests/test_uatomic.c
@@ -1,21 +4,10 @@
 #include <stdio.h>
 #include <assert.h>
-
-#define UATOMIC_NO_LINK_ERROR
 #include <urcu/uatomic_arch.h>
 
-#if (defined(__i386__) || defined(__x86_64__))
-#define HAS_ATOMIC_BYTE
-#define HAS_ATOMIC_SHORT
-#endif
-
 struct testvals {
-#ifdef HAS_ATOMIC_BYTE
 	unsigned char c;
-#endif
-#ifdef HAS_ATOMIC_SHORT
 	unsigned short s;
-#endif
 	unsigned int i;
 	unsigned long l;
 };
@@ -54,10 +45,10 @@ do {						\
 
 int main(int argc, char **argv)
 {
-#ifdef HAS_ATOMIC_BYTE
+#ifdef UATOMIC_HAS_ATOMIC_BYTE
 	do_test(&vals.c);
 #endif
-#ifdef HAS_ATOMIC_SHORT
+#ifdef UATOMIC_HAS_ATOMIC_SHORT
 	do_test(&vals.s);
 #endif
 	do_test(&vals.i);
diff --git a/urcu/uatomic_arch_x86.h b/urcu/uatomic_arch_x86.h
index 0aadbd5..aea207e 100644
--- a/urcu/uatomic_arch_x86.h
+++ b/urcu/uatomic_arch_x86.h
@@ -23,6 +23,9 @@
 #include <urcu/compiler.h>
 #include <urcu/system.h>
 
+#define UATOMIC_HAS_ATOMIC_CHAR
+#define UATOMIC_HAS_ATOMIC_SHORT
+
 #ifdef __cplusplus
 extern "C" {
 #endif 
diff --git a/urcu/uatomic_gcc.h b/urcu/uatomic_gcc.h
index 28f6d71..5a4cc40 100644
--- a/urcu/uatomic_gcc.h
+++ b/urcu/uatomic_gcc.h
@@ -64,6 +64,14 @@ unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
 			      unsigned long _new, int len)
 {
 	switch (len) {
+#ifdef UATOMIC_HAS_ATOMIC_CHAR
+	case 1:
+		return __sync_val_compare_and_swap_1(addr, old, _new);
+#endif
+#ifdef UATOMIC_HAS_ATOMIC_SHORT
+	case 2:
+		return __sync_val_compare_and_swap_2(addr, old, _new);
+#endif
 	case 4:
 		return __sync_val_compare_and_swap_4(addr, old, _new);
 #if (BITS_PER_LONG == 64)
@@ -90,6 +98,14 @@ unsigned long _uatomic_add_return(void *addr, unsigned long val,
 				 int len)
 {
 	switch (len) {
+#ifdef UATOMIC_HAS_ATOMIC_CHAR
+	case 1:
+		return __sync_add_and_fetch_1(addr, val);
+#endif
+#ifdef UATOMIC_HAS_ATOMIC_SHORT
+	case 2:
+		return __sync_add_and_fetch_2(addr, val);
+#endif
 	case 4:
 		return __sync_add_and_fetch_4(addr, val);
 #if (BITS_PER_LONG == 64)
@@ -115,6 +131,34 @@ static inline __attribute__((always_inline))
 unsigned long _uatomic_add_return(void *addr, unsigned long val, int len)
 {
 	switch (len) {
+#ifdef UATOMIC_HAS_ATOMIC_CHAR
+	case 1:
+	{
+		unsigned char old, oldt;
+
+		oldt = uatomic_read((unsigned char *)addr);
+		do {
+			old = oldt;
+			oldt = _uatomic_cmpxchg(addr, old, old + val, 1);
+		} while (oldt != old);
+
+		return old + val;
+	}
+#endif
+#ifdef UATOMIC_HAS_ATOMIC_SHORT
+	case 2:
+	{
+		unsigned short old, oldt;
+
+		oldt = uatomic_read((unsigned short *)addr);
+		do {
+			old = oldt;
+			oldt = _uatomic_cmpxchg(addr, old, old + val, 2);
+		} while (oldt != old);
+
+		return old + val;
+	}
+#endif
 	case 4:
 	{
 		unsigned int old, oldt;
@@ -161,6 +205,34 @@ static inline __attribute__((always_inline))
 unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
 {
 	switch (len) {
+#ifdef UATOMIC_HAS_ATOMIC_CHAR
+	case 1:
+	{
+		unsigned char old, oldt;
+
+		oldt = uatomic_read((unsigned char *)addr);
+		do {
+			old = oldt;
+			oldt = _uatomic_cmpxchg(addr, old, val, 1);
+		} while (oldt != old);
+
+		return old;
+	}
+#endif
+#ifdef UATOMIC_HAS_ATOMIC_SHORT
+	case 2:
+	{
+		unsigned short old, oldt;
+
+		oldt = uatomic_read((unsigned short *)addr);
+		do {
+			old = oldt;
+			oldt = _uatomic_cmpxchg(addr, old, val, 2);
+		} while (oldt != old);
+
+		return old;
+	}
+#endif
 	case 4:
 	{
 		unsigned int old, oldt;
-- 
1.6.6

[ltt-dev] [PATCH 10/11] add Alpha support

[Paolo Bonzini]

And you already know what needs to be special-cased for Alpha...

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 configure.ac              |    1 +
 urcu/arch_alpha.h         |   49 +++++++++++++++++++++++++++++++++++++++++++++
 urcu/uatomic_arch_alpha.h |   32 +++++++++++++++++++++++++++++
 3 files changed, 82 insertions(+), 0 deletions(-)
 create mode 100644 urcu/arch_alpha.h
 create mode 100644 urcu/uatomic_arch_alpha.h

diff --git a/configure.ac b/configure.ac
index 5fade2c..a78db70 100644
--- a/configure.ac
+++ b/configure.ac
@@ -50,6 +50,7 @@ case $host_cpu in
 	s390) ARCHTYPE="s390" ;;
 	s390x) ARCHTYPE="s390" ;;
 	sparc64) ARCHTYPE="sparc64" ;;
+	alpha*) ARCHTYPE="alpha" ;;
 	*) ARCHTYPE="unknown";;
 esac
 
diff --git a/urcu/arch_alpha.h b/urcu/arch_alpha.h
new file mode 100644
index 0000000..cabc915
--- /dev/null
+++ b/urcu/arch_alpha.h
@@ -0,0 +1,48 @@
+#ifndef _URCU_ARCH_ALPHA_H
+#define _URCU_ARCH_ALPHA_H
+
+/*
+ * arch_ppc.h: trivial definitions for the Alpha architecture.
+ *
+ * Copyright (c) 2010 Paolo Bonzini <pbonzini at redhat.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+*
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define mb()			asm volatile("mb":::"memory")
+#define wmb()			asm volatile("wmb":::"memory")
+#define read_barrier_depends()	asm volatile("mb":::"memory")
+
+typedef unsigned long long cycles_t;
+
+static inline cycles_t get_cycles (void)
+{
+	return 0;	/* not supported */
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <urcu/arch_defaults.h>
+
+#endif /* _URCU_ARCH_ALPHA_H */
diff --git a/urcu/uatomic_arch_alpha.h b/urcu/uatomic_arch_alpha.h
new file mode 100644
index 0000000..d7c1604
--- /dev/null
+++ b/urcu/uatomic_arch_alpha.h
@@ -0,0 +1,32 @@
+#ifndef _URCU_UATOMIC_ARCH_ALPHA_H
+#define _URCU_UATOMIC_ARCH_ALPHA_H
+
+/*
+ * Atomic exchange operations for the Alpha architecture. Let GCC do it.
+ *
+ * Copyright (c) 2010 Paolo Bonzini <pbonzini at redhat.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/system.h>
+#include <urcu/uatomic_gcc.h>
+
+#endif /* _URCU_UATOMIC_ARCH_ALPHA_H */
-- 
1.6.6

[ltt-dev] [PATCH 11/11] support compiling on unknown architectures

[Paolo Bonzini]

The new defaults mean that, for example, ia64 support comes for free.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 configure.ac |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/configure.ac b/configure.ac
index 4580f38..5fade2c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -53,11 +53,13 @@ case $host_cpu in
 	*) ARCHTYPE="unknown";;
 esac
 
-if test "$ARCHTYPE" = "unknown"; then
-	AC_MSG_ERROR([Unable to detect the architecture.])
+if test "$ARCHTYPE" != "unknown"; then
+	UATOMICSRC=urcu/uatomic_arch_$ARCHTYPE.h
+	ARCHSRC=urcu/arch_$ARCHTYPE.h
+else
+	UATOMICSRC=urcu/uatomic_gcc.h
+	ARCHSRC=urcu/arch_defaults.h
 fi
-UATOMICSRC=urcu/uatomic_arch_$ARCHTYPE.h
-ARCHSRC=urcu/arch_$ARCHTYPE.h
 AC_SUBST(ARCHTYPE)
 AC_SUBST(SUBARCHTYPE)
 
-- 
1.6.6

[ltt-dev] [PATCH 12/11] test uatomic_gcc.h

[Paolo Bonzini]

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/uatomic_arch_x86.h |  446 -----------------------------------------------
 1 files changed, 0 insertions(+), 446 deletions(-)

diff --git a/urcu/uatomic_arch_x86.h b/urcu/uatomic_arch_x86.h
index aea207e..6e21817 100644
--- a/urcu/uatomic_arch_x86.h
+++ b/urcu/uatomic_arch_x86.h
@@ -25,452 +25,6 @@
 
 #define UATOMIC_HAS_ATOMIC_CHAR
 #define UATOMIC_HAS_ATOMIC_SHORT
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
-#endif
-
-/*
- * Derived from AO_compare_and_swap() and AO_test_and_set_full().
- */
-
-struct __uatomic_dummy {
-	unsigned long v[10];
-};
-#define __hp(x)	((struct __uatomic_dummy *)(x))
-
-#define _uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
-
-#if 0
-/* Read is atomic even in compat mode */
-#define _uatomic_read(addr)	LOAD_SHARED(*(addr))
-#endif
-
-/* cmpxchg */
-
-static inline __attribute__((always_inline))
-unsigned long __uatomic_cmpxchg(void *addr, unsigned long old,
-			      unsigned long _new, int len)
-{
-	switch (len) {
-	case 1:
-	{
-		unsigned char result = old;
-
-		__asm__ __volatile__(
-		"lock; cmpxchgb %2, %1"
-			: "+a"(result), "+m"(*__hp(addr))
-			: "q"((unsigned char)_new)
-			: "memory");
-		return result;
-	}
-	case 2:
-	{
-		unsigned short result = old;
-
-		__asm__ __volatile__(
-		"lock; cmpxchgw %2, %1"
-			: "+a"(result), "+m"(*__hp(addr))
-			: "r"((unsigned short)_new)
-			: "memory");
-		return result;
-	}
-	case 4:
-	{
-		unsigned int result = old;
-
-		__asm__ __volatile__(
-		"lock; cmpxchgl %2, %1"
-			: "+a"(result), "+m"(*__hp(addr))
-			: "r"((unsigned int)_new)
-			: "memory");
-		return result;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long result = old;
-
-		__asm__ __volatile__(
-		"lock; cmpxchgq %2, %1"
-			: "+a"(result), "+m"(*__hp(addr))
-			: "r"((unsigned long)_new)
-			: "memory");
-		return result;
-	}
-#endif
-	}
-	/* generate an illegal instruction. Cannot catch this with linker tricks
-	 * when optimizations are disabled. */
-	__asm__ __volatile__("ud2");
-	return 0;
-}
-
-#define _uatomic_cmpxchg(addr, old, _new)				      \
-	((__typeof__(*(addr))) __uatomic_cmpxchg((addr), (unsigned long)(old),\
-						(unsigned long)(_new), 	      \
-						sizeof(*(addr))))
-
-/* xchg */
-
-static inline __attribute__((always_inline))
-unsigned long __uatomic_exchange(void *addr, unsigned long val, int len)
-{
-	/* Note: the "xchg" instruction does not need a "lock" prefix. */
-	switch (len) {
-	case 1:
-	{
-		unsigned char result;
-		__asm__ __volatile__(
-		"xchgb %0, %1"
-			: "=q"(result), "+m"(*__hp(addr))
-			: "0" ((unsigned char)val)
-			: "memory");
-		return result;
-	}
-	case 2:
-	{
-		unsigned short result;
-		__asm__ __volatile__(
-		"xchgw %0, %1"
-			: "=r"(result), "+m"(*__hp(addr))
-			: "0" ((unsigned short)val)
-			: "memory");
-		return result;
-	}
-	case 4:
-	{
-		unsigned int result;
-		__asm__ __volatile__(
-		"xchgl %0, %1"
-			: "=r"(result), "+m"(*__hp(addr))
-			: "0" ((unsigned int)val)
-			: "memory");
-		return result;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long result;
-		__asm__ __volatile__(
-		"xchgq %0, %1"
-			: "=r"(result), "+m"(*__hp(addr))
-			: "0" ((unsigned long)val)
-			: "memory");
-		return result;
-	}
-#endif
-	}
-	/* generate an illegal instruction. Cannot catch this with linker tricks
-	 * when optimizations are disabled. */
-	__asm__ __volatile__("ud2");
-	return 0;
-}
-
-#define _uatomic_xchg(addr, v)						      \
-	((__typeof__(*(addr))) __uatomic_exchange((addr), (unsigned long)(v), \
-						sizeof(*(addr))))
-
-/* uatomic_add_return */
-
-static inline __attribute__((always_inline))
-unsigned long __uatomic_add_return(void *addr, unsigned long val,
-				 int len)
-{
-	switch (len) {
-	case 1:
-	{
-		unsigned char result = val;
-
-		__asm__ __volatile__(
-		"lock; xaddb %1, %0"
-			: "+m"(*__hp(addr)), "+q" (result)
-			:
-			: "memory");
-		return result + (unsigned char)val;
-	}
-	case 2:
-	{
-		unsigned short result = val;
-
-		__asm__ __volatile__(
-		"lock; xaddw %1, %0"
-			: "+m"(*__hp(addr)), "+r" (result)
-			:
-			: "memory");
-		return result + (unsigned short)val;
-	}
-	case 4:
-	{
-		unsigned int result = val;
-
-		__asm__ __volatile__(
-		"lock; xaddl %1, %0"
-			: "+m"(*__hp(addr)), "+r" (result)
-			:
-			: "memory");
-		return result + (unsigned int)val;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		unsigned long result = val;
-
-		__asm__ __volatile__(
-		"lock; xaddq %1, %0"
-			: "+m"(*__hp(addr)), "+r" (result)
-			:
-			: "memory");
-		return result + (unsigned long)val;
-	}
-#endif
-	}
-	/* generate an illegal instruction. Cannot catch this with linker tricks
-	 * when optimizations are disabled. */
-	__asm__ __volatile__("ud2");
-	return 0;
-}
-
-#define _uatomic_add_return(addr, v)					\
-	((__typeof__(*(addr))) __uatomic_add_return((addr),		\
-						  (unsigned long)(v),	\
-						  sizeof(*(addr))))
-
-/* uatomic_add */
-
-static inline __attribute__((always_inline))
-void __uatomic_add(void *addr, unsigned long val, int len)
-{
-	switch (len) {
-	case 1:
-	{
-		__asm__ __volatile__(
-		"lock; addb %1, %0"
-			: "=m"(*__hp(addr))
-			: "iq" ((unsigned char)val)
-			: "memory");
-		return;
-	}
-	case 2:
-	{
-		__asm__ __volatile__(
-		"lock; addw %1, %0"
-			: "=m"(*__hp(addr))
-			: "ir" ((unsigned short)val)
-			: "memory");
-		return;
-	}
-	case 4:
-	{
-		__asm__ __volatile__(
-		"lock; addl %1, %0"
-			: "=m"(*__hp(addr))
-			: "ir" ((unsigned int)val)
-			: "memory");
-		return;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		__asm__ __volatile__(
-		"lock; addq %1, %0"
-			: "=m"(*__hp(addr))
-			: "er" ((unsigned long)val)
-			: "memory");
-		return;
-	}
-#endif
-	}
-	/* generate an illegal instruction. Cannot catch this with linker tricks
-	 * when optimizations are disabled. */
-	__asm__ __volatile__("ud2");
-	return;
-}
-
-#define _uatomic_add(addr, v)						   \
-	(__uatomic_add((addr), (unsigned long)(v), sizeof(*(addr))))
-
-
-/* uatomic_inc */
-
-static inline __attribute__((always_inline))
-void __uatomic_inc(void *addr, int len)
-{
-	switch (len) {
-	case 1:
-	{
-		__asm__ __volatile__(
-		"lock; incb %0"
-			: "=m"(*__hp(addr))
-			:
-			: "memory");
-		return;
-	}
-	case 2:
-	{
-		__asm__ __volatile__(
-		"lock; incw %0"
-			: "=m"(*__hp(addr))
-			:
-			: "memory");
-		return;
-	}
-	case 4:
-	{
-		__asm__ __volatile__(
-		"lock; incl %0"
-			: "=m"(*__hp(addr))
-			:
-			: "memory");
-		return;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		__asm__ __volatile__(
-		"lock; incq %0"
-			: "=m"(*__hp(addr))
-			:
-			: "memory");
-		return;
-	}
-#endif
-	}
-	/* generate an illegal instruction. Cannot catch this with linker tricks
-	 * when optimizations are disabled. */
-	__asm__ __volatile__("ud2");
-	return;
-}
-
-#define _uatomic_inc(addr)	(__uatomic_inc((addr), sizeof(*(addr))))
-
-/* uatomic_dec */
-
-static inline __attribute__((always_inline))
-void __uatomic_dec(void *addr, int len)
-{
-	switch (len) {
-	case 1:
-	{
-		__asm__ __volatile__(
-		"lock; decb %0"
-			: "=m"(*__hp(addr))
-			:
-			: "memory");
-		return;
-	}
-	case 2:
-	{
-		__asm__ __volatile__(
-		"lock; decw %0"
-			: "=m"(*__hp(addr))
-			:
-			: "memory");
-		return;
-	}
-	case 4:
-	{
-		__asm__ __volatile__(
-		"lock; decl %0"
-			: "=m"(*__hp(addr))
-			:
-			: "memory");
-		return;
-	}
-#if (BITS_PER_LONG == 64)
-	case 8:
-	{
-		__asm__ __volatile__(
-		"lock; decq %0"
-			: "=m"(*__hp(addr))
-			:
-			: "memory");
-		return;
-	}
-#endif
-	}
-	/* generate an illegal instruction. Cannot catch this with linker tricks
-	 * when optimizations are disabled. */
-	__asm__ __volatile__("ud2");
-	return;
-}
-
-#define _uatomic_dec(addr)	(__uatomic_dec((addr), sizeof(*(addr))))
-
-#if ((BITS_PER_LONG != 64) && defined(CONFIG_RCU_COMPAT_ARCH))
-extern int __rcu_cas_avail;
-extern int __rcu_cas_init(void);
-
-#define UATOMIC_COMPAT(insn)							\
-	((likely(__rcu_cas_avail > 0))						\
-	? (_uatomic_##insn)							\
-		: ((unlikely(__rcu_cas_avail < 0)				\
-			? ((__rcu_cas_init() > 0)				\
-				? (_uatomic_##insn)				\
-				: (compat_uatomic_##insn))			\
-			: (compat_uatomic_##insn))))
-
-extern unsigned long _compat_uatomic_set(void *addr,
-					 unsigned long _new, int len);
-#define compat_uatomic_set(addr, _new)				     	       \
-	((__typeof__(*(addr))) _compat_uatomic_set((addr),		       \
-						(unsigned long)(_new), 	       \
-						sizeof(*(addr))))
-
-
-extern unsigned long _compat_uatomic_xchg(void *addr,
-					  unsigned long _new, int len);
-#define compat_uatomic_xchg(addr, _new)					       \
-	((__typeof__(*(addr))) _compat_uatomic_xchg((addr),		       \
-						(unsigned long)(_new), 	       \
-						sizeof(*(addr))))
-
-extern unsigned long _compat_uatomic_cmpxchg(void *addr, unsigned long old,
-					     unsigned long _new, int len);
-#define compat_uatomic_cmpxchg(addr, old, _new)				       \
-	((__typeof__(*(addr))) _compat_uatomic_cmpxchg((addr),		       \
-						(unsigned long)(old),	       \
-						(unsigned long)(_new), 	       \
-						sizeof(*(addr))))
-
-extern unsigned long _compat_uatomic_xchg(void *addr,
-					  unsigned long _new, int len);
-#define compat_uatomic_add_return(addr, v)				       \
-	((__typeof__(*(addr))) _compat_uatomic_add_return((addr),	       \
-						(unsigned long)(v), 	       \
-						sizeof(*(addr))))
-
-#define compat_uatomic_add(addr, v)					       \
-		((void)compat_uatomic_add_return((addr), (v)))
-#define compat_uatomic_inc(addr)					       \
-		(compat_uatomic_add((addr), 1))
-#define compat_uatomic_dec(addr)					       \
-		(compat_uatomic_add((addr), -1))
-
-#else
-#define UATOMIC_COMPAT(insn)	(_uatomic_##insn)
-#endif
-
-#define uatomic_set(addr, v)			\
-		UATOMIC_COMPAT(set(addr, v))
-#define uatomic_cmpxchg(addr, old, _new)	\
-		UATOMIC_COMPAT(cmpxchg(addr, old, _new))
-#define uatomic_xchg(addr, v)			\
-		UATOMIC_COMPAT(xchg(addr, v))
-#define uatomic_add_return(addr, v)		\
-		UATOMIC_COMPAT(add_return(addr, v))
-#define uatomic_add(addr, v)	UATOMIC_COMPAT(add(addr, v))
-#define uatomic_inc(addr)	UATOMIC_COMPAT(inc(addr))
-#define uatomic_dec(addr)	UATOMIC_COMPAT(dec(addr))
-
-#ifdef __cplusplus 
-}
-#endif
-
 #include <urcu/uatomic_gcc.h>
 
 #endif /* _URCU_ARCH_UATOMIC_X86_H */
-- 
1.6.6

[ltt-dev] [PATCH 00/11] Simplify system dependent URCU code

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> This patch series simplifies the system dependent code in the
> userspace RCU library by removing redundant definitions and
> moving them to common code.  The common code is then less
> subject to bitrotting because it can be tested on x86 too.

Hi Paolo,

I like the patchset in general. I have a few comments though. Once
addressed, please re-send the whole patchset, as there may be
dependencies between the individual patches.

I'll reply to the individual patches with comments.

Mathieu

> 
> 
> Patches 3 and 4 take care of urcu/arch_*.  Definitions for
> rmb/wmb/mc/rmc/wmc can often be omitted, and even mb can
> for example defer to the compiler-provided __sync_synchronize.
> 
> Patch 5 removes a redundant definition that is probably
> a residual of libatomicops, and so does patch 6.
> 
> Patches 7 to 9 take care of urcu/uatomic_arch_*, by defining
> fallbacks using __sync_* builtins.  S390 can use them completely
> without basically changing the generated code, while other
> architectures still require a little help.
> 
> Patches 10 and 11 show how this helps by supporting
> compilation to unknown architectures that support GCC
> builtins (MIPS and IA64 are serviced nicely for example),
> and by supporting Alpha (obviously chosen as an example of
> read_barrier_depends) with ~20 lines of non-comment code.
> 
> Patch 12 is not meant to be committed, but was used to test
> the atomic op implementations on x86_64.  It is not counted
> in the diffstat below.
> 
> HTH,
> 
> Paolo
> 
> Paolo Bonzini (11+1):
>   use kernel style makefile output
>   use autoconf symbolic linking
>   add urcu/arch_defaults.h
>   define sync_core for x86 PIC
>   __SIZEOF_LONG__ is always defined by GCC
>   remove compat_uatomic_cmpxchg #define from non-x86
>   add uatomic_gcc.h, use it for default definitions
>   use uatomic_gcc.h
>   move whether atomic byte/short exists to uatomic_arch_*.h
>   add Alpha support
>   support compiling on unknown architectures
>   test uatomic_gcc.h
> 
>  Makefile.am                 |   14 +-
>  configure.ac                |   15 ++-
>  tests/test_uatomic.c        |   15 +-
>  urcu/arch_alpha.h           |   49 +++++
>  urcu/arch_defaults.h        |  109 ++++++++++
>  urcu/arch_ppc.h             |   50 +-----
>  urcu/arch_s390.h            |   46 +----
>  urcu/arch_sparc64.h         |   51 +-----
>  urcu/arch_x86.h             |   68 +------
>  urcu/uatomic_arch_alpha.h   |   32 +++
>  urcu/uatomic_arch_ppc.h     |  143 +-------------
>  urcu/uatomic_arch_s390.h    |  193 +------------------
>  urcu/uatomic_arch_sparc64.h |  109 +----------
>  urcu/uatomic_arch_x86.h     |   37 ++----
>  urcu/uatomic_gcc.h          |  293 +++++++++++++++++++++++++++++++++++++++++++
>  15 files changed, 538 insertions(+), 686 deletions(-)
>  create mode 100644 urcu/arch_alpha.h
>  create mode 100644 urcu/arch_defaults.h
>  create mode 100644 urcu/uatomic_arch_alpha.h
>  create mode 100644 urcu/uatomic_gcc.h
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68