[ltt-dev] [patch 0/9] LTTng for ARM OMAP3 (v2)

[ltt-dev] [patch 0/9] LTTng for ARM OMAP3 (v2)

[Mathieu Desnoyers]

Hello,

I decided to add better privitives to eventually support PM sleep in idle.
Please see

omap-trace-clock-add-write-trace-clock.patch
omap-trace-clock-basic-pm-fix.patch

At the end of the patchset. Basically, it resynchronizes the whole trace-clock,
not just the cycle counter. This will be needed for proper PM support.

Mathieu

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [patch 1/9] omap lttng instrumentation kernel fix

[Mathieu Desnoyers]

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[ltt-dev] [patch 1/9] omap lttng instrumentation kernel fix

[Mathieu Desnoyers]

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[ltt-dev] [patch 2/9] LTTng - ARM instrumentation

[Mathieu Desnoyers]

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[ltt-dev] [patch 2/9] LTTng - ARM instrumentation

[Mathieu Desnoyers]

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[ltt-dev] [patch 3/9] OMAP ltt statedump include irq.h

[Mathieu Desnoyers]

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[ltt-dev] [patch 3/9] OMAP ltt statedump include irq.h

[Mathieu Desnoyers]

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[ltt-dev] [patch 4/9] omap lttng use iter div

[Mathieu Desnoyers]

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[ltt-dev] [patch 4/9] omap lttng use iter div

[Mathieu Desnoyers]

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[ltt-dev] [patch 5/9] omap lttng statedump arm

[Mathieu Desnoyers]

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[ltt-dev] [patch 5/9] omap lttng statedump arm

[Mathieu Desnoyers]

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[ltt-dev] [patch 6/9] omap trace clock specialize

[Mathieu Desnoyers]

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[ltt-dev] [patch 6/9] omap trace clock specialize

[Mathieu Desnoyers]

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[ltt-dev] [patch 7/9] omap trace clock

[Mathieu Desnoyers]

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[ltt-dev] [patch 7/9] omap trace clock

[Mathieu Desnoyers]

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[ltt-dev] [patch 7/9] omap trace clock

[Trilok Soni]

Hi Mathieu,

> +
> +/*
> + * Cycle counter management.
> + */
> +
> +static inline void write_pmnc(u32 val)
> +{
> + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
> +}
> +
> +static inline u32 read_pmnc(void)
> +{
> + ? ? ? u32 val;
> + ? ? ? __asm__ __volatile__ ("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
> + ? ? ? ?return val;
> +}
> +
> +static inline void write_ctens(u32 val)
> +{
> + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
> +}
> +
> +static inline u32 read_ctens(void)
> +{
> + ? ? ? u32 val;
> + ? ? ? __asm__ __volatile__ ("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
> + ? ? ? return val;
> +}
> +
> +static inline void write_intenc(u32 val)
> +{
> + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
> +}
> +
> +static inline u32 read_intenc(void)
> +{
> + ? ? ? u32 val;
> + ? ? ? ?__asm__ __volatile__ ("mrc p15, 0, %0, c9, c14, 2" : "=r" (val));
> + ? ? ? return val;
> +}
> +
> +static inline void write_useren(u32 val)
> +{
> + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c14, 0" : : "r" (val));
> +}
> +
> +static inline u32 read_useren(void)
> +{
> + ? ? ? u32 val;
> + ? ? ? ?__asm__ __volatile__ ("mrc p15, 0, %0, c9, c14, 0" : "=r" (val));
> + ? ? ? return val;
> +}
> +
> +/*
> + * Must disable counter before writing to it.
> + */
> +static inline void write_ccnt(u32 val)
> +{
> + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
> +}

Isn't is some of this cycle counter management code remain same for
any cortext-A8 based SoC. I mean this doesn't seem to be specific to
OMAP3 but to cortex-a8 it seems.



-- 
---Trilok Soni
http://triloksoni.wordpress.com
http://www.linkedin.com/in/triloksoni

[ltt-dev] [patch 7/9] omap trace clock

[Mathieu Desnoyers]

* Trilok Soni (soni.trilok at gmail.com) wrote:
> Hi Mathieu,
> 
> > +
> > +/*
> > + * Cycle counter management.
> > + */
> > +
> > +static inline void write_pmnc(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
> > +}
> > +
> > +static inline u32 read_pmnc(void)
> > +{
> > + ? ? ? u32 val;
> > + ? ? ? __asm__ __volatile__ ("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
> > + ? ? ? ?return val;
> > +}
> > +
> > +static inline void write_ctens(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
> > +}
> > +
> > +static inline u32 read_ctens(void)
> > +{
> > + ? ? ? u32 val;
> > + ? ? ? __asm__ __volatile__ ("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
> > + ? ? ? return val;
> > +}
> > +
> > +static inline void write_intenc(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
> > +}
> > +
> > +static inline u32 read_intenc(void)
> > +{
> > + ? ? ? u32 val;
> > + ? ? ? ?__asm__ __volatile__ ("mrc p15, 0, %0, c9, c14, 2" : "=r" (val));
> > + ? ? ? return val;
> > +}
> > +
> > +static inline void write_useren(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c14, 0" : : "r" (val));
> > +}
> > +
> > +static inline u32 read_useren(void)
> > +{
> > + ? ? ? u32 val;
> > + ? ? ? ?__asm__ __volatile__ ("mrc p15, 0, %0, c9, c14, 0" : "=r" (val));
> > + ? ? ? return val;
> > +}
> > +
> > +/*
> > + * Must disable counter before writing to it.
> > + */
> > +static inline void write_ccnt(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
> > +}
> 
> Isn't is some of this cycle counter management code remain same for
> any cortext-A8 based SoC. I mean this doesn't seem to be specific to
> OMAP3 but to cortex-a8 it seems.
> 

Yes, given the understanding I have of the overall ARM world, I stayed
conservative in what headers files I touched and the configuration
options that I used. If you have hints about locations for .c and .h
files and about the configuration options, I would be glad to hear them.

Thanks !

Mathieu

> 
> 
> -- 
> ---Trilok Soni
> http://triloksoni.wordpress.com
> http://www.linkedin.com/in/triloksoni
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

[ltt-dev] [patch 8/9] omap trace clock add write value

[Mathieu Desnoyers]

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[ltt-dev] [patch 8/9] omap trace clock add write value

[Mathieu Desnoyers]

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[ltt-dev] [patch 9/9] --- arch/arm/mach-omap2/trace-clock.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)

[Mathieu Desnoyers]

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[ltt-dev] [patch 9/9] --- arch/arm/mach-omap2/trace-clock.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)

[Mathieu Desnoyers]

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[ltt-dev] [patch 9/9] OMAP trace clock basic PM fix

[Mathieu Desnoyers]

(With a proper header)

This patch sets the whole trace clock when resynchronising with the 32k timer.
Just setting the cycle counter is not enough, because we would lose bits for
long sleeps.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers at polymtl.ca>
---
 arch/arm/mach-omap2/trace-clock.c |   18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

Index: linux-omap-2.6/arch/arm/mach-omap2/trace-clock.c
===================================================================
--- linux-omap-2.6.orig/arch/arm/mach-omap2/trace-clock.c	2009-02-18 21:17:24.000000000 +0000
+++ linux-omap-2.6/arch/arm/mach-omap2/trace-clock.c	2009-02-18 21:18:04.000000000 +0000
@@ -16,6 +16,10 @@
 /* Need direct access to the clock from kernel/time/timekeeping.c */
 extern struct clocksource *clock;
 
+/* 32KHz counter count save upon PM sleep */
+static u32 saved_32k_count;
+static u64 saved_trace_clock;
+
 static void clear_ccnt_ms(unsigned long data);
 
 static DEFINE_TIMER(clear_ccnt_ms_timer, clear_ccnt_ms, 0, 0);
@@ -139,13 +143,21 @@
 	/*
 	 * Set the timer's value MSBs to the same as current 32K timer.
 	 */
+	ref_time = saved_trace_clock;
 	local_irq_save(flags);
 	count_32k = clocksource_read(clock);
-	ref_time = (u64)count_32k * (cpu_hz >> TIMER_32K_SHIFT);
+	/*
+	 * Delta done on 32-bits, then casted to u64. Must guarantee
+	 * that we are called often enough so the difference does not
+	 * overflow 32 bits anyway.
+	 */
+	ref_time += (u64)(count_32k - saved_32k_count)
+			* (cpu_hz >> TIMER_32K_SHIFT);
 	write_ctens(read_ctens() & ~(1 << 31));	/* disable counter */
-	write_ccnt((u32)ref_time);
+	write_ccnt((u32)ref_time & ~(1 << 31));
 	write_ctens(read_ctens() |  (1 << 31));	/* enable counter */
 	count_trace_clock = trace_clock_read32();
+	_trace_clock_write_synthetic_tsc(ref_time);
 	local_irq_restore(flags);
 
 	get_synthetic_tsc();
@@ -160,6 +172,8 @@
 
 void _stop_trace_clock(void)
 {
+	saved_32k_count = clocksource_read(clock);
+	saved_trace_clock = trace_clock_read64();
 	del_timer_sync(&clear_ccnt_ms_timer);
 	put_synthetic_tsc();
 }

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68