From mboxrd@z Thu Jan  1 00:00:00 1970
From: mathieu.desnoyers@polymtl.ca (Mathieu Desnoyers)
Date: Fri, 6 Mar 2009 13:02:42 -0500
Subject: [ltt-dev] [patch 7/9] omap trace clock
In-Reply-To: <5d5443650903052233u25e63e07x725169a74141f45f@mail.gmail.com>
References: <20090219030213.010652037@polymtl.ca>
	<20090219030504.083768548@polymtl.ca>
	<5d5443650903052233u25e63e07x725169a74141f45f@mail.gmail.com>
Message-ID: <20090306180241.GA14236@Krystal>

* Trilok Soni (soni.trilok at gmail.com) wrote:
> Hi Mathieu,
> 
> > +
> > +/*
> > + * Cycle counter management.
> > + */
> > +
> > +static inline void write_pmnc(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
> > +}
> > +
> > +static inline u32 read_pmnc(void)
> > +{
> > + ? ? ? u32 val;
> > + ? ? ? __asm__ __volatile__ ("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
> > + ? ? ? ?return val;
> > +}
> > +
> > +static inline void write_ctens(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
> > +}
> > +
> > +static inline u32 read_ctens(void)
> > +{
> > + ? ? ? u32 val;
> > + ? ? ? __asm__ __volatile__ ("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
> > + ? ? ? return val;
> > +}
> > +
> > +static inline void write_intenc(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
> > +}
> > +
> > +static inline u32 read_intenc(void)
> > +{
> > + ? ? ? u32 val;
> > + ? ? ? ?__asm__ __volatile__ ("mrc p15, 0, %0, c9, c14, 2" : "=r" (val));
> > + ? ? ? return val;
> > +}
> > +
> > +static inline void write_useren(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c14, 0" : : "r" (val));
> > +}
> > +
> > +static inline u32 read_useren(void)
> > +{
> > + ? ? ? u32 val;
> > + ? ? ? ?__asm__ __volatile__ ("mrc p15, 0, %0, c9, c14, 0" : "=r" (val));
> > + ? ? ? return val;
> > +}
> > +
> > +/*
> > + * Must disable counter before writing to it.
> > + */
> > +static inline void write_ccnt(u32 val)
> > +{
> > + ? ? ? __asm__ __volatile__ ("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
> > +}
> 
> Isn't is some of this cycle counter management code remain same for
> any cortext-A8 based SoC. I mean this doesn't seem to be specific to
> OMAP3 but to cortex-a8 it seems.
> 

Yes, given the understanding I have of the overall ARM world, I stayed
conservative in what headers files I touched and the configuration
options that I used. If you have hints about locations for .c and .h
files and about the configuration options, I would be glad to hear them.

Thanks !

Mathieu

> 
> 
> -- 
> ---Trilok Soni
> http://triloksoni.wordpress.com
> http://www.linkedin.com/in/triloksoni
> 

-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68