* AM33/2.0 support for mn10300-elf
@ 2003-07-10 3:10 Alexandre Oliva
2003-07-10 3:31 ` Alexandre Oliva
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Alexandre Oliva @ 2003-07-10 3:10 UTC (permalink / raw)
To: gdb-patches
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This patch introduces support for AM33/2.0, that adds a
single-precision floating-point unit to AM33. The GCC and binutils
corresponding patches are already in the corresponding CVS trees;
newlib has just been posted for review. Ok to install?
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Index: sim/mn10300/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2000-08-07 Graham Stott <grahams@cygnus.co.uk>
* am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo.
2000-05-29 Alexandre Oliva <aoliva@cygnus.com>
* interp.c (fpu_disabled_exception, fpu_unimp_exception,
fpu_check_signal_exception): Take additional state arguments.
Print exception type and call program_interrupt. Adjust callers.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional
arguments.
* mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception,
fpu_check_signal_exception): Adjust prototypes.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise.
* am33-2.igen: Adjust calls.
2000-05-19 Alexandre Oliva <aoliva@cygnus.com>
* op_utils.c (cmp2fcc): Moved...
* interp.c: ... here.
2000-05-18 Alexandre Oliva <aoliva@cygnus.com>
* am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or
`signed64' where type width is relevant.
2000-05-15 Alexandre Oliva <aoliva@cygnus.com>
* mn10300_sim.h: Include sim-fpu.h.
(FD2FPU, FPU2FD): Enclose the FD argument in parentheses.
(fpu_check_signal_exception): Declare.
(struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise.
(FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare.
* interp.c (fpu_disabled_exception): Document.
(fpu_unimp_exception): Likewise.
(fpu_check_signal_exception): Define.
(reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise.
(reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise.
(REG2VAL, ROUND, VAL2REG): Define shorthands.
(fpu_status_ok): Define.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define.
* am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv,
fmadd, fmsub, fnmadd, fnmsub): Use new functions.
2000-04-27 Alexandre Oliva <aoliva@cygnus.com>
* interp.c (sim_create_inferior): Set PSW bit to enable FP insns
if architecture is AM33/2.0.
* am33.igen: Include am33-2.igen.
2000-04-23 Alexandre Oliva <aoliva@cygnus.com>
* mn10300.igen (movm, call, ret, retf): Check for am33_2 too.
* am33.igen (movm): Likewise.
2000-04-19 Alexandre Oliva <aoliva@cygnus.com>
* am33.igen: Added `*am33_2' to some instructions that were
missing it.
2000-04-07 Alexandre Oliva <aoliva@cygnus.com>
* am33-2.igen: New file. All insns implemented, but FP flags are
only set for fcmp, exceptional conditions are not handled yet.
* Makefile.in (IGEN_INSN): Added am33-2.igen.
(tmp-igen): Added -M am33_2.
* mn10300.igen, am33.igen: Added `*am33_2' to all insns.
* gencode.c: Support FMT_D3.
* mn10300_sim.h (dword): New type.
(struct _state): Added fpregs.
(REG_FPCR, FPCR): New define. All assorted bitmaps.
(XS2FS, AS2FS, Xf2FD): New macros.
(FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise.
(load_dword, store_dword): New functions or macros.
(u642dw, dw2u64): New functions.
(fpu_disabled_exception, fpu_unimp_exception): Declared.
* interp.c (fpu_disabled_exception): Defined; no actual
implementation.
(fpu_unimp_exception): Likewise.
* op_utils.c (cmp2fcc): New function.
Index: sim/mn10300/Makefile.in
===================================================================
RCS file: /cvs/uberbaum/sim/mn10300/Makefile.in,v
retrieving revision 1.6
diff -u -p -r1.6 Makefile.in
--- sim/mn10300/Makefile.in 28 Nov 2002 18:08:26 -0000 1.6
+++ sim/mn10300/Makefile.in 9 Jul 2003 22:55:34 -0000
@@ -108,7 +108,7 @@ clean-igen:
cd ../igen && $(MAKE)
IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
-IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen
+IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen $(srcdir)/am33-2.igen
IGEN_DC=$(srcdir)/mn10300.dc
tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
cd ../igen && $(MAKE)
@@ -116,6 +116,7 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../ige
$(IGEN_TRACE) \
-G gen-direct-access \
-M mn10300,am33 -G gen-multi-sim=am33 \
+ -M am33_2 \
-I $(srcdir) \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
Index: sim/mn10300/am33-2.igen
===================================================================
RCS file: sim/mn10300/am33-2.igen
diff -N sim/mn10300/am33-2.igen
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sim/mn10300/am33-2.igen 9 Jul 2003 22:55:35 -0000
@@ -0,0 +1,2285 @@
+// data cache pre-fetch:
+
+// 1111 1001 1010 0110 Rm.. 0000; dcpf (Rm)
+8.0xf9+8.0xa6+4.RN2,4.0000:D1a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+ load_word (State.regs[srcreg]);
+}
+
+// 1111 1001 1010 0111 0000 0000; dcpf (sp)
+8.0xf9+8.0xa7+8.0x00:D1b:::dcpf
+"dcpf"
+*am33_2
+{
+ PC = cia;
+
+ load_word (SP);
+}
+
+// 1111 1011 1010 0110 Ri.. Rm.. 0000 0000; dcpf (Ri,Rm)
+8.0xfb+8.0xa6+4.RN2,4.RN0+8.0x00:D2a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srci, srcm;
+
+ PC = cia;
+
+ srci = translate_rreg (SD_, RN2);
+ srcm = translate_rreg (SD_, RN0);
+
+ load_word (State.regs[srci] + State.regs[srcm]);
+}
+
+// 1111 1011 1010 0111 Rm.. 0000 IMM8; dcpf (d8,Rm)
+8.0xfb+8.0xa7+4.RN2,4.0000+8.IMM8:D2b:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
+8.0xfd+8.0xa7+4.RN2,4.0000+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg] + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1110 0100 0110 Rm.. 0000 IMM32; dcpf (d32,Rm)
+8.0xfe+8.0x46+4.RN2,4.0000+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// bit operations with imm8,(abs16) addressing mode:
+
+// 1111 1110 1000 0010 ABS16 IMM8; btst imm8,(abs16)
+8.0xfe+8.0x82+8.IMM16A+8.IMM16B+8.IMM8:D3:::btst
+"btst"
+*am33_2
+{
+ PC = cia;
+ genericBtst (IMM8, FETCH16 (IMM16A, IMM16B));
+}
+
+// 1111 1110 1000 0000 ABS16 IMM8; bset imm8,(abs16)
+8.0xfe+8.0x80+8.IMM16A+8.IMM16B+8.IMM8:D3:::bset
+"bset"
+*am33_2
+{
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH16 (IMM16A, IMM16B));
+ z = (temp & IMM8) == 0;
+ temp |= IMM8;
+ store_byte (FETCH16 (IMM16A, IMM16B), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+// 1111 1110 1000 0001 ABS16 IMM8; bclr imm8,(abs16)
+8.0xfe+8.0x81+8.IMM16A+8.IMM16B+8.IMM8:D3:::bclr
+"bclr"
+*am33_2
+{
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH16 (IMM16A, IMM16B));
+ z = (temp & IMM8) == 0;
+ temp = temp & ~(IMM8);
+ store_byte (FETCH16 (IMM16A, IMM16B), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+// single precision fmov:
+
+// 1111 1001 0010 000X Rm.. Sn..; fmov (Rm),FSn
+8.0xf9+4.2,3.0,1.X+4.Rm,4.Sn:D1a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ }
+}
+
+// 1111 1001 0010 001X Rm.. Sn..; fmov (Rm+),FSn
+8.0xf9+4.2,3.1,1.X+4.Rm,4.Sn:D1b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1001 0010 010X ---- Sn..; fmov (SP),FSn
+8.0xf9+4.2,3.2,1.X+4.0,4.Sn:D1c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ }
+}
+
+// 1111 1001 0010 011X Rm.. Sn..; fmov Rm,FSn
+8.0xf9+4.2,3.3,1.X+4.Rm,4.Sn:D1d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = State.regs[reg];
+ }
+}
+
+// 1111 1001 0011 00Y0 Sm.. Rn..; fmov FSm,(Rn)
+8.0xf9+4.3,2.0,1.Y,1.0+4.Sm,4.Rn:D1e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ }
+}
+
+// 1111 1001 0011 00Y1 Sm.. Rn..; fmov FSm,(Rn+)
+8.0xf9+4.3,2.0,1.Y,1.1+4.Sm,4.Rn:D1f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1001 0011 01Y0 Sm.. ----; fmov FSm,(SP)
+8.0xf9+4.3,2.1,1.Y,1.0+4.Sm,4.0:D1g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ }
+}
+
+// 1111 1001 0011 01Y1 Sm.. Rn..; fmov FSm,Rn
+8.0xf9+4.3,2.1,1.Y,1.1+4.Sm,4.Rn:D1h:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ State.regs[reg] = XS2FS (Y,Sm);
+ }
+}
+
+// 1111 1001 0100 00YX Sm.. Sn..; fmov FSm,FSn
+8.0xf9+4.4,2.0,1.Y,1.X+4.Sm,4.Sn:D1i:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ XS2FS (X,Sn) = XS2FS (Y,Sm);
+}
+
+// 1111 1011 0010 000X Rm.. Sn.. d8; fmov (d8,Rm),FSn
+8.0xfb+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM8:D2a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+ }
+}
+
+// 1111 1011 0010 001X Rm.. Sn.. d8; fmov (Rm+,imm8),FSn
+8.0xfb+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM8:D2b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1011 0010 010X ---- Sn.. d8; fmov (d8,SP),FSn
+8.0xfb+4.2,3.2,1.X+4.0,4.Sn+8.IMM8:D2c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg] + IMM8);
+ }
+}
+
+// 1111 1011 0010 0111 Ri.. Rm.. Sn.. --Z-; fmov (Ri,Rm),FSn
+8.0xfb+8.0x27+4.Ri,4.Rm+4.Sn,2.0,1.Z,1.0:D2d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ XS2FS (Z, Sn) = load_word (State.regs[ri] + State.regs[rm]);
+ }
+}
+
+// 1111 1011 0011 00Y0 Sm.. Rn.. d8; fmov FSm,(d8,Rn)
+8.0xfb+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM8:D2e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1011 0011 00Y1 Sm.. Rn.. d8; fmov FSm,(Rn+,d8)
+8.0xfb+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM8:D2f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1011 0011 01Y0 Sm.. ---- d8; fmov FSm,(d8,SP)
+8.0xfb+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM8:D2g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg] + IMM8, XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1011 0011 0111 Ri.. Rm.. Sm.. --Z-; fmov FSm,(Ri,Rm)
+8.0xfb+8.0x37+4.Ri,4.Rm+4.Sm,2.0,1.Z,1.0:D2h:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ store_word (State.regs[ri] + State.regs[rm], XS2FS (Z, Sm));
+ }
+}
+
+// 1111 1101 0010 000X Rm.. Sn.. d24; fmov (d24,Rm),FSn
+8.0xfd+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ }
+}
+
+// 1111 1101 0010 001X Rm.. Sn.. d24; fmov (Rm+,imm24),FSn
+8.0xfd+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1101 0010 010X ---- Sn.. d24; fmov (d24,SP),FSn
+8.0xfd+4.2,3.2,1.X+4.0,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg] + FETCH24 (IMM24A,
+ IMM24B, IMM24C));
+ }
+}
+
+// 1111 1101 0011 00Y0 Sm.. Rn.. d24; fmov FSm,(d24,Rn)
+8.0xfd+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1101 0011 00Y1 Sm.. Rn.. d24; fmov FSm,(Rn+,d24)
+8.0xfd+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1101 0011 01Y0 Sm.. ---- d24; fmov FSm,(d24,SP)
+8.0xfd+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg]
+ + FETCH24 (IMM24A,
+ IMM24B, IMM24C), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1110 0010 000X Rm.. Sn.. d32; fmov (d32,Rm),FSn
+8.0xfe+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ }
+}
+
+// 1111 1110 0010 001X Rm.. Sn.. d32; fmov (Rm+,imm32),FSn
+8.0xfe+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1110 0010 010X ---- Sn.. d32; fmov (d32,SP),FSn
+8.0xfe+4.2,3.2,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D));
+ }
+}
+
+// 1111 1110 0010 011X ---- Sn.. d32; fmov imm32,FSn
+8.0xfe+4.2,3.3,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ XS2FS (X, Sn) = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0011 00Y0 Sm.. Rn.. d32; fmov FSm,(d32,Rn)
+8.0xfe+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1110 0011 00Y1 Sm.. Rn.. d32; fmov FSm,(Rn+,d32)
+8.0xfe+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1110 0011 01Y0 Sm.. ---- d32; fmov FSm,(d32,SP)
+8.0xfe+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D), XS2FS (Y, Sm));
+ }
+}
+
+// double precision fmov:
+
+// 1111 1001 1010 000X Rm.. fn.-; fmov (Rm),FDn
+8.0xf9+4.0xa,3.0,1.X+4.Rm,3.fn,1.0:D1j:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ }
+}
+
+// 1111 1001 1010 001X Rm.. fn.-; fmov (Rm+),FDn
+8.0xf9+4.0xa,3.1,1.X+4.Rm,3.fn,1.0:D1k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1001 1010 010X ---- fn.-; fmov (SP),FDn
+8.0xf9+4.0xa,3.2,1.X+4.0,3.fn,1.0:D1l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ }
+}
+
+// 1111 1001 1011 00Y0 fm.- Rn..; fmov FDm,(Rn)
+8.0xf9+4.0xb,2.0,1.Y,1.0+3.fm,1.0,4.Rn:D1m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ }
+}
+
+// 1111 1001 1011 00Y1 fm.- Rn..; fmov FDm,(Rn+)
+8.0xf9+4.0xb,2.0,1.Y,1.1+3.fm,1.0,4.Rn:D1n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1001 1011 01Y0 fm.- ----; fmov FDm,(SP)
+8.0xf9+4.0xb,2.1,1.Y,1.0+3.fm,1.0,4.0:D1o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ }
+}
+
+// 1111 1001 1100 00YX fm.- fn.-; fmov FDm,FDn
+8.0xf9+4.0xc,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0111 Ri.. Rm.. fn.- --Z-; fmov (Ri,Rm),FDn
+8.0xfb+8.0x47+4.Ri,4.Rm+3.fn,1.0,2.0,1.Z,1.0:D2i:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ Xf2FD (Z,fn) = load_dword (State.regs[ri] + State.regs[rm]);
+ }
+}
+
+// 1111 1011 0101 0111 Ri.. Rn.. fm.- --Z-; fmov FDm,(Ri,Rn)
+8.0xfb+8.0x57+4.Ri,4.Rn+3.fm,1.0,2.0,1.Z,1.0:D2j:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rn = translate_rreg (SD_, Rn);
+ store_dword (State.regs[ri] + State.regs[rn], Xf2FD (Z,fm));
+ }
+}
+
+// 1111 1011 1010 000X Rm.. fn.- d8; fmov (d8,Rm),FDn
+8.0xfb+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM8:D2k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+ }
+}
+
+// 1111 1011 1010 001X Rm.. fn.- d8; fmov (Rm+,imm8),FDn
+8.0xfb+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM8:D2l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1011 1010 010X ---- fn.- d8; fmov (d8,SP),FDn
+8.0xfb+4.0xa,3.2,1.X+4.0,4.fn+8.IMM8:D2m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + IMM8);
+ }
+}
+
+// 1111 1011 1011 00Y0 fm.- Rn.. d8; fmov FDm,(d8,Rn)
+8.0xfb+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM8:D2n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1011 1011 00Y1 fm.- Rn.. d8; fmov FDm,(Rn+,d8)
+8.0xfb+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM8:D2o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1011 1011 01Y0 fm.- ---- d8; fmov FDm,(d8,SP)
+8.0xfb+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM8:D2p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg] + IMM8, Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1101 1010 000X Rm.. fn.- d24; fmov (d24,Rm),FDn
+8.0xfd+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ }
+}
+
+// 1111 1101 1010 001X Rm.. fn.- d24; fmov (Rm+,imm24),FDn
+8.0xfd+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1101 1010 010X ---- fn.- d24; fmov (d24,SP),FDn
+8.0xfd+4.0xa,3.2,1.X+4.0,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + FETCH24 (IMM24A,
+ IMM24B, IMM24C));
+ }
+}
+
+// 1111 1101 1011 00Y0 fm.- Rn.. d24; fmov FDm,(d24,Rn)
+8.0xfd+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1101 1011 00Y1 fm.- Rn.. d24; fmov FDm,(Rn+,d24)
+8.0xfd+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1101 1011 01Y0 fm.- ---- d24; fmov FDm,(d24,SP)
+8.0xfd+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg] + FETCH24 (IMM24A,
+ IMM24B, IMM24C), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1110 1010 000X Rm.. fn.- d32; fmov (d32,Rm),FDn
+8.0xfe+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ }
+}
+
+// 1111 1110 1010 001X Rm.. fn.- d32; fmov (Rm+,imm32),FDn
+8.0xfe+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1110 1010 010X ---- fn.- d32; fmov (d32,SP),FDn
+8.0xfe+4.0xa,3.2,1.X+4.0,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D));
+ }
+}
+
+// 1111 1110 1011 00Y0 fm.- Rn.. d32; fmov FDm,(d32,Rn)
+8.0xfe+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1110 1011 00Y1 fm.- Rn.. d32; fmov FDm,(Rn+,d32)
+8.0xfe+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1110 1011 01Y0 fm.- ---- d32; fmov FDm,(d32,SP)
+8.0xfe+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D), Xf2FD (Y, fm));
+ }
+}
+
+// FPCR fmov:
+
+// 1111 1001 1011 0101 Rm.. ----; fmov Rm,FPCR
+8.0xf9+8.0xb5+4.Rm,4.0:D1q:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ unsigned32 val = State.regs[reg];
+ FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+ | ((FPCR & ~val) & EF_MASK);
+ }
+}
+
+// 1111 1001 1011 0111 ---- Rn..; fmov FPCR,Rn
+8.0xf9+8.0xb7+4.0,4.Rn:D1r:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ State.regs[reg] = FPCR & FPCR_MASK;
+ }
+}
+
+// 1111 1101 1011 0101 imm32; fmov imm32,FPCR
+8.0xfd+8.0xb5+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+ | ((FPCR & ~val) & EF_MASK);
+ }
+}
+
+// fabs:
+
+// 1111 1001 0100 010X ---- Sn..; fabs FSn
+8.0xf9+4.4,3.2,1.X+4.0,4.Sn:D1a:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sn), in);
+ sim_fpu_abs (&out, &in);
+ FPU2FS (out, XS2FS (X,Sn));
+ }
+}
+
+// 1111 1001 1100 010X ---- Sn..; fabs FDn
+8.0xf9+4.0xc,3.2,1.X+4.0,3.fn,1.0:D1b:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0100 Sm.. ---- Sn.. X-Z-; fabs FSm,FSn
+8.0xfb+8.0x44+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sm), in);
+ sim_fpu_abs (&out, &in);
+ FPU2FS (out, XS2FS (Z,Sn));
+ }
+}
+
+// 1111 1011 1100 0100 fm.- ---- fn.- X-Z-; fabs FDm,FDn
+8.0xfb+8.0xc4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0100 011X ---- Sn..; fneg FSn
+8.0xf9+4.4,3.3,1.X+4.0,4.Sn:D1a:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sn), in);
+ sim_fpu_neg (&out, &in);
+ FPU2FS (out, XS2FS (X,Sn));
+ }
+}
+
+// 1111 1001 1100 011X ---- Sn..; fneg FDn
+8.0xf9+4.0xc,3.3,1.X+4.0,3.fn,1.0:D1b:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0110 Sm.. ---- Sn.. X-Z-; fneg FSm,FSn
+8.0xfb+8.0x46+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sm), in);
+ sim_fpu_neg (&out, &in);
+ FPU2FS (out, XS2FS (Z,Sn));
+ }
+}
+
+// 1111 1011 1100 0110 fm.- ---- fn.- X-Z-; fneg FDm,FDn
+8.0xfb+8.0xc6+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 000X ---- Sn..; frsqrt FSn
+8.0xf9+4.5,3.0,1.X+4.0,4.Sn:D1a:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1101 000X ---- fn.-; frsqrt FDn
+8.0xf9+4.0xd,3.0,1.X+4.0,3.fn,1.0:D1b:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0000 Sm.. ---- Sn.. X-Z-; frsqrt FSm,FSn
+8.0xfb+8.0x50+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sm), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1101 0000 fm.- ---- fn.- X-Z-; frsqrt FDm,FDn
+8.0xfb+8.0xd0+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 001X ---- Sn..; fsqrt FSn
+8.0xf9+4.5,3.1,1.X+4.0,4.Sn:D1a:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 1101 001X ---- fn.-; fsqrt FDn
+8.0xf9+4.0xd,3.1,1.X+4.0,3.fn,1.0:D1b:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0100 Sm.. ---- Sn.. X-Z-; fsqrt FSm,FSn
+8.0xfb+8.0x54+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 1101 0100 fm.- ---- fn.- X-Z-; fsqrt FDm,FDn
+8.0xfb+8.0xd4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 01YX Sm.. Sn..; fcmp FSm, FSn
+8.0xf9+4.5,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_cmp (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (Y,Sm), FP_SINGLE);
+}
+
+// 1111 1001 1101 01YX fm.- fn.-; fcmp FDm, FDn
+8.0xf9+4.0xd,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1110 0011 01Y1 Sm.. ---- IMM32; fcmp imm32, FSm
+8.0xfe+4.3,2.1,1.Y,1.1+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
+ }
+}
+
+// 1111 1001 0110 00YX Sm.. Sn..; fadd FSm, FSn
+8.0xf9+4.6,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_add (SD, CPU, cia,
+ &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 00YX fm.- fn.-; fadd FDm, FDn
+8.0xf9+4.0xe,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0000 Sm1. Sm2. Sn.. XYZ-; fadd FSm1, FSm2, FSn
+8.0xfb+8.0x60+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_add (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0000 fm1- fm2- fn.- XYZ-; fadd FDm1, FDm2, FDn
+8.0xfb+8.0xe0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 00YX Sm.. Sn.. IMM32; fadd imm32, FSm, FSn
+8.0xfe+4.6,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_add (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0110 01YX Sm.. Sn..; fsub FSm, FSn
+8.0xf9+4.6,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 01YX fm.- fn.-; fsub FDm, FDn
+8.0xf9+4.0xe,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0100 Sm1. Sm2. Sn.. XYZ-; fsub FSm1, FSm2, FSn
+8.0xfb+8.0x64+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0100 fm1- fm2- fn.- XYZ-; fsub FDm1, FDm2, FDn
+8.0xfb+8.0xe4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 01YX Sm.. Sn.. IMM32; fsub imm32, FSm, FSn
+8.0xfe+4.6,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0111 00YX Sm.. Sn..; fmul FSm, FSn
+8.0xf9+4.7,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_mul (SD, CPU, cia,
+ &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 00YX fm.- fn.-; fmul FDm, FDn
+8.0xf9+4.0xf,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0000 Sm1. Sm2. Sn.. XYZ-; fmul FSm1, FSm2, FSn
+8.0xfb+8.0x70+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_mul (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0000 fm1- fm2- fn.- XYZ-; fmul FDm1, FDm2, FDn
+8.0xfb+8.0xf0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 00YX Sm.. Sn.. IMM32; fmul imm32, FSm, FSn
+8.0xfe+4.7,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_mul (SD, CPU, cia,
+ &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0111 01YX Sm.. Sn..; fdiv FSm, FSn
+8.0xf9+4.7,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_div (SD, CPU, cia,
+ &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 01YX fm.- fn.-; fdiv FDm, FDn
+8.0xf9+4.0xf,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0100 Sm1. Sm2. Sn.. XYZ-; fdiv FSm1, FSm2, FSn
+8.0xfb+8.0x74+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_div (SD, CPU, cia,
+ &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0100 fm1- fm2- fn.- XYZ-; fdiv FDm1, FDm2, FDn
+8.0xfb+8.0xf4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 01YX Sm.. Sn.. IMM32; fdiv imm32, FSm, FSn
+8.0xfe+4.7,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_div (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1011 1000 00Sn Sm1. Sm2. Sm3. XYZA; fmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmadd
+"fmadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fmadd (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1000 01Sn Sm1. Sm2. Sm3. XYZA; fmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmsub
+"fmsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fmsub (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 00Sn Sm1. Sm2. Sm3. XYZA; fnmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmadd
+"fnmadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fnmadd (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 01Sn Sm1. Sm2. Sm3. XYZA; fnmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmsub
+"fnmsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fnmsub (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// conversion:
+
+// 1111 1011 0100 0000 Sm.. ---- Sn.. X-Z-; ftoi FSm,FSn
+8.0xfb+8.0x40+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::ftoi
+"ftoi"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0010 Sm.. ---- Sn.. X-Z-; itof FSm,FSn
+8.0xfb+8.0x42+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::itof
+"itof"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0010 Sm.. ---- fn.- X-Z-; ftod FSm,FDn
+8.0xfb+8.0x52+4.Sm,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2:::ftod
+"ftod"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0110 fm.- ---- Sn.. X-Z-; dtof FDm,FSn
+8.0xfb+8.0x56+3.fm,1.0,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::dtof
+"dtof"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// branching:
+
+// 1111 1000 1101 0000 d8; fbeq (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd0+8.D8:D1:::fbeq
+"fbeq"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_E))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0001 d8; fbne (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd1+8.D8:D1:::fbne
+"fbne"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0010 d8; fbgt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd2+8.D8:D1:::fbgt
+"fbgt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_G))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0011 d8; fbge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd3+8.D8:D1:::fbge
+"fbge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0100 d8; fblt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd4+8.D8:D1:::fblt
+"fblt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_L))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0101 d8; fble (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd5+8.D8:D1:::fble
+"fble"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0110 d8; fbuo (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd6+8.D8:D1:::fbuo
+"fbuo"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_U))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0111 d8; fblg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd7+8.D8:D1:::fblg
+"fblg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+// 1111 1000 1101 1000 d8; fbleg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd8+8.D8:D1:::fbleg
+"fbleg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1001 d8; fbug (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd9+8.D8:D1:::fbug
+"fbug"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1010 d8; fbuge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xda+8.D8:D1:::fbuge
+"fbuge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1011 d8; fbul (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdb+8.D8:D1:::fbul
+"fbul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1100 d8; fbule (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdc+8.D8:D1:::fbule
+"fbule"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1101 d8; fbue (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdd+8.D8:D1:::fbue
+"fbue"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0000; fleq
+8.0xf0+8.0xd0:D0:::fleq
+"fleq"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_E))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0001; flne
+8.0xf0+8.0xd1:D0:::flne
+"flne"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0010; flgt
+8.0xf0+8.0xd2:D0:::flgt
+"flgt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_G))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0011; flge
+8.0xf0+8.0xd3:D0:::flge
+"flge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0100; fllt
+8.0xf0+8.0xd4:D0:::fllt
+"fllt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_L))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0101; flle
+8.0xf0+8.0xd5:D0:::flle
+"flle"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0110; fluo
+8.0xf0+8.0xd6:D0:::fluo
+"fluo"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_U))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0111; fllg
+8.0xf0+8.0xd7:D0:::fllg
+"fllg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+// 1111 0000 1101 1000; flleg
+8.0xf0+8.0xd8:D0:::flleg
+"flleg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1001; flug
+8.0xf0+8.0xd9:D0:::flug
+"flug"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1010; fluge
+8.0xf0+8.0xda:D0:::fluge
+"fluge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1011; flul
+8.0xf0+8.0xdb:D0:::flul
+"flul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1100; flule
+8.0xf0+8.0xdc:D0:::flule
+"flule"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1101; flue
+8.0xf0+8.0xdd:D0:::flue
+"flue"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
Index: sim/mn10300/am33.igen
===================================================================
RCS file: /cvs/uberbaum/sim/mn10300/am33.igen,v
retrieving revision 1.8
diff -u -p -r1.8 am33.igen
--- sim/mn10300/am33.igen 26 Feb 2003 23:27:09 -0000 1.8
+++ sim/mn10300/am33.igen 9 Jul 2003 22:55:43 -0000
@@ -42,6 +42,7 @@
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_USP];
@@ -52,6 +53,7 @@
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
@@ -62,6 +64,7 @@
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
@@ -72,6 +75,7 @@
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = PC;
@@ -82,6 +86,7 @@
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_USP] = State.regs[REG_A0 + AM1];
@@ -91,6 +96,7 @@
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
@@ -100,6 +106,7 @@
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
@@ -110,6 +117,7 @@
8.0xf0+4.0xe,IMM4:D0t:::syscall
"syscall"
*am33
+*am33_2
{
unsigned32 sp, next_pc;
@@ -127,6 +135,7 @@
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_D0 + DN0] = PSW;
@@ -137,6 +146,7 @@
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
PSW = State.regs[REG_D0 + DM1];
@@ -146,6 +156,7 @@
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
@@ -157,6 +168,7 @@
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
@@ -168,6 +180,7 @@
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
@@ -179,6 +192,7 @@
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
@@ -191,6 +205,7 @@
8.0xf8+8.0xce+8.REGS:D1a:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
@@ -242,6 +257,7 @@
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x1)
@@ -283,6 +299,7 @@
8.0xf8+8.0xcf+8.REGS:D1b:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
@@ -291,6 +308,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
@@ -375,6 +393,7 @@
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
"and"
*am33
+*am33_2
{
PC = cia;
PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -384,6 +403,7 @@
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
"or"
*am33
+*am33_2
{
PC = cia;
PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -393,6 +413,7 @@
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -407,6 +428,7 @@
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -422,6 +444,7 @@
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
"extb"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -435,6 +458,7 @@
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
"extbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -448,6 +472,7 @@
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
"exth"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -461,6 +486,7 @@
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
"exthu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -474,6 +500,7 @@
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
"clr"
*am33
+*am33_2
{
int dstreg;
@@ -488,6 +515,7 @@
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
"add"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -501,6 +529,7 @@
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
"addc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
@@ -530,6 +559,7 @@
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
"sub"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -543,6 +573,7 @@
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
"subc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
@@ -572,6 +603,7 @@
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
"inc"
*am33
+*am33_2
{
int dstreg;
@@ -584,6 +616,7 @@
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
"inc4"
*am33
+*am33_2
{
int dstreg;
@@ -596,6 +629,7 @@
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2;
@@ -609,6 +643,7 @@
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
"mov"
*am33
+*am33_2
{
int dstreg, srcreg;
@@ -623,6 +658,7 @@
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -637,6 +673,7 @@
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
"and"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
@@ -657,6 +694,7 @@
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
"or"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
@@ -676,6 +714,7 @@
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
"xor"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
@@ -695,6 +734,7 @@
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
"not"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -713,6 +753,7 @@
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
"asr"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
@@ -736,6 +777,7 @@
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
"lsr"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n, c;
@@ -757,6 +799,7 @@
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
"asl"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
@@ -776,6 +819,7 @@
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
"asl2"
*am33
+*am33_2
{
int dstreg;
int n, z;
@@ -794,6 +838,7 @@
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
"ror"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
@@ -818,6 +863,7 @@
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
"rol"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
@@ -842,6 +888,7 @@
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
"mul"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
@@ -865,6 +912,7 @@
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
@@ -888,6 +936,7 @@
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
"div"
*am33
+*am33_2
{
int srcreg, dstreg;
signed64 temp;
@@ -913,6 +962,7 @@
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
"divu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
@@ -939,6 +989,7 @@
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -952,6 +1003,7 @@
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -965,6 +1017,7 @@
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -978,6 +1031,7 @@
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -991,6 +1045,7 @@
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1004,6 +1059,7 @@
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1017,6 +1073,7 @@
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1031,6 +1088,7 @@
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1045,6 +1103,7 @@
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -1057,6 +1116,7 @@
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -1069,6 +1129,7 @@
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -1081,6 +1142,7 @@
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -1093,6 +1155,7 @@
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -1105,6 +1168,7 @@
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -1117,6 +1181,7 @@
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1131,6 +1196,7 @@
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1146,6 +1212,7 @@
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@ -1174,6 +1241,7 @@
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned64 temp, sum;
@@ -1202,6 +1270,7 @@
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, sum;
@@ -1225,6 +1294,7 @@
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@ -1248,6 +1318,7 @@
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@ -1276,6 +1347,7 @@
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@ -1304,6 +1376,7 @@
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, temp2, sum;
@@ -1329,6 +1402,7 @@
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned32 temp, temp2, sum;
@@ -1354,6 +1428,7 @@
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
@@ -1374,6 +1449,7 @@
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
"dmachu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned32 temp;
@@ -1394,6 +1470,7 @@
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
"sat16"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, z, n;
@@ -1421,6 +1498,7 @@
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
"mcste"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1518,6 +1596,7 @@
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
"swap"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1535,6 +1614,7 @@
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
"swaph"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1552,6 +1632,7 @@
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
"swhw"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1567,6 +1648,7 @@
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg, dstreg;
@@ -1606,6 +1688,7 @@
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -1618,6 +1701,7 @@
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
@@ -1630,6 +1714,7 @@
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
"add"
*am33
+*am33_2
{
int dstreg;
@@ -1642,6 +1727,7 @@
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
"addc"
*am33
+*am33_2
{
int dstreg, imm;
int z, c, n, v;
@@ -1670,6 +1756,7 @@
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
@@ -1683,6 +1770,7 @@
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
"subc"
*am33
+*am33_2
{
int imm, dstreg;
int z, c, n, v;
@@ -1711,6 +1799,7 @@
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
@@ -1723,6 +1812,7 @@
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -1736,6 +1826,7 @@
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -1754,6 +1845,7 @@
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -1772,6 +1864,7 @@
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -1790,6 +1883,7 @@
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
@@ -1812,6 +1906,7 @@
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
@@ -1831,6 +1926,7 @@
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -1849,6 +1945,7 @@
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -1871,6 +1968,7 @@
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -1893,6 +1991,7 @@
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
@@ -1905,6 +2004,7 @@
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1918,6 +2018,7 @@
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1931,6 +2032,7 @@
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1944,6 +2046,7 @@
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1957,6 +2060,7 @@
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1970,6 +2074,7 @@
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1983,6 +2088,7 @@
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1997,6 +2103,7 @@
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -2012,6 +2119,7 @@
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -2024,6 +2132,7 @@
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -2036,6 +2145,7 @@
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -2048,6 +2158,7 @@
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -2060,6 +2171,7 @@
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -2072,6 +2184,7 @@
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -2084,6 +2197,7 @@
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -2098,6 +2212,7 @@
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -2113,6 +2228,7 @@
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2140,6 +2256,7 @@
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2167,6 +2284,7 @@
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2194,6 +2312,7 @@
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2221,6 +2340,7 @@
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2248,6 +2368,7 @@
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2275,6 +2396,7 @@
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
"mcste"
*am33
+*am33_2
{
int dstreg;
@@ -2371,6 +2493,7 @@
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
"add"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
@@ -2401,6 +2524,7 @@
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
"addc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
@@ -2431,6 +2555,7 @@
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
"sub"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
@@ -2461,6 +2586,7 @@
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
"subc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
@@ -2491,6 +2617,7 @@
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
"and"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@ -2513,6 +2640,7 @@
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
"or"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@ -2535,6 +2663,7 @@
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
"xor"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@ -2557,6 +2686,7 @@
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
"asr"
*am33
+*am33_2
{
int z, c, n;
signed32 temp;
@@ -2583,6 +2713,7 @@
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
"lsr"
*am33
+*am33_2
{
int z, c, n;
int srcreg1, srcreg2, dstreg;
@@ -2606,6 +2737,7 @@
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
"asl"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@ -2628,6 +2760,7 @@
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
"mul"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -2655,6 +2788,7 @@
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -2682,6 +2816,7 @@
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -2694,6 +2829,7 @@
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -2706,6 +2842,7 @@
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -2718,6 +2855,7 @@
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -2730,6 +2868,7 @@
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -2742,6 +2881,7 @@
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -2754,6 +2894,7 @@
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
"mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
@@ -2768,6 +2909,7 @@
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
@@ -2782,6 +2924,7 @@
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
@@ -2796,6 +2939,7 @@
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
@@ -2810,6 +2954,7 @@
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
@@ -2824,6 +2969,7 @@
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
@@ -2838,6 +2984,7 @@
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -2874,6 +3021,7 @@
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -2910,6 +3058,7 @@
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
@@ -2938,6 +3087,7 @@
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
@@ -2966,6 +3116,7 @@
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
@@ -2996,6 +3147,7 @@
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
@@ -3026,6 +3178,7 @@
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
@@ -3056,6 +3209,7 @@
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
@@ -3086,6 +3240,7 @@
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -3108,6 +3263,7 @@
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -3130,6 +3286,7 @@
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
"sat24"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, n, z;
@@ -3157,6 +3314,7 @@
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg1, srcreg2, dstreg;
@@ -3196,6 +3354,7 @@
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3208,6 +3367,7 @@
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
@@ -3220,6 +3380,7 @@
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
"add"
*am33
+*am33_2
{
int dstreg;
@@ -3232,6 +3393,7 @@
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
"addc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 sum, imm, reg2;
@@ -3259,6 +3421,7 @@
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
@@ -3271,6 +3434,7 @@
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
"subc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 difference, imm, reg2;
@@ -3298,6 +3462,7 @@
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
@@ -3310,6 +3475,7 @@
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3323,6 +3489,7 @@
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -3341,6 +3508,7 @@
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -3359,6 +3527,7 @@
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -3377,6 +3546,7 @@
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
@@ -3400,6 +3570,7 @@
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
@@ -3419,6 +3590,7 @@
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -3437,6 +3609,7 @@
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -3459,6 +3632,7 @@
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -3481,6 +3655,7 @@
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
@@ -3493,6 +3668,7 @@
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3508,6 +3684,7 @@
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3522,6 +3699,7 @@
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3537,6 +3715,7 @@
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3551,6 +3730,7 @@
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3566,6 +3746,7 @@
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3580,6 +3761,7 @@
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3594,6 +3776,7 @@
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3609,6 +3792,7 @@
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3622,6 +3806,7 @@
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -3635,6 +3820,7 @@
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -3648,6 +3834,7 @@
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -3661,6 +3848,7 @@
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -3674,6 +3862,7 @@
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -3687,6 +3876,7 @@
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3701,6 +3891,7 @@
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3715,6 +3906,7 @@
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3742,6 +3934,7 @@
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3769,6 +3962,7 @@
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3796,6 +3990,7 @@
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3823,6 +4018,7 @@
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3850,6 +4046,7 @@
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3877,6 +4074,7 @@
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3889,6 +4087,7 @@
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -3902,6 +4101,7 @@
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -3914,6 +4114,7 @@
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -3927,6 +4128,7 @@
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -3939,6 +4141,7 @@
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -3952,6 +4155,7 @@
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3964,6 +4168,7 @@
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
@@ -3976,6 +4181,7 @@
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
"add"
*am33
+*am33_2
{
int dstreg;
@@ -3988,6 +4194,7 @@
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
"addc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, sum;
@@ -4016,6 +4223,7 @@
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
@@ -4028,6 +4236,7 @@
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
"subc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, difference;
@@ -4056,6 +4265,7 @@
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
@@ -4068,6 +4278,7 @@
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -4081,6 +4292,7 @@
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -4099,6 +4311,7 @@
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -4117,6 +4330,7 @@
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -4135,6 +4349,7 @@
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
@@ -4157,6 +4372,7 @@
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
@@ -4176,6 +4392,7 @@
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -4194,6 +4411,7 @@
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -4216,6 +4434,7 @@
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -4238,6 +4457,7 @@
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
@@ -4250,6 +4470,7 @@
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4264,6 +4485,7 @@
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4278,6 +4500,7 @@
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4292,6 +4515,7 @@
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4306,6 +4530,7 @@
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4320,6 +4545,7 @@
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4334,6 +4560,7 @@
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4348,6 +4575,7 @@
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4363,6 +4591,7 @@
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -4376,6 +4605,7 @@
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -4389,6 +4619,7 @@
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -4402,6 +4633,7 @@
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -4415,6 +4647,7 @@
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -4428,6 +4661,7 @@
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -4442,6 +4676,7 @@
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4456,6 +4691,7 @@
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4471,6 +4707,7 @@
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
"mac"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
@@ -4499,6 +4736,7 @@
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
"macu"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
@@ -4527,6 +4765,7 @@
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
"macb"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
@@ -4550,6 +4789,7 @@
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
@@ -4573,6 +4813,7 @@
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
"mach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
@@ -4596,6 +4837,7 @@
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
"machu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
@@ -4619,6 +4861,7 @@
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
@@ -4644,6 +4887,7 @@
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
@@ -4669,6 +4913,7 @@
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
"dmulh"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
@@ -4689,6 +4934,7 @@
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
@@ -4709,6 +4955,7 @@
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -4721,6 +4968,7 @@
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -4733,6 +4981,7 @@
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -4745,6 +4994,7 @@
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -4757,6 +5007,7 @@
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -4769,6 +5020,7 @@
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -4781,6 +5033,7 @@
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4800,6 +5053,7 @@
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -4818,6 +5072,7 @@
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4837,6 +5092,7 @@
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -4855,6 +5111,7 @@
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -4872,6 +5129,7 @@
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -4888,6 +5146,7 @@
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4907,6 +5166,7 @@
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -4925,6 +5185,7 @@
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4947,6 +5208,7 @@
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -4968,6 +5230,7 @@
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4987,6 +5250,7 @@
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5006,6 +5270,7 @@
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5025,6 +5290,7 @@
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5043,6 +5309,7 @@
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5060,6 +5327,7 @@
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5076,6 +5344,7 @@
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5093,6 +5362,7 @@
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5109,6 +5379,7 @@
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5126,6 +5397,7 @@
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5142,6 +5414,7 @@
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed int temp;
@@ -5162,6 +5435,7 @@
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed int temp;
@@ -5181,6 +5455,7 @@
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5198,6 +5473,7 @@
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5215,6 +5491,7 @@
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5232,6 +5509,7 @@
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5248,6 +5526,7 @@
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5267,6 +5546,7 @@
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5285,6 +5565,7 @@
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5304,6 +5585,7 @@
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5322,6 +5604,7 @@
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5339,6 +5622,7 @@
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5355,6 +5639,7 @@
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5374,6 +5659,7 @@
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5392,6 +5678,7 @@
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5414,6 +5701,7 @@
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5435,6 +5723,7 @@
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5454,6 +5743,7 @@
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5473,6 +5763,7 @@
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5492,6 +5783,7 @@
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5510,6 +5802,7 @@
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5529,6 +5822,7 @@
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5547,6 +5841,7 @@
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5566,6 +5861,7 @@
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5584,6 +5880,7 @@
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5601,6 +5898,7 @@
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5617,6 +5915,7 @@
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5636,6 +5935,7 @@
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5654,6 +5954,7 @@
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5676,6 +5977,7 @@
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5697,6 +5999,7 @@
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5716,6 +6019,7 @@
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5735,6 +6039,7 @@
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5754,6 +6059,7 @@
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5772,6 +6078,7 @@
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5790,6 +6097,7 @@
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
"add_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5807,6 +6115,7 @@
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5825,6 +6134,7 @@
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
"add_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5842,6 +6152,7 @@
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -5858,6 +6169,7 @@
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -5873,6 +6185,7 @@
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5891,6 +6204,7 @@
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
"add_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5908,6 +6222,7 @@
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5929,6 +6244,7 @@
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
"add_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5949,6 +6265,7 @@
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5967,6 +6284,7 @@
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5985,6 +6303,7 @@
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6003,6 +6322,7 @@
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
"add_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6020,6 +6340,7 @@
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6036,6 +6357,7 @@
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6051,6 +6373,7 @@
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6067,6 +6390,7 @@
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6082,6 +6406,7 @@
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6098,6 +6423,7 @@
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6113,6 +6439,7 @@
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
signed int temp;
@@ -6132,6 +6459,7 @@
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
signed int temp;
@@ -6150,6 +6478,7 @@
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6166,6 +6495,7 @@
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6182,6 +6512,7 @@
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6198,6 +6529,7 @@
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6213,6 +6545,7 @@
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6231,6 +6564,7 @@
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
"sub_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6248,6 +6582,7 @@
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6266,6 +6601,7 @@
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6283,6 +6619,7 @@
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6299,6 +6636,7 @@
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6314,6 +6652,7 @@
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6332,6 +6671,7 @@
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6349,6 +6689,7 @@
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6370,6 +6711,7 @@
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6390,6 +6732,7 @@
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6408,6 +6751,7 @@
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6426,6 +6770,7 @@
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6444,6 +6789,7 @@
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6461,6 +6807,7 @@
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6479,6 +6826,7 @@
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
"mov_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6496,6 +6844,7 @@
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6514,6 +6863,7 @@
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6531,6 +6881,7 @@
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6547,6 +6898,7 @@
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6562,6 +6914,7 @@
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6580,6 +6933,7 @@
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6597,6 +6951,7 @@
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6618,6 +6973,7 @@
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6638,6 +6994,7 @@
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6656,6 +7013,7 @@
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6674,6 +7032,7 @@
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6692,6 +7051,7 @@
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6709,6 +7069,7 @@
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6728,6 +7089,7 @@
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6746,6 +7108,7 @@
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6765,6 +7128,7 @@
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6783,6 +7147,7 @@
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -6800,6 +7165,7 @@
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -6816,6 +7182,7 @@
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6835,6 +7202,7 @@
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6853,6 +7221,7 @@
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6875,6 +7244,7 @@
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6896,6 +7266,7 @@
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6915,6 +7286,7 @@
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6934,6 +7306,7 @@
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6953,6 +7326,7 @@
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6971,6 +7345,7 @@
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -6995,6 +7370,7 @@
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7018,6 +7394,7 @@
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7042,6 +7419,7 @@
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7065,6 +7443,7 @@
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7089,6 +7468,7 @@
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7112,6 +7492,7 @@
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7136,6 +7517,7 @@
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7159,6 +7541,7 @@
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7185,6 +7568,7 @@
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7210,6 +7594,7 @@
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7234,6 +7619,7 @@
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7258,6 +7644,7 @@
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7282,6 +7669,7 @@
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7305,6 +7693,7 @@
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7324,6 +7713,7 @@
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7342,6 +7732,7 @@
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7361,6 +7752,7 @@
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7379,6 +7771,7 @@
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -7396,6 +7789,7 @@
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -7412,6 +7806,7 @@
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7431,6 +7826,7 @@
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7449,6 +7845,7 @@
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7471,6 +7868,7 @@
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7492,6 +7890,7 @@
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7511,6 +7910,7 @@
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7530,6 +7930,7 @@
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7549,6 +7950,7 @@
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7567,6 +7969,7 @@
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7586,6 +7989,7 @@
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7605,6 +8009,7 @@
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7625,6 +8030,7 @@
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7644,6 +8050,7 @@
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -7662,6 +8069,7 @@
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -7679,6 +8087,7 @@
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7699,6 +8108,7 @@
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7718,6 +8128,7 @@
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7741,6 +8152,7 @@
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7763,6 +8175,7 @@
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7783,6 +8196,7 @@
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7803,6 +8217,7 @@
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7823,6 +8238,7 @@
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7842,6 +8258,7 @@
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7861,6 +8278,7 @@
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7879,6 +8297,7 @@
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7898,6 +8317,7 @@
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7916,6 +8336,7 @@
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -7933,6 +8354,7 @@
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -7949,6 +8371,7 @@
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7968,6 +8391,7 @@
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7986,6 +8410,7 @@
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8008,6 +8433,7 @@
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8029,6 +8455,7 @@
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8048,6 +8475,7 @@
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8067,6 +8495,7 @@
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8086,6 +8515,7 @@
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8104,6 +8534,7 @@
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8129,6 +8560,7 @@
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8153,6 +8585,7 @@
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8178,6 +8611,7 @@
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8202,6 +8636,7 @@
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -8224,6 +8659,7 @@
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -8245,6 +8681,7 @@
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8270,6 +8707,7 @@
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8294,6 +8732,7 @@
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8322,6 +8761,7 @@
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8349,6 +8789,7 @@
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8374,6 +8815,7 @@
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8399,6 +8841,7 @@
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8424,6 +8867,7 @@
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8448,6 +8892,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
"mov_llt"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8469,6 +8914,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
"mov_lgt"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8491,6 +8937,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
"mov_lge"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8512,6 +8959,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
"mov_lle"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8534,6 +8982,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
"mov_lcs"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8555,6 +9004,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
"mov_lhi"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8576,6 +9026,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
"mov_lcc"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8597,6 +9048,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
"mov_lls"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8618,6 +9070,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
"mov_leq"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8639,6 +9092,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
"mov_lne"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8660,6 +9114,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
"mov_lra"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8674,3 +9129,4 @@
nia = PC;
}
+:include::am33_2:am33-2.igen
Index: sim/mn10300/gencode.c
===================================================================
RCS file: /cvs/uberbaum/sim/mn10300/gencode.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 gencode.c
--- sim/mn10300/gencode.c 16 Apr 1999 01:35:07 -0000 1.1.1.1
+++ sim/mn10300/gencode.c 9 Jul 2003 22:55:43 -0000
@@ -109,6 +109,8 @@ write_opcodes ()
size = 5;
else if (opcode->format == FMT_D2)
size = 4;
+ else if (opcode->format == FMT_D3)
+ size = 5;
else if (opcode->format == FMT_D4)
size = 6;
else
Index: sim/mn10300/interp.c
===================================================================
RCS file: /cvs/uberbaum/sim/mn10300/interp.c,v
retrieving revision 1.2
diff -u -p -r1.2 interp.c
--- sim/mn10300/interp.c 27 Feb 2003 23:26:34 -0000 1.2
+++ sim/mn10300/interp.c 9 Jul 2003 22:55:52 -0000
@@ -860,6 +860,10 @@ sim_create_inferior (sd, abfd, argv, env
PC = bfd_get_start_address (abfd);
else
PC = 0;
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
+ PSW |= PSW_FE;
+
return SIM_RC_OK;
}
@@ -1182,6 +1186,9 @@ sim_create_inferior (sd, prog_bfd, argv,
}
CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
+ PSW |= PSW_FE;
+
return SIM_RC_OK;
}
@@ -1419,4 +1426,631 @@ mn10300_cpu_exception_resume(SIM_DESC sd
sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
}
State.exc_suspended = 0;
+}
+
+/* This is called when an FP instruction is issued when the FP unit is
+ disabled, i.e., the FE bit of PSW is zero. It raises interrupt
+ code 0x1c0. */
+void
+fpu_disabled_exception (sd, cpu, cia)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+{
+ sim_io_eprintf(sd, "FPU disabled exception\n");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called when the FP unit is enabled but one of the
+ unimplemented insns is issued. It raises interrupt code 0x1c8. */
+void
+fpu_unimp_exception (sd, cpu, cia)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+{
+ sim_io_eprintf(sd, "Unimplemented FPU instruction exception\n");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called at the end of any FP insns that may have triggered
+ FP exceptions. If no exception is enabled, it returns immediately.
+ Otherwise, it raises an exception code 0x1d0. */
+void
+fpu_check_signal_exception (sd, cpu, cia)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+{
+ if ((FPCR & EC_MASK) == 0)
+ return;
+
+ sim_io_eprintf(sd, "FPU %s%s%s%s%s exception\n",
+ (FPCR & EC_V) ? "V" : "",
+ (FPCR & EC_Z) ? "Z" : "",
+ (FPCR & EC_O) ? "O" : "",
+ (FPCR & EC_U) ? "U" : "",
+ (FPCR & EC_I) ? "I" : "");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* Convert a 32-bit single-precision FP value in the target platform
+ format to a sim_fpu value. */
+static void
+reg2val_32 (reg, val)
+ const void *reg;
+ sim_fpu *val;
+{
+ FS2FPU (*(reg_t *)reg, *val);
+}
+
+/* Round the given sim_fpu value to single precision, following the
+ target platform rounding and denormalization conventions. On
+ AM33/2.0, round_near is the only rounding mode. */
+static int
+round_32 (val)
+ sim_fpu *val;
+{
+ return sim_fpu_round_32 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 32-bit single-precision target
+ representation. */
+static void
+val2reg_32 (val, reg)
+ const sim_fpu *val;
+ void *reg;
+{
+ FPU2FS (*val, *(reg_t *)reg);
+}
+
+/* Define the 32-bit single-precision conversion and rounding uniform
+ interface. */
+const struct fp_prec_t
+fp_single_prec = {
+ reg2val_32, round_32, val2reg_32
+};
+
+/* Convert a 64-bit double-precision FP value in the target platform
+ format to a sim_fpu value. */
+static void
+reg2val_64 (reg, val)
+ const void *reg;
+ sim_fpu *val;
+{
+ FD2FPU (*(dword *)reg, *val);
+}
+
+/* Round the given sim_fpu value to double precision, following the
+ target platform rounding and denormalization conventions. On
+ AM33/2.0, round_near is the only rounding mode. */
+int
+round_64 (val)
+ sim_fpu *val;
+{
+ return sim_fpu_round_64 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 64-bit double-precision target
+ representation. */
+static void
+val2reg_64 (val, reg)
+ const sim_fpu *val;
+ void *reg;
+{
+ FPU2FD (*val, *(dword *)reg);
+}
+
+/* Define the 64-bit single-precision conversion and rounding uniform
+ interface. */
+const struct fp_prec_t
+fp_double_prec = {
+ reg2val_64, round_64, val2reg_64
+};
+
+/* Define shortcuts to the uniform interface operations. */
+#define REG2VAL(reg,val) (*ops->reg2val) (reg,val)
+#define ROUND(val) (*ops->round) (val)
+#define VAL2REG(val,reg) (*ops->val2reg) (val,reg)
+
+/* Check whether overflow, underflow or inexact exceptions should be
+ raised. */
+int
+fpu_status_ok (stat)
+ sim_fpu_status stat;
+{
+ if ((stat & sim_fpu_status_overflow)
+ && (FPCR & EE_O))
+ FPCR |= EC_O;
+ else if ((stat & (sim_fpu_status_underflow | sim_fpu_status_denorm))
+ && (FPCR & EE_U))
+ FPCR |= EC_U;
+ else if ((stat & (sim_fpu_status_inexact | sim_fpu_status_rounded))
+ && (FPCR & EE_I))
+ FPCR |= EC_I;
+ else if (stat & ~ (sim_fpu_status_overflow
+ | sim_fpu_status_underflow
+ | sim_fpu_status_denorm
+ | sim_fpu_status_inexact
+ | sim_fpu_status_rounded))
+ abort ();
+ else
+ return 1;
+ return 0;
+}
+
+/* Implement a 32/64 bit reciprocal square root, signaling FP
+ exceptions when appropriate. */
+void
+fpu_rsqrt (sd, cpu, cia, reg_in, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu in, med, out;
+
+ REG2VAL (reg_in, &in);
+ ROUND (&in);
+ FPCR &= ~ EC_MASK;
+ switch (sim_fpu_is (&in))
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NINF:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ break;
+
+ case SIM_FPU_IS_QNAN:
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ break;
+
+ case SIM_FPU_IS_PINF:
+ VAL2REG (&sim_fpu_zero, reg_out);
+ break;
+
+ case SIM_FPU_IS_PNUMBER:
+ {
+ /* Since we don't have a function to compute rsqrt directly,
+ use sqrt and inv. */
+ sim_fpu_status stat = 0;
+ stat |= sim_fpu_sqrt (&med, &in);
+ stat |= sim_fpu_inv (&out, &med);
+ stat |= ROUND (&out);
+ if (fpu_status_ok (stat))
+ VAL2REG (&out, reg_out);
+ }
+ break;
+
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ if (FPCR & EE_Z)
+ FPCR |= EC_Z;
+ else
+ {
+ /* Generate an INF with the same sign. */
+ sim_fpu_inv (&out, &in);
+ VAL2REG (&out, reg_out);
+ }
+ break;
+
+ default:
+ abort ();
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+static inline reg_t
+cmp2fcc (res)
+ int res;
+{
+ switch (res)
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ return FCC_U;
+
+ case SIM_FPU_IS_NINF:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NDENORM:
+ return FCC_L;
+
+ case SIM_FPU_IS_PINF:
+ case SIM_FPU_IS_PNUMBER:
+ case SIM_FPU_IS_PDENORM:
+ return FCC_G;
+
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ return FCC_E;
+
+ default:
+ abort ();
+ }
+}
+
+/* Implement a 32/64 bit FP compare, setting the FPCR status and/or
+ exception bits as specified. */
+void
+fpu_cmp (sd, cpu, cia, reg_in1, reg_in2, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m, n;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ FPCR &= ~ EC_MASK;
+ FPCR &= ~ FCC_MASK;
+ ROUND (&m);
+ ROUND (&n);
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ FPCR |= FCC_U;
+ }
+ else
+ FPCR |= cmp2fcc (sim_fpu_cmp (&m, &n));
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP add, setting FP exception bits when
+ appropriate. */
+void
+fpu_add (sd, cpu, cia, reg_in1, reg_in2, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_NINF)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_PINF))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_add (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP sub, setting FP exception bits when
+ appropriate. */
+void
+fpu_sub (sd, cpu, cia, reg_in1, reg_in2, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_PINF)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_NINF))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_sub (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP mul, setting FP exception bits when
+ appropriate. */
+void
+fpu_mul (sd, cpu, cia, reg_in1, reg_in2, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m) && sim_fpu_is_zero (&n))
+ || (sim_fpu_is_zero (&m) && sim_fpu_is_infinity (&n)))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP div, setting FP exception bits when
+ appropriate. */
+void
+fpu_div (sd, cpu, cia, reg_in1, reg_in2, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n))
+ || (sim_fpu_is_zero (&m) && sim_fpu_is_zero (&n)))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else if (sim_fpu_is_number (&m) && sim_fpu_is_zero (&n)
+ && (FPCR & EE_Z))
+ FPCR |= EC_Z;
+ else
+ {
+ sim_fpu_status stat = sim_fpu_div (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP madd, setting FP exception bits when
+ appropriate. */
+void
+fpu_fmadd (sd, cpu, cia, reg_in1, reg_in2, reg_in3, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2, *reg_in3;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m1, m2, m, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_add (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP msub, setting FP exception bits when
+ appropriate. */
+void
+fpu_fmsub (sd, cpu, cia, reg_in1, reg_in2, reg_in3, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2, *reg_in3;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m1, m2, m, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_sub (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmadd, setting FP exception bits when
+ appropriate. */
+void
+fpu_fnmadd (sd, cpu, cia, reg_in1, reg_in2, reg_in3, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2, *reg_in3;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m1, m2, m, mm, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_neg (&mm, &m);
+ stat |= sim_fpu_add (&r, &mm, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmsub, setting FP exception bits when
+ appropriate. */
+void
+fpu_fnmsub (sd, cpu, cia, reg_in1, reg_in2, reg_in3, reg_out, ops)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ sim_cia cia;
+ const void *reg_in1, *reg_in2, *reg_in3;
+ void *reg_out;
+ const struct fp_prec_t *ops;
+{
+ sim_fpu m1, m2, m, mm, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_neg (&mm, &m);
+ stat |= sim_fpu_sub (&r, &mm, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
}
Index: sim/mn10300/mn10300.igen
===================================================================
RCS file: /cvs/uberbaum/sim/mn10300/mn10300.igen,v
retrieving revision 1.4
diff -u -p -r1.4 mn10300.igen
--- sim/mn10300/mn10300.igen 7 May 2001 04:52:00 -0000 1.4
+++ sim/mn10300/mn10300.igen 9 Jul 2003 22:55:52 -0000
@@ -4,6 +4,7 @@
:option:::hi-bit-nr:7
:model:::mn10300:mn10300:
:model:::am33:am33:
+:model:::am33_2:am33_2:
// What do we do with an illegal instruction?
:internal::::illegal:
@@ -17,6 +18,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_8000 (); */
signed32 immed = EXTEND8 (IMM8);
@@ -29,6 +31,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_80 (); */
@@ -41,6 +44,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F1E0 (); */
PC = cia;
@@ -53,6 +57,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F1D0 (); */
PC = cia;
@@ -65,6 +70,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_9000 (); */
@@ -77,6 +83,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_90 (); */
@@ -89,6 +96,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_3C (); */
PC = cia;
@@ -101,6 +109,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F0 (); */
PC = cia;
@@ -113,6 +122,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2E4 (); */
PC = cia;
@@ -125,6 +135,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F3 (); */
PC = cia;
@@ -137,6 +148,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2E0 (); */
PC = cia;
@@ -149,6 +161,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F2 (); */
PC = cia;
@@ -161,6 +174,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_70 (); */
PC = cia;
@@ -173,6 +187,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F80000 (); */
PC = cia;
@@ -186,6 +201,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA000000 (); */
PC = cia;
@@ -199,6 +215,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC000000 (); */
PC = cia;
@@ -213,6 +230,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_5800 (); */
PC = cia;
@@ -225,6 +243,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAB40000 (); */
PC = cia;
@@ -238,6 +257,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCB40000 (); */
PC = cia;
@@ -251,6 +271,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F300 (); */
PC = cia;
@@ -264,6 +285,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_300000 (); */
PC = cia;
@@ -275,6 +297,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCA40000 (); */
PC = cia;
@@ -287,6 +310,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F000 (); */
PC = cia;
@@ -299,6 +323,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F82000 (); */
PC = cia;
@@ -312,6 +337,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA200000 (); */
PC = cia;
@@ -326,6 +352,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC200000 (); */
PC = cia;
@@ -340,6 +367,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_5C00 (); */
PC = cia;
@@ -353,6 +381,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAB00000 (); */
PC = cia;
@@ -366,6 +395,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCB00000 (); */
PC = cia;
@@ -380,6 +410,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F380 (); */
PC = cia;
@@ -394,6 +425,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAA00000 (); */
PC = cia;
@@ -406,6 +438,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCA00000 (); */
PC = cia;
@@ -419,6 +452,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F8F000 (); */
PC = cia;
@@ -432,6 +466,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_60 (); */
PC = cia;
@@ -444,6 +479,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F81000 (); */
PC = cia;
@@ -457,6 +493,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA100000 (); */
PC = cia;
@@ -470,6 +507,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC100000 (); */
PC = cia;
@@ -484,6 +522,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_4200 (); */
PC = cia;
@@ -496,6 +535,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA910000 (); */
PC = cia;
@@ -509,6 +549,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC910000 (); */
PC = cia;
@@ -522,6 +563,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F340 (); */
PC = cia;
@@ -535,6 +577,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_10000 (); */
PC = cia;
@@ -547,6 +590,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC810000 (); */
PC = cia;
@@ -560,6 +604,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F010 (); */
PC = cia;
@@ -572,6 +617,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F83000 (); */
PC = cia;
@@ -585,6 +631,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA300000 (); */
PC = cia;
@@ -598,6 +645,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC300000 (); */
PC = cia;
@@ -613,6 +661,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_4300 (); */
@@ -627,6 +676,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA900000 (); */
@@ -642,6 +692,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC900000 (); */
@@ -657,6 +708,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F3C0 (); */
@@ -672,6 +724,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA800000 (); */
@@ -687,6 +740,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC800000 (); */
@@ -702,6 +756,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8F400 (); */
@@ -717,6 +772,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_2C0000 (); */
@@ -734,6 +790,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCCC0000 (); */
@@ -751,6 +808,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_240000 (); */
@@ -768,6 +826,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCDC0000 (); */
@@ -782,6 +841,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F040 (); */
@@ -797,6 +857,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F84000 (); */
@@ -812,6 +873,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA400000 (); */
@@ -828,6 +890,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC400000 (); */
@@ -844,6 +907,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8B800 (); */
@@ -859,6 +923,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAB80000 (); */
@@ -875,6 +940,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCB80000 (); */
@@ -891,6 +957,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F400 (); */
@@ -907,6 +974,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_340000 (); */
@@ -921,6 +989,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCA80000 (); */
@@ -936,6 +1005,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F050 (); */
@@ -950,6 +1020,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F85000 (); */
@@ -965,6 +1036,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA500000 (); */
@@ -980,6 +1052,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC500000 (); */
@@ -996,6 +1069,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F89200 (); */
@@ -1010,6 +1084,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA920000 (); */
@@ -1025,6 +1100,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC920000 (); */
@@ -1040,6 +1116,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F440 (); */
@@ -1055,6 +1132,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_20000 (); */
@@ -1070,6 +1148,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC820000 (); */
@@ -1085,6 +1164,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F060 (); */
@@ -1100,6 +1180,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F86000 (); */
@@ -1115,6 +1196,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA600000 (); */
@@ -1131,6 +1213,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC600000 (); */
@@ -1147,6 +1230,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8BC00 (); */
@@ -1162,6 +1246,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FABC0000 (); */
@@ -1177,6 +1262,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCBC0000 (); */
@@ -1192,6 +1278,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F480 (); */
@@ -1207,6 +1294,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_380000 (); */
@@ -1221,6 +1309,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCAC0000 (); */
@@ -1236,6 +1325,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F070 (); */
@@ -1251,6 +1341,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F87000 (); */
@@ -1266,6 +1357,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA700000 (); */
@@ -1281,6 +1373,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC700000 (); */
@@ -1297,6 +1390,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F89300 (); */
@@ -1312,6 +1406,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA930000 (); */
@@ -1327,6 +1422,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC930000 (); */
@@ -1342,6 +1438,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F4C0 (); */
@@ -1357,6 +1454,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_30000 (); */
@@ -1371,6 +1469,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC830000 (); */
@@ -1386,6 +1485,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F2D0 (); */
@@ -1403,6 +1503,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_10 (); */
@@ -1417,6 +1518,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_14 (); */
@@ -1431,6 +1533,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_18 (); */
@@ -1445,6 +1548,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_1C (); */
@@ -1459,6 +1563,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_0 (); */
@@ -1476,6 +1581,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_E0 (); */
@@ -1489,6 +1595,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F160 (); */
@@ -1503,6 +1610,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F150 (); */
@@ -1517,6 +1625,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F170 (); */
@@ -1531,6 +1640,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_2800 (); */
@@ -1545,6 +1655,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAC00000 (); */
@@ -1559,6 +1670,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCC00000 (); */
@@ -1573,6 +1685,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_2000 (); */
@@ -1587,6 +1700,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAD00000 (); */
@@ -1601,6 +1715,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCD00000 (); */
@@ -1615,6 +1730,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8FE00 (); */
@@ -1633,6 +1749,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAFE0000 (); */
@@ -1651,6 +1768,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCFE0000 (); */
@@ -1669,6 +1787,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F140 (); */
@@ -1699,6 +1818,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F100 (); */
@@ -1712,6 +1832,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F120 (); */
@@ -1726,6 +1847,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F110 (); */
@@ -1740,6 +1862,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F130 (); */
@@ -1754,6 +1877,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCC40000 (); */
@@ -1768,6 +1892,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCD40000 (); */
@@ -1782,6 +1907,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F180 (); */
@@ -1812,6 +1938,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F240 (); */
@@ -1836,6 +1963,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F250 (); */
@@ -1860,6 +1988,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F260 (); */
@@ -1897,6 +2026,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F270 (); */
@@ -1933,6 +2063,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_40 (); */
@@ -1950,6 +2081,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_41 (); */
@@ -1964,6 +2096,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_50 (); */
@@ -1978,6 +2111,7 @@
*mn10300
*am33
+*am33_2
{
PC = cia;
@@ -1992,6 +2126,7 @@
*mn10300
*am33
+*am33_2
{
PC = cia;
@@ -2006,6 +2141,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F1A0 (); */
@@ -2020,6 +2156,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F190 (); */
@@ -2034,6 +2171,7 @@
*mn10300
*am33
+*am33_2
{
PC = cia;
@@ -2049,6 +2187,7 @@
*mn10300
*am33
+*am33_2
{
PC = cia;
@@ -2063,6 +2202,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAC80000 (); */
@@ -2078,6 +2218,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCC80000 (); */
@@ -2093,6 +2234,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAD80000 (); */
@@ -2108,6 +2250,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCD80000 (); */
@@ -2123,6 +2266,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F200 (); */
@@ -2143,6 +2287,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8E000 (); */
@@ -2163,6 +2308,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAE00000 (); */
@@ -2183,6 +2329,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCE00000 (); */
@@ -2204,6 +2351,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAFC0000 (); */
@@ -2219,6 +2367,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F210 (); */
@@ -2233,6 +2382,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8E400 (); */
@@ -2247,6 +2397,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAE40000 (); */
@@ -2261,6 +2412,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCE40000 (); */
@@ -2275,6 +2427,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAFD0000 (); */
@@ -2289,6 +2442,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F220 (); */
@@ -2303,6 +2457,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAE80000 (); */
@@ -2317,6 +2472,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCE80000 (); */
@@ -2331,6 +2487,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F230 (); */
@@ -2351,6 +2508,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8EC00 (); */
@@ -2365,6 +2523,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAEC0000 (); */
@@ -2379,6 +2538,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCEC0000 (); */
@@ -2394,6 +2554,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FE020000 (); */
@@ -2410,6 +2571,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAF80000 (); */
@@ -2425,6 +2587,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F080 (); */
@@ -2448,6 +2611,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FE000000 (); */
@@ -2471,6 +2635,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAF00000 (); */
@@ -2493,6 +2658,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F090 (); */
@@ -2516,6 +2682,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FE010000 (); */
@@ -2539,6 +2706,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAF40000 (); */
@@ -2561,6 +2729,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F2B0 (); */
@@ -2585,6 +2754,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8C800 (); */
@@ -2609,6 +2779,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F2A0 (); */
@@ -2631,6 +2802,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8C400 (); */
@@ -2652,6 +2824,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F290 (); */
@@ -2673,6 +2846,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8C000 (); */
@@ -2693,6 +2867,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_54 (); */
@@ -2713,6 +2888,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F284 (); */
@@ -2739,6 +2915,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F280 (); */
@@ -2765,6 +2942,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C800 (); */
@@ -2783,6 +2961,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C900 (); */
@@ -2801,6 +2980,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C100 (); */
@@ -2820,6 +3000,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C200 (); */
@@ -2838,6 +3019,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C300 (); */
@@ -2857,6 +3039,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C000 (); */
@@ -2875,6 +3058,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C500 (); */
@@ -2893,6 +3077,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C600 (); */
@@ -2911,6 +3096,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C700 (); */
@@ -2929,6 +3115,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C400 (); */
@@ -2947,6 +3134,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8E800 (); */
@@ -2965,6 +3153,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8E900 (); */
@@ -2983,6 +3172,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8EA00 (); */
@@ -3001,6 +3191,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8EB00 (); */
@@ -3019,6 +3210,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CA00 (); */
@@ -3034,6 +3226,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D8 (); */
@@ -3052,6 +3245,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D9 (); */
@@ -3070,6 +3264,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D1 (); */
@@ -3089,6 +3284,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D2 (); */
@@ -3107,6 +3303,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D3 (); */
@@ -3126,6 +3323,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D0 (); */
@@ -3144,6 +3342,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D5 (); */
@@ -3162,6 +3361,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D6 (); */
@@ -3180,6 +3380,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D7 (); */
@@ -3198,6 +3399,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D4 (); */
@@ -3216,6 +3418,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DA (); */
@@ -3231,6 +3434,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DB (); */
@@ -3246,6 +3450,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0F4 (); */
@@ -3260,6 +3465,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CC0000 (); */
@@ -3274,6 +3480,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DC000000 (); */
@@ -3288,6 +3495,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0F0 (); */
@@ -3309,6 +3517,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAFF0000 (); */
@@ -3330,6 +3539,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCFF0000 (); */
@@ -3351,6 +3561,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0FC (); */
@@ -3368,6 +3579,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0FD (); */
@@ -3387,6 +3599,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0FE (); */
@@ -3406,6 +3619,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0FF (); */
@@ -3420,6 +3634,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CB (); */
@@ -3444,6 +3659,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F6F0 (); */
@@ -3465,6 +3681,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F600 (); */
@@ -3489,6 +3706,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F90000 (); */
@@ -3513,6 +3731,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FB000000 (); */
@@ -3537,6 +3756,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FD000000 (); */
@@ -3561,6 +3781,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F610 (); */
@@ -3585,6 +3806,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F91400 (); */
@@ -3609,6 +3831,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FB140000 (); */
@@ -3633,6 +3856,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FD140000 (); */
@@ -3657,6 +3881,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F640 (); */
@@ -3676,6 +3901,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F650 (); */
@@ -3695,6 +3921,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F670 (); */
@@ -3715,6 +3942,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0C0 (); */
@@ -3729,6 +3957,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FF (); */
@@ -3742,6 +3971,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CE00 (); */
@@ -3795,6 +4025,7 @@
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x1)
@@ -3839,6 +4070,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CF00 (); */
@@ -3849,6 +4081,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
@@ -3936,6 +4169,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CD000000 (); */
@@ -3950,6 +4184,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
@@ -4043,6 +4278,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DD000000 (); */
@@ -4058,6 +4294,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
@@ -4150,6 +4387,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DF0000 (); */
@@ -4164,6 +4402,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
@@ -4253,6 +4492,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DE0000 (); */
@@ -4268,6 +4508,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
Index: sim/mn10300/mn10300_sim.h
===================================================================
RCS file: /cvs/uberbaum/sim/mn10300/mn10300_sim.h,v
retrieving revision 1.3
diff -u -p -r1.3 mn10300_sim.h
--- sim/mn10300/mn10300_sim.h 9 Jun 2002 15:45:50 -0000 1.3
+++ sim/mn10300/mn10300_sim.h 9 Jul 2003 22:55:55 -0000
@@ -6,6 +6,7 @@
#include <limits.h>
#include "gdb/remote-sim.h"
#include "bfd.h"
+#include "sim-fpu.h"
#ifndef INLINE
#ifdef __GNUC__
@@ -53,6 +54,10 @@ typedef signed long int32;
# endif
#endif
+typedef struct
+{
+ uint32 low, high;
+} dword;
typedef uint32 reg_t;
struct simops
@@ -73,6 +78,11 @@ struct _state
reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
lir, lar, mdrq, plus some room for processor
specific regs. */
+ union
+ {
+ reg_t fs[32]; /* FS0-31 */
+ dword fd[16]; /* FD0,2,...,30 */
+ } fpregs;
uint8 *mem; /* main memory */
int exception;
int exited;
@@ -123,6 +133,52 @@ extern struct simops Simops[];
#define REG_MCRL 27
#define REG_MCVF 28
+#define REG_FPCR 29
+
+#define FPCR (State.regs[REG_FPCR])
+
+#define FCC_MASK LSMASK (21, 18)
+#define RM_MASK LSMASK (17, 16) /* Must always be zero. */
+#define EC_MASK LSMASK (14, 10)
+#define EE_MASK LSMASK ( 9, 5)
+#define EF_MASK LSMASK ( 4, 0)
+#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
+
+#define FCC_L LSBIT (21)
+#define FCC_G LSBIT (20)
+#define FCC_E LSBIT (19)
+#define FCC_U LSBIT (18)
+
+#define EC_V LSBIT (14)
+#define EC_Z LSBIT (13)
+#define EC_O LSBIT (12)
+#define EC_U LSBIT (11)
+#define EC_I LSBIT (10)
+
+#define EE_V LSBIT (9)
+#define EE_Z LSBIT (8)
+#define EE_O LSBIT (7)
+#define EE_U LSBIT (6)
+#define EE_I LSBIT (5)
+
+#define EF_V LSBIT (4)
+#define EF_Z LSBIT (3)
+#define EF_O LSBIT (2)
+#define EF_U LSBIT (1)
+#define EF_I LSBIT (0)
+
+#define PSW_FE LSBIT(20)
+#define FPU_DISABLED !(PSW & PSW_FE)
+
+#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
+#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
+#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
+
+#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
+#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
+#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
+#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
+
#if WITH_COMMON
/* These definitions conflict with similar macros in common. */
#else
@@ -176,6 +232,21 @@ sim_core_read_unaligned_2 (STATE_CPU (si
#define load_word(ADDR) \
sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+#define load_dword(ADDR) \
+u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
+ PC, read_map, (ADDR)))
+
+static INLINE dword
+u642dw (dw)
+ unsigned64 dw;
+{
+ dword r;
+
+ r.low = (unsigned32)dw;
+ r.high = (unsigned32)(dw >> 32);
+ return r;
+}
+
#define store_byte(ADDR, DATA) \
sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), (DATA))
@@ -189,6 +260,16 @@ sim_core_write_unaligned_2 (STATE_CPU (s
#define store_word(ADDR, DATA) \
sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), (DATA))
+#define store_dword(ADDR, DATA) \
+sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
+ PC, write_map, (ADDR), dw2u64 (DATA))
+
+static INLINE unsigned64
+dw2u64 (data)
+ dword data;
+{
+ return data.low | (((unsigned64)data.high) << 32);
+}
#endif /* WITH_COMMON */
#if WITH_COMMON
@@ -261,6 +342,17 @@ load_word (addr)
return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
}
+static INLINE dword
+load_dword (addr)
+ SIM_ADDR addr;
+{
+ dword r;
+
+ r.low = load_word (addr);
+ r.high = load_word (addr+4);
+ return r;
+}
+
static INLINE uint32
load_mem (addr, len)
SIM_ADDR addr;
@@ -353,6 +445,15 @@ store_word (addr, data)
p[2] = data >> 16;
p[3] = data >> 24;
}
+
+static INLINE void
+store_dword (addr, data)
+ SIM_ADDR addr;
+ dword data;
+{
+ store_word (addr, data.low);
+ store_word (addr + 4, data.high);
+}
#endif /* not WITH_COMMON */
/* Function declarations. */
@@ -388,3 +489,29 @@ void program_interrupt (SIM_DESC sd, sim
void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+
+void fpu_disabled_exception PARAMS ((SIM_DESC, sim_cpu *, address_word));
+void fpu_unimp_exception PARAMS ((SIM_DESC, sim_cpu *, address_word));
+void fpu_check_signal_exception PARAMS ((SIM_DESC, sim_cpu *, address_word));
+
+extern const struct fp_prec_t
+{
+ void (* reg2val) PARAMS ((const void *, sim_fpu *));
+ int (* round) PARAMS ((sim_fpu *));
+ void (* val2reg) PARAMS ((const sim_fpu *, void *));
+} fp_single_prec, fp_double_prec;
+
+#define FP_SINGLE (&fp_single_prec)
+#define FP_DOUBLE (&fp_double_prec)
+
+void fpu_rsqrt PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *));
+void fpu_sqrt PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *));
+void fpu_cmp PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *));
+void fpu_add PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *));
+void fpu_sub PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *));
+void fpu_mul PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *));
+void fpu_div PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *));
+void fpu_fmadd PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *));
+void fpu_fmsub PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *));
+void fpu_fnmadd PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *));
+void fpu_fnmsub PARAMS ((SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *));
Index: gdb/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2003-06-11 Alexandre Oliva <aoliva@redhat.com>
* mn10300-tdep.c (set_reg_offsets): Don't dereference frame_info*.
(mn10300_analyze_prologue): Likewise.
2002-11-04 Andrew Cagney <cagney@redhat.com>
* mn10300-tdep.c (am33_2_register_name): Make return type const.
2002-01-20 Jackie Smith Cashion <jsmith@redhat.com>
* mn10300-tdep.c (set_reg_offsets): New function.
(mn10300_analyze_prologue): Add support for AM33-2 function prologues.
2001-02-27 Matt Hiller <hiller@redhat.com>
* config/mn10300/tm-mn10300.h (FS0_REGNUM): New macro.
Fri Aug 11 19:00:51 2000 Andrew Cagney <cagney@makita.cygnus.com>
* mn10300-tdep.c (am33_2_register_name): Fix names for ``fs0'' on.
Were one index out.
2000-08-11 Andrew Cagney <cagney@ops1.cygnus.com>
* mn10300-tdep.c (am33_2_register_name): Fix register names - add
FPCR and MDRQ.
2000-08-10 Andrew Cagney <cagney@ops1.cygnus.com>
* mn10300-tdep.c (am33_2_register_name): New function. Replace
am33_2_register_names.
Sat Aug 5 01:19:12 2000 Andrew Cagney <cagney@b1.cygnus.com>
* mn10300-tdep.c (am33_2_register_names): New array.
(set_machine_hook): Set mn10300_register_names to
am33_2_register_names.
* config/mn10300/tm-mn10300.h (NUM_REGS): Increase to 64.
Index: gdb/mn10300-tdep.c
===================================================================
RCS file: /cvs/uberbaum/gdb/mn10300-tdep.c,v
retrieving revision 1.83
diff -u -p -r1.83 mn10300-tdep.c
--- gdb/mn10300-tdep.c 16 Jun 2003 16:47:42 -0000 1.83
+++ gdb/mn10300-tdep.c 9 Jul 2003 22:56:10 -0000
@@ -32,6 +32,7 @@
#include "regcache.h"
#include "arch-utils.h"
#include "gdb_assert.h"
+#include "solib-svr4.h"
#define D0_REGNUM 0
#define D2_REGNUM 2
@@ -48,6 +49,7 @@
#define MCRH_REGNUM 26
#define MCRL_REGNUM 27
#define MCVF_REGNUM 28
+#define FS0_REGNUM 32
enum movm_register_bits {
movm_exother_bit = 0x01,
@@ -114,6 +116,23 @@ am33_register_name (int reg)
return register_name (reg, regs, sizeof regs);
}
+static const char *
+am33_2_register_name (int reg)
+{
+ static char *regs[] =
+ {
+ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
+ "sp", "pc", "mdr", "psw", "lir", "lar", "mdrq", "r0",
+ "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ssp",
+ "msp", "usp", "mcrh", "mcrl", "mcvf", "fpcr", "", "",
+ "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+ "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
+ "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
+ "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
+ };
+ return register_name (reg, regs, sizeof regs);
+}
+
static CORE_ADDR
mn10300_saved_pc_after_call (struct frame_info *fi)
{
@@ -219,6 +238,103 @@ fix_frame_pointer (struct frame_info *fi
}
}
+/* Set offsets of saved registers.
+ This is a helper function for mn10300_analyze_prologue. When the AM33-2
+ code is no longer sanitized consider deleting the set_movm_offsets function
+ and use only this funciton. */
+
+static void
+set_reg_offsets (struct frame_info *fi, int movm_args, unsigned long fpregmask)
+{
+ int i, offset = 0;
+
+ if (fi == NULL)
+ return;
+
+ if (AM33_MODE == 2)
+ {
+ /* If bit N is set in fpregmask, fsN is saved on the stack.
+ The floating point registers are saved in ascending order.
+ For example: fs16 <- Frame Pointer
+ fs17 Frame Pointer + 4 */
+ if (fpregmask != 0)
+ {
+ for (i = 0; i < 32; i++)
+ {
+ if (fpregmask & (1 << i))
+ {
+ get_frame_saved_regs (fi)[FS0_REGNUM + i] = get_frame_base (fi) + offset;
+ offset += 4;
+ }
+ }
+ }
+ }
+
+ if (movm_args == 0)
+ return;
+
+ if (movm_args & movm_other_bit)
+ {
+ /* The `other' bit leaves a blank area of four bytes at the
+ beginning of its block of saved registers, making it 32 bytes
+ long in total. */
+ get_frame_saved_regs (fi)[LAR_REGNUM] = get_frame_base (fi) + offset + 4;
+ get_frame_saved_regs (fi)[LIR_REGNUM] = get_frame_base (fi) + offset + 8;
+ get_frame_saved_regs (fi)[MDR_REGNUM] = get_frame_base (fi) + offset + 12;
+ get_frame_saved_regs (fi)[A0_REGNUM + 1] = get_frame_base (fi) + offset + 16;
+ get_frame_saved_regs (fi)[A0_REGNUM] = get_frame_base (fi) + offset + 20;
+ get_frame_saved_regs (fi)[D0_REGNUM + 1] = get_frame_base (fi) + offset + 24;
+ get_frame_saved_regs (fi)[D0_REGNUM] = get_frame_base (fi) + offset + 28;
+ offset += 32;
+ }
+ if (movm_args & movm_a3_bit)
+ {
+ get_frame_saved_regs (fi)[A3_REGNUM] = get_frame_base (fi) + offset;
+ offset += 4;
+ }
+ if (movm_args & movm_a2_bit)
+ {
+ get_frame_saved_regs (fi)[A2_REGNUM] = get_frame_base (fi) + offset;
+ offset += 4;
+ }
+ if (movm_args & movm_d3_bit)
+ {
+ get_frame_saved_regs (fi)[D3_REGNUM] = get_frame_base (fi) + offset;
+ offset += 4;
+ }
+ if (movm_args & movm_d2_bit)
+ {
+ get_frame_saved_regs (fi)[D2_REGNUM] = get_frame_base (fi) + offset;
+ offset += 4;
+ }
+ if (AM33_MODE)
+ {
+ if (movm_args & movm_exother_bit)
+ {
+ get_frame_saved_regs (fi)[MCVF_REGNUM] = get_frame_base (fi) + offset;
+ get_frame_saved_regs (fi)[MCRL_REGNUM] = get_frame_base (fi) + offset + 4;
+ get_frame_saved_regs (fi)[MCRH_REGNUM] = get_frame_base (fi) + offset + 8;
+ get_frame_saved_regs (fi)[MDRQ_REGNUM] = get_frame_base (fi) + offset + 12;
+ get_frame_saved_regs (fi)[E0_REGNUM + 1] = get_frame_base (fi) + offset + 16;
+ get_frame_saved_regs (fi)[E0_REGNUM + 0] = get_frame_base (fi) + offset + 20;
+ offset += 24;
+ }
+ if (movm_args & movm_exreg1_bit)
+ {
+ get_frame_saved_regs (fi)[E0_REGNUM + 7] = get_frame_base (fi) + offset;
+ get_frame_saved_regs (fi)[E0_REGNUM + 6] = get_frame_base (fi) + offset + 4;
+ get_frame_saved_regs (fi)[E0_REGNUM + 5] = get_frame_base (fi) + offset + 8;
+ get_frame_saved_regs (fi)[E0_REGNUM + 4] = get_frame_base (fi) + offset + 12;
+ offset += 16;
+ }
+ if (movm_args & movm_exreg0_bit)
+ {
+ get_frame_saved_regs (fi)[E0_REGNUM + 3] = get_frame_base (fi) + offset;
+ get_frame_saved_regs (fi)[E0_REGNUM + 2] = get_frame_base (fi) + offset + 4;
+ offset += 8;
+ }
+ }
+}
/* Set offsets of registers saved by movm instruction.
This is a helper function for mn10300_analyze_prologue. */
@@ -399,6 +515,8 @@ mn10300_analyze_prologue (struct frame_i
unsigned char buf[4];
int status, movm_args = 0;
char *name;
+ unsigned char regnum;
+ unsigned long regmask = 0;
/* Use the PC in the frame if it's provided to look up the
start of this function. */
@@ -519,6 +637,145 @@ mn10300_analyze_prologue (struct frame_i
}
}
+ if (AM33_MODE == 2)
+ {
+ /* Determine if any floating point registers are to be saved.
+ Look for one of the following three prologue formats:
+
+ [movm [regs],(sp)] [movm [regs],(sp)] [movm [regs],(sp)]
+
+ add -SIZE,sp add -SIZE,sp add -SIZE,sp
+ fmov fs#,(sp) mov sp,a0/a1 mov sp,a0/a1
+ fmov fs#,(#,sp) fmov fs#,(a0/a1+) add SIZE2,a0/a1
+ ... ... fmov fs#,(a0/a1+)
+ ... ... ...
+ fmov fs#,(#,sp) fmov fs#,(a0/a1+) fmov fs#,(a0/a1+)
+
+ [mov sp,a3] [mov sp,a3]
+ [add -SIZE2,sp] [add -SIZE2,sp] */
+
+ /* First, look for add -SIZE,sp (i.e. add imm8,sp (0xf8feXX)
+ or add imm16,sp (0xfafeXXXX)
+ or add imm32,sp (0xfcfeXXXXXXXX)) */
+ imm_size = 0;
+ if (buf[0] == 0xf8 && buf[1] == 0xfe)
+ imm_size = 1;
+ else if (buf[0] == 0xfa && buf[1] == 0xfe)
+ imm_size = 2;
+ else if (buf[0] == 0xfc && buf[1] == 0xfe)
+ imm_size = 4;
+ if (imm_size != 0)
+ {
+ /* An "add -#,sp" instruction has been found. "addr + 2 + imm_size"
+ is the address of the next instruction. Don't modify "addr" until
+ the next "floating point prologue" instruction is found. If this
+ is not a prologue that saves floating point registers we need to
+ be able to back out of this bit of code and continue with the
+ prologue analysis. */
+ if (addr + 2 + imm_size < stop)
+ {
+ status = read_memory_nobpt (addr + 2 + imm_size, buf, 3);
+ if (status != 0)
+ {
+ fix_frame_pointer (fi, 0);
+ set_reg_offsets (fi, movm_args, regmask);
+ return (addr);
+ }
+ if ((buf[0] & 0xfc) == 0x3c)
+ {
+ /* Occasionally, especially with C++ code, the "fmov"
+ instructions will be preceded by "mov sp,aN"
+ (aN => a0, a1, a2, or a3).
+
+ This is a one byte instruction: mov sp,aN = 0011 11XX
+ where XX is the register number.
+
+ Skip this instruction by incrementing addr. (We're
+ committed now.) The "fmov" instructions will have the
+ form "fmov fs#,(aN+)" in this case, but that will not
+ necessitate a change in the "fmov" parsing logic below. */
+
+ addr++;
+
+ if ((buf[1] & 0xfc) == 0x20)
+ {
+ /* Occasionally, especially with C++ code compiled with
+ the -fomit-frame-pointer or -O3 options, the
+ "mov sp,aN" instruction will be followed by an
+ "add #,aN" instruction. This indicates the
+ "stack_size", the size of the portion of the stack
+ containing the arguments. This instruction format is:
+ add #,aN = 0010 00XX YYYY YYYY
+ where XX is the register number
+ YYYY YYYY is the constant.
+ Note the size of the stack (as a negative number) in
+ the frame info structure. */
+ if (fi)
+ get_frame_extra_info (fi)->stack_size = -(buf[2]);
+
+ addr += 2;
+ }
+ }
+
+ if ((buf[0] & 0xfc) == 0x3c ||
+ buf[0] == 0xf9 || buf[0] == 0xfb)
+ {
+ /* An "fmov" instruction has been found indicating that this
+ prologue saves floating point registers (or, as described
+ above, a "mov sp,aN" and possible "add #,aN" have been
+ found and we will assume an "fmov" follows). Process the
+ consecutive "fmov" instructions. */
+ for (addr += 2 + imm_size;;addr += imm_size)
+ {
+ /* Read the "fmov" instruction. */
+ if (addr >= stop ||
+ (status = read_memory_nobpt (addr, buf, 4)) != 0)
+ {
+ fix_frame_pointer (fi, 0);
+ set_reg_offsets (fi, movm_args, regmask);
+ return addr;
+ }
+ if (buf[0] != 0xf9 && buf[0] != 0xfb)
+ break;
+
+ /* Get the floating point register number from the
+ 2nd and 3rd bytes of the "fmov" instruction:
+ Machine Code: 0000 00X0 YYYY 0000 =>
+ Regnum: 000X YYYY */
+ regnum = (buf[1] & 0x02) << 3;
+ regnum |= ((buf[2] & 0xf0) >> 4) & 0x0f;
+
+ /* Add this register number to the bit mask of floating
+ point registers that have been saved. */
+ regmask |= 1 << regnum;
+
+ /* Determine the length of this "fmov" instruction.
+ fmov fs#,(sp) => 3 byte instruction
+ fmov fs#,(#,sp) => 4 byte instruction */
+ imm_size = (buf[0] == 0xf9) ? 3 : 4;
+ }
+ }
+ else
+ {
+ /* No "fmov" was found. Reread the two bytes at the original
+ "addr" to reset the state. */
+ status = read_memory_nobpt (addr, buf, 2);
+ if (status != 0)
+ {
+ fix_frame_pointer (fi, 0);
+ set_movm_offsets (fi, movm_args);
+ return addr;
+ }
+ }
+ }
+ /* else the prologue consists entirely of an "add -SIZE,sp"
+ instruction. Handle this below. */
+ }
+ /* else no "add -SIZE,sp" was found indicating no floating point
+ registers are saved in this prologue. Do not increment addr. Pretend
+ this bit of code never happened. */
+ }
+
/* Now see if we set up a frame pointer via "mov sp,a3" */
if (buf[0] == 0x3f)
{
@@ -538,6 +795,9 @@ mn10300_analyze_prologue (struct frame_i
fix_frame_pointer (fi, 0);
/* Note if/where callee saved registers were saved. */
+ if (AM33_MODE == 2)
+ set_reg_offsets (fi, movm_args, regmask);
+ else
set_movm_offsets (fi, movm_args);
return addr;
}
@@ -550,6 +810,9 @@ mn10300_analyze_prologue (struct frame_i
fix_frame_pointer (fi, 0);
/* Note if/where callee saved registers were saved. */
+ if (AM33_MODE == 2)
+ set_reg_offsets (fi, movm_args, regmask);
+ else
set_movm_offsets (fi, movm_args);
return addr;
}
@@ -572,6 +835,9 @@ mn10300_analyze_prologue (struct frame_i
fix_frame_pointer (fi, 0);
/* Note if/where callee saved registers were saved. */
+ if (AM33_MODE == 2)
+ set_reg_offsets (fi, movm_args, regmask);
+ else
set_movm_offsets (fi, movm_args);
return addr;
}
@@ -595,6 +861,9 @@ mn10300_analyze_prologue (struct frame_i
fix_frame_pointer (fi, 0);
/* Note if/where callee saved registers were saved. */
+ if (AM33_MODE == 2)
+ set_reg_offsets (fi, movm_args, regmask);
+ else
set_movm_offsets (fi, movm_args);
return addr;
}
@@ -612,6 +881,9 @@ mn10300_analyze_prologue (struct frame_i
fix_frame_pointer (fi, stack_size);
/* Note if/where callee saved registers were saved. */
+ if (AM33_MODE == 2)
+ set_reg_offsets (fi, movm_args, regmask);
+ else
set_movm_offsets (fi, movm_args);
return addr;
}
@@ -622,6 +894,9 @@ mn10300_analyze_prologue (struct frame_i
fix_frame_pointer (fi, 0);
/* Note if/where callee saved registers were saved. */
+ if (AM33_MODE == 2)
+ set_reg_offsets (fi, movm_args, regmask);
+ else
set_movm_offsets (fi, movm_args);
return addr;
}
@@ -996,6 +1271,10 @@ mn10300_dwarf2_reg_to_regnum (int dwarf2
static int dwarf2_to_gdb[] = {
0, 1, 2, 3, 4, 5, 6, 7, -1, 8,
15, 16, 17, 18, 19, 20, 21, 22
+ , 32, 33, 34, 35, 36, 37, 38, 39
+ , 40, 41, 42, 43, 44, 45, 46, 47
+ , 48, 49, 50, 51, 52, 53, 54, 55
+ , 56, 57, 58, 59, 60, 61, 62, 63
};
int gdb;
@@ -1067,6 +1346,8 @@ mn10300_do_registers_info (int regnum, i
int c;
int printing = 0;
int padding = 0;
+ if (!fpregs && FP0_REGNUM >= 0 && r >= FP0_REGNUM)
+ break;
for (c = r; c < r + nr_in_row; c++)
{
const char *name = REGISTER_NAME (c);
@@ -1110,6 +1391,49 @@ mn10300_dump_tdep (struct gdbarch *curre
tdep->am33_mode);
}
+/* Fetch, and possibly build, an appropriate link_map_offsets structure
+ for mn10300 linux targets using the struct offsets defined in <link.h>.
+ Note, however, that link.h is not actually referred to in this file.
+ Instead, the relevant structs offsets were obtained from examining
+ link.h. (We can't refer to link.h from this file because the host
+ system won't necessarily have it, or if it does, the structs which
+ it defines will refer to the host system, not the target.) */
+
+struct link_map_offsets *
+mn10300_linux_svr4_fetch_link_map_offsets (void)
+{
+ static struct link_map_offsets lmo;
+ static struct link_map_offsets *lmp = 0;
+
+ if (lmp == 0)
+ {
+ lmp = &lmo;
+
+ lmo.r_debug_size = 8; /* Actual size is 20, but this is all we
+ need. */
+
+ lmo.r_map_offset = 4;
+ lmo.r_map_size = 4;
+
+ lmo.link_map_size = 20; /* Might be larger, but this is all we
+ need. */
+
+ lmo.l_addr_offset = 0;
+ lmo.l_addr_size = 4;
+
+ lmo.l_name_offset = 4;
+ lmo.l_name_size = 4;
+
+ lmo.l_next_offset = 12;
+ lmo.l_next_size = 4;
+
+ lmo.l_prev_offset = 16;
+ lmo.l_prev_size = 4;
+ }
+
+ return lmp;
+}
+
static struct gdbarch *
mn10300_gdbarch_init (struct gdbarch_info info,
struct gdbarch_list *arches)
@@ -1146,6 +1470,11 @@ mn10300_gdbarch_init (struct gdbarch_inf
register_name = am33_register_name;
num_regs = 32;
break;
+ case bfd_mach_am33_2:
+ register_name = am33_2_register_name;
+ am33_mode = 2;
+ num_regs = 64;
+ break;
default:
internal_error (__FILE__, __LINE__,
"mn10300_gdbarch_init: Unknown mn10300 variant");
@@ -1169,6 +1498,7 @@ mn10300_gdbarch_init (struct gdbarch_inf
set_gdbarch_pc_regnum (gdbarch, 9);
set_gdbarch_deprecated_fp_regnum (gdbarch, 31);
set_gdbarch_virtual_frame_pointer (gdbarch, mn10300_virtual_frame_pointer);
+ set_gdbarch_fp0_regnum (gdbarch, 32);
/* Breakpoints. */
set_gdbarch_breakpoint_from_pc (gdbarch, mn10300_breakpoint_from_pc);
[-- Attachment #3: Type: text/plain, Size: 289 bytes --]
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2003-07-10 3:10 AM33/2.0 support for mn10300-elf Alexandre Oliva
@ 2003-07-10 3:31 ` Alexandre Oliva
2003-07-10 4:59 ` Alexandre Oliva
2003-07-10 4:57 ` Alexandre Oliva
2003-08-02 14:26 ` Andrew Cagney
2 siblings, 1 reply; 12+ messages in thread
From: Alexandre Oliva @ 2003-07-10 3:31 UTC (permalink / raw)
To: gdb-patches, bug-dejagnu
[-- Attachment #1: Type: text/plain, Size: 437 bytes --]
On Jul 10, 2003, Alexandre Oliva <aoliva@redhat.com> wrote:
> This patch introduces support for AM33/2.0, that adds a
> single-precision floating-point unit to AM33. The GCC and binutils
> corresponding patches are already in the corresponding CVS trees;
> newlib has just been posted for review. Ok to install?
These are the dejagnu bits, posted separately for convenience of the
DejaGNU maintainer :-) Ok for the GDB repository?
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: dejagnu-am33-2.patch --]
[-- Type: text/x-patch, Size: 1159 bytes --]
Index: dejagnu/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2000-11-21 Drew Moseley <dmoseley@redhat.com>
* baseboards/mn10300-cygmon.exp: Use the am33-2 flag for the
ASB2303 board.
2000-08-10 Drew Moseley <dmoseley@cygnus.com>
* baseboards/mn10300-cygmon.exp: Added support for Cygmon based ASB2303 board.
Index: dejagnu/baseboards/mn10300-cygmon.exp
===================================================================
RCS file: /cvs/uberbaum/dejagnu/baseboards/mn10300-cygmon.exp,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mn10300-cygmon.exp
--- dejagnu/baseboards/mn10300-cygmon.exp 9 Nov 1999 01:28:42 -0000 1.1.1.1
+++ dejagnu/baseboards/mn10300-cygmon.exp 9 Jul 2003 22:55:32 -0000
@@ -15,6 +15,9 @@ set_board_info ldflags "[libgloss_link_
# CygMON linker script.
set_board_info ldscript "-Teval.ld"
+if {[string compare [board_info $board boardtype] "asb2303"] == 0} {
+ set_board_info ldflags "[libgloss_link_flags] [newlib_link_flags] [board_info $board addl_link_flags] -mno-crt0 -mam33-2";
+ set_board_info ldscript "-mam33-2 -Tasb2303.ld"
# Standard remote protocol.
set_board_info gdb_protocol "remote";
[-- Attachment #3: Type: text/plain, Size: 289 bytes --]
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2003-07-10 3:10 AM33/2.0 support for mn10300-elf Alexandre Oliva
2003-07-10 3:31 ` Alexandre Oliva
@ 2003-07-10 4:57 ` Alexandre Oliva
2003-08-02 14:26 ` Andrew Cagney
2 siblings, 0 replies; 12+ messages in thread
From: Alexandre Oliva @ 2003-07-10 4:57 UTC (permalink / raw)
To: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 403 bytes --]
On Jul 10, 2003, Alexandre Oliva <aoliva@redhat.com> wrote:
> This patch introduces support for AM33/2.0, that adds a
> single-precision floating-point unit to AM33. The GCC and binutils
> corresponding patches are already in the corresponding CVS trees;
> newlib has just been posted for review. Ok to install?
And this is the patch that introduces am33_2.0-unknown-linux-gnu
support in GDB. Ok?
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: gdb-am33linux.patch --]
[-- Type: text/x-patch, Size: 6217 bytes --]
Index: sim/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2001-08-07 Michael Keezer <mkeezer@redhat.com>
* configure.in (target): Add am33_2.0 to mn10300 case
* configure: Rebuild.
Index: sim/configure
===================================================================
RCS file: /cvs/uberbaum/sim/configure,v
retrieving revision 1.10
diff -u -p -r1.10 configure
--- sim/configure 13 Apr 2003 16:44:57 -0000 1.10
+++ sim/configure 10 Jul 2003 04:13:00 -0000
@@ -1441,7 +1441,7 @@ case "${target}" in
only_if_gcc=yes
extra_subdirs="${extra_subdirs} igen"
;;
- mn10300*-*-*)
+ mn10300*-*-* | am33_2.0*-*-*)
# The mn10300 simulator can only be compiled by gcc.
sim_target=mn10300
only_if_gcc=yes
Index: sim/configure.in
===================================================================
RCS file: /cvs/uberbaum/sim/configure.in,v
retrieving revision 1.11
diff -u -p -r1.11 configure.in
--- sim/configure.in 13 Apr 2003 16:44:57 -0000 1.11
+++ sim/configure.in 10 Jul 2003 04:13:00 -0000
@@ -80,7 +80,7 @@ case "${target}" in
only_if_gcc=yes
extra_subdirs="${extra_subdirs} igen"
;;
- mn10300*-*-*)
+ mn10300*-*-* | am33_2.0*-*-*)
# The mn10300 simulator can only be compiled by gcc.
sim_target=mn10300
only_if_gcc=yes
Index: gdb/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2002-02-25 Jackie Smith Cashion <jsmith@redhat.com>
* configure.tgt (am33_2.0*-*-*_): Remove unused target.
From Kevin Buettner <kevinb@redhat.com>:
* configure.tgt (am33_2.0*-*-linux*): New target.
* mn10300-tdep.c (solib-svr4.h): Include.
(mn10300_linux_svr4_fetch_link_map_offsets): New function.
* config/mn10300/linux.mt: New file.
* config/mn10300/tm-linux.h: New file.
2001-08-07 Michael Keezer <mkeezer@redhat.com>
* configure.tgt: put blank line after target_cpu case.
2001-08-07 Michael Keezer <mkeezer@redhat.com>
* configure.tgt: Add am33_2.0 target_cpu & target.
Index: gdb/configure.tgt
===================================================================
RCS file: /cvs/uberbaum/gdb/configure.tgt,v
retrieving revision 1.107
diff -u -p -r1.107 configure.tgt
--- gdb/configure.tgt 13 Jun 2003 17:49:49 -0000 1.107
+++ gdb/configure.tgt 10 Jul 2003 04:13:37 -0000
@@ -12,6 +12,7 @@
case "${target_cpu}" in
+am33_2.0*) gdb_target_cpu=mn10300 ;;
alpha*) gdb_target_cpu=alpha ;;
arm*) gdb_target_cpu=arm ;;
avr*) gdb_target_cpu=avr ;;
@@ -176,6 +177,7 @@ mips*-*-*) gdb_target=embed ;;
# OBSOLETE mn10200-*-*) gdb_target=mn10200 ;;
mn10300-*-*) gdb_target=mn10300 ;;
+am33_2.0*-*-linux*) gdb_target=linux ;;
none-*-*) gdb_target=none ;;
Index: gdb/config/mn10300/linux.mt
===================================================================
RCS file: gdb/config/mn10300/linux.mt
diff -N gdb/config/mn10300/linux.mt
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gdb/config/mn10300/linux.mt 10 Jul 2003 04:13:39 -0000
@@ -0,0 +1,6 @@
+# Target: Matsushita mn10300 running Linux
+TDEPFILES= mn10300-tdep.o solib.o solib-svr4.o
+TM_FILE= tm-linux.h
+
+SIM_OBS = remote-sim.o
+SIM = ../sim/mn10300/libsim.a
Index: gdb/config/mn10300/tm-linux.h
===================================================================
RCS file: gdb/config/mn10300/tm-linux.h
diff -N gdb/config/mn10300/tm-linux.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gdb/config/mn10300/tm-linux.h 10 Jul 2003 04:13:39 -0000
@@ -0,0 +1,60 @@
+/* Target definitions for Matsushita AM33-2 processor running Linux.
+ Copyright 2002
+ Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+/* The mn10300 target is fully multi-arched and, therefore, does not have
+ a "tm" file. The mn10300 target does not support Linux shared libraries.
+ At this time shared library support and full multi-arch support are
+ mutually exclusive.
+
+ The AM33-2 target does support Linux shared libraries and, therefore, must
+ be only partially multi-arched. This allows the specification of this "tm"
+ file from which the generic tm-linux.h is included (which, in turn,
+ includes the required solib.h).
+
+ Notice that gdb/configure.tgt sets the following:
+
+ target_cpu == mn10300: target_cpu == am33_2.0*-*-linux*:
+ gdb_target_cpu=mn10300 gdb_target_cpu=mn10300
+ gdb_target=mn10300 gdb_target=linux
+ gdb_target == mn10300: gdb_target == linux:
+ gdb_multi_arch=yes gdb_multi_arch=<undefined>
+
+This causes the mn10300 target to look in gdb/config/mn10300 for mn10300.mt
+and specifies that this target is fully multi-arched. And it causes the AM33-2
+target to look in that same directory for linux.mt. Since gdb_multi_arch is
+not defined for this target, linux.mt can specify the TM_FILE symbol pointing
+to gdb/config/mn10300/tm-linux.h (this file). */
+
+/* Pull in generic linux definitions. */
+#include "tm-linux.h"
+
+/* Set the multi-arch level to "partial". */
+#define GDB_MULTI_ARCH 1
+
+/* Use target_specific function to define link map offsets.
+ Specify this function here with a #define instead of calling
+ set_solib_svr4_fetch_link_map_offsets in mn10300_gdbarch_init.
+ This keeps this functionality isolated to the am33_2.0-linux-gnu target.
+ mn10300-elf targets cannot call set_solib_svr4_fetch_link_map_offsets
+ because solib-svr4.c is not linked in for them. */
+
+extern struct link_map_offsets *mn10300_linux_svr4_fetch_link_map_offsets (void);
+#define SVR4_FETCH_LINK_MAP_OFFSETS() mn10300_linux_svr4_fetch_link_map_offsets ()
[-- Attachment #3: Type: text/plain, Size: 289 bytes --]
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2003-07-10 3:31 ` Alexandre Oliva
@ 2003-07-10 4:59 ` Alexandre Oliva
2003-07-16 16:05 ` [Bug-dejagnu] " Rob Savoye
0 siblings, 1 reply; 12+ messages in thread
From: Alexandre Oliva @ 2003-07-10 4:59 UTC (permalink / raw)
To: gdb-patches; +Cc: bug-dejagnu
[-- Attachment #1: Type: text/plain, Size: 788 bytes --]
On Jul 10, 2003, Alexandre Oliva <aoliva@redhat.com> wrote:
> On Jul 10, 2003, Alexandre Oliva <aoliva@redhat.com> wrote:
>> This patch introduces support for AM33/2.0, that adds a
>> single-precision floating-point unit to AM33. The GCC and binutils
>> corresponding patches are already in the corresponding CVS trees;
>> newlib has just been posted for review. Ok to install?
> These are the dejagnu bits, posted separately for convenience of the
> DejaGNU maintainer :-) Ok for the GDB repository?
And here's a patch for am33_2.0-unknown-linux-gnu. It seems to be
lacking some love (setting compiler the way it does is odd, but I'm no
expert in this kind of file), and I'm not entirely sure we actually
use it any longer, but I thought I'd post it anyway. Should I put it
in?
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: dejagnu-am33linux.patch --]
[-- Type: text/x-patch, Size: 1480 bytes --]
Index: dejagnu/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2002-02-25 Jackie Smith Cashion <jsmith@redhat.com>
* baseboards/am33_2.0-libremote.exp: New file.
Index: dejagnu/baseboards/am33_2.0-libremote.exp
===================================================================
RCS file: dejagnu/baseboards/am33_2.0-libremote.exp
diff -N dejagnu/baseboards/am33_2.0-libremote.exp
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ dejagnu/baseboards/am33_2.0-libremote.exp 10 Jul 2003 04:13:22 -0000
@@ -0,0 +1,32 @@
+# This file is useful for gdb testing with libremote on an embedded linux
+# board. In this case a Matsushita ASB2305 AM33 v2.0 board.
+
+load_generic_config "libremote_server";
+
+process_multilib_options "";
+
+# The default compiler for this target.
+#set_board_info compiler "[find_gcc]";
+set_board_info compiler "am33_2.0-linux-gnu-gcc";
+
+# We will be using the standard GDB remote protocol
+set_board_info gdb_protocol "remote"
+
+# Use techniques appropriate to a stub
+set_board_info use_gdb_stub 1;
+set_board_info gdb,gdb_stub 1;
+
+# This gdbserver can only run a process once per session.
+set_board_info gdb,do_reload_on_run 1;
+
+# There's no support for argument-passing (yet).
+set_board_info noargs 1
+
+# Can't do input (or output) in the current gdbserver.
+set_board_info gdb,noinferiorio 1
+
+# Can't do hardware watchpoints, in general
+set_board_info gdb,no_hardware_watchpoints 1;
+
+# New
+set_board_info gdb,nosignals 1
[-- Attachment #3: Type: text/plain, Size: 289 bytes --]
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Bug-dejagnu] Re: AM33/2.0 support for mn10300-elf
2003-07-10 4:59 ` Alexandre Oliva
@ 2003-07-16 16:05 ` Rob Savoye
2003-07-22 20:02 ` Alexandre Oliva
0 siblings, 1 reply; 12+ messages in thread
From: Rob Savoye @ 2003-07-16 16:05 UTC (permalink / raw)
To: Alexandre Oliva; +Cc: gdb-patches, bug-dejagnu
On Thu, Jul 10, 2003 at 01:59:48AM -0300, Alexandre Oliva wrote:
> > These are the dejagnu bits, posted separately for convenience of the
> > DejaGNU maintainer :-) Ok for the GDB repository?
>
> And here's a patch for am33_2.0-unknown-linux-gnu. It seems to be
> lacking some love (setting compiler the way it does is odd, but I'm no
> expert in this kind of file), and I'm not entirely sure we actually
> use it any longer, but I thought I'd post it anyway. Should I put it
> in?
Well, the compiler name *should* really be gotten by transforming the
target name, but I assume there was some reason for hardcoding it ? It looks
like am33_2.0-linux-gnu isn't a standard target-triplet. What does
config.guess return on this target ? find_gcc should have worked.
As I'm guessing almost nobody uses this target, I'll check this into
Savannah 'as is".
- rob -
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Bug-dejagnu] Re: AM33/2.0 support for mn10300-elf
2003-07-16 16:05 ` [Bug-dejagnu] " Rob Savoye
@ 2003-07-22 20:02 ` Alexandre Oliva
0 siblings, 0 replies; 12+ messages in thread
From: Alexandre Oliva @ 2003-07-22 20:02 UTC (permalink / raw)
To: Rob Savoye; +Cc: gdb-patches, bug-dejagnu
On Jul 16, 2003, Rob Savoye <rob@welcomehome.org> wrote:
> Well, the compiler name *should* really be gotten by transforming the
> target name
Yup.
> but I assume there was some reason for hardcoding it?
I've no idea :-(
> It looks like am33_2.0-linux-gnu isn't a standard
> target-triplet. What does config.guess return on this target?
Err... I'm not sure config.guess supports it at all (we have mostly
only cross-built to it), but config.sub (as in ftp.gnu.org)
recognizes am33_2.0-unkwnon-linux-gnu as a canonical form.
> As I'm guessing almost nobody uses this target, I'll check this into
> Savannah 'as is".
Thanks.
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2003-07-10 3:10 AM33/2.0 support for mn10300-elf Alexandre Oliva
2003-07-10 3:31 ` Alexandre Oliva
2003-07-10 4:57 ` Alexandre Oliva
@ 2003-08-02 14:26 ` Andrew Cagney
2004-06-21 13:59 ` Alexandre Oliva
` (2 more replies)
2 siblings, 3 replies; 12+ messages in thread
From: Andrew Cagney @ 2003-08-02 14:26 UTC (permalink / raw)
To: Alexandre Oliva; +Cc: gdb-patches
Sigh, separate SIM and GDB patches might have been easier.
For the simulator, two refinements:
+void fpu_disabled_exception PARAMS ((SIM_DESC, sim_cpu *,
address_word));
The code needs to use strict ISO C. It might be easier to just convert
everything.
+ store_word (addr + 4, data.high);
+}
#endif /* not WITH_COMMON */
The MN10300 switched to sim/common long ago, the #if !WITH_COMMON code
should be deleted.
they can both be considered pretty "obvious".
Other than that, its approved.
--
> +/* Fetch, and possibly build, an appropriate link_map_offsets structure
> + for mn10300 linux targets using the struct offsets defined in <link.h>.
> + Note, however, that link.h is not actually referred to in this file.
> + Instead, the relevant structs offsets were obtained from examining
> + link.h. (We can't refer to link.h from this file because the host
> + system won't necessarily have it, or if it does, the structs which
> + it defines will refer to the host system, not the target.) */
> +
> +struct link_map_offsets *
> +mn10300_linux_svr4_fetch_link_map_offsets (void)
> +{
This really belongs in mn10300-linux-tdep.c. I also suspect that stuff
is also missing from the patch (tm-mn10300.h?), as the function doesn't
appear to be called? Does this need an ABI sniffer (see osabi.[sh])?
> + if (AM33_MODE == 2)
I'm guessing this is a macro that relies on global state. New code
instead accesses everything via parameters. Here, something like:
fi->arch->tdep->am33_mode
which, in GDB, is written as:
gdbarch_tdep (get_frame_arch (fi))->am33_mode.
> + get_frame_saved_regs (fi)[LAR_REGNUM] = get_frame_base (fi) + offset + 4;
See: http://sources.redhat.com/gdb/current/ari/
The method get_frame_saved_regs() is obsolete. Changes should be
decreasing, not increasing that function's usage count :-/ The new code
will need to be written in a way that avoids this method. The best way
of doing this is to convert it to convert that section of the code to
the new unwind mechanism.
> 15, 16, 17, 18, 19, 20, 21, 22
> + , 32, 33, 34, 35, 36, 37, 38, 39
> + , 40, 41, 42, 43, 44, 45, 46, 47
GNU coding style?
+ set_gdbarch_fp0_regnum (gdbarch, 32);
Is this needed? Adding a field to the am33's tdep struct would be
better. FP0_REGNUM is almost, but not quite deprecated.
sorry,
Andrew
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2003-08-02 14:26 ` Andrew Cagney
@ 2004-06-21 13:59 ` Alexandre Oliva
2004-06-25 21:41 ` Andrew Cagney
2004-06-26 22:00 ` Alexandre Oliva
2004-06-26 22:00 ` Alexandre Oliva
2004-06-26 22:18 ` Alexandre Oliva
2 siblings, 2 replies; 12+ messages in thread
From: Alexandre Oliva @ 2004-06-21 13:59 UTC (permalink / raw)
To: Andrew Cagney; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 531 bytes --]
On Aug 2, 2003, Andrew Cagney <ac131313@redhat.com> wrote:
> + store_word (addr + 4, data.high);
> +}
> #endif /* not WITH_COMMON */
> The MN10300 switched to sim/common long ago, the #if !WITH_COMMON code
> should be deleted.
> they can both be considered pretty "obvious".
> Other than that, its approved.
Here's a patch that removes the non-COMMON bits from the mn10300 sim.
Ok to install them, and then the AM33/2.0 sim patches I posted back on
Jul 10, 2003, with the other refinements you requested on Aug 2, 2003?
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: mn10300-sim-common.patch --]
[-- Type: text/x-patch, Size: 25162 bytes --]
Index: sim/mn10300/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* configure.in: Use common simulator always. Don't subst sim_gen
nor mn10300_common.
* configure: Rebuilt.
* Makefile.in (WITHOUT_COMMON_OBJS, WITHOUT_COMMON_INTERP_DEP,
WITHOUT_COMMON_RUN_OBJS): Remove.
(WITH_COMMON_OBJS): Rename to MN10300_OBJS.
(WITH_COMMON_INTERP_DEP): Rename to MN10300_INTERP_DEP.
(WITH_COMMON_RUN_OBJS): Rename to SIM_RUN_OBJS.
(SIM_EXTRA_CFLAGS): Don't use @sim_gen@.
* interp.c: Remove non-common bits.
* mn10300_sim.h: Likewise.
Index: sim/mn10300/Makefile.in
===================================================================
RCS file: /cvs/uberbaum/./sim/mn10300/Makefile.in,v
retrieving revision 1.6
diff -u -p -r1.6 Makefile.in
--- sim/mn10300/Makefile.in 28 Nov 2002 18:08:26 -0000 1.6
+++ sim/mn10300/Makefile.in 21 Jun 2004 13:55:31 -0000
@@ -1,5 +1,5 @@
# Makefile template for Configure for the mn10300 sim library.
-# Copyright (C) 1996, 1997, 2000, 2001 Free Software Foundation, Inc.
+# Copyright (C) 1996, 1997, 2000, 2001, 2004 Free Software Foundation, Inc.
# Written by Cygnus Support.
#
# This program is free software; you can redistribute it and/or modify
@@ -18,9 +18,7 @@
## COMMON_PRE_CONFIG_FRAG
-WITHOUT_COMMON_OBJS = table.o simops.o sim-load.o
-WITHOUT_COMMON_INTERP_DEP = table.c
-WITH_COMMON_OBJS = \
+MN10300_OBJS = \
itable.o semantics.o idecode.o icache.o engine.o irun.o support.o \
$(SIM_NEW_COMMON_OBJS) \
op_utils.o \
@@ -31,17 +29,12 @@ WITH_COMMON_OBJS = \
sim-reason.o \
sim-stop.o \
dv-sockser.o
-WITH_COMMON_INTERP_DEP =
-
-MN10300_OBJS = $(@mn10300_common@_COMMON_OBJS)
-MN10300_INTERP_DEP = $(@mn10300_common@_COMMON_INTERP_DEP)
+MN10300_INTERP_DEP =
SIM_OBJS = $(MN10300_OBJS) interp.o
# List of main object files for `run'.
-WITHOUT_COMMON_RUN_OBJS = run.o
-WITH_COMMON_RUN_OBJS = nrun.o
-SIM_RUN_OBJS = $(@mn10300_common@_COMMON_RUN_OBJS)
+SIM_RUN_OBJS = nrun.o
SIM_EXTRA_CLEAN = clean-extra
# Extra dependencies for "sim-main.h"
@@ -53,7 +46,7 @@ NL_TARGET = -DNL_TARGET_mn10300
INCLUDE = mn10300_sim.h $(srcdir)/../../include/gdb/callback.h
# List of extra flags to always pass to $(CC).
-SIM_EXTRA_CFLAGS = @sim_gen@ -DPOLL_QUIT_INTERVAL=0x20
+SIM_EXTRA_CFLAGS = -DPOLL_QUIT_INTERVAL=0x20
## COMMON_POST_CONFIG_FRAG
Index: sim/mn10300/configure.in
===================================================================
RCS file: /cvs/uberbaum/./sim/mn10300/configure.in,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 configure.in
--- sim/mn10300/configure.in 16 Apr 1999 01:35:07 -0000 1.1.1.1
+++ sim/mn10300/configure.in 21 Jun 2004 13:55:33 -0000
@@ -18,20 +18,4 @@ SIM_AC_OPTION_HARDWARE(yes,,mn103cpu mn1
AC_CHECK_FUNCS(time chmod utime fork execve execv chown)
AC_CHECK_HEADERS(unistd.h stdlib.h string.h strings.h utime.h time.h)
-#
-# Enable common
-#
-AC_ARG_ENABLE(sim-common,
-[ --enable-sim-common Enable common simulator],
-[case "${enableval}" in
- yes) sim_gen="-DWITH_COMMON=1"; mn10300_common="WITH";;
- no) sim_gen="-DWITH_COMMON=0"; mn10300_common="WITHOUT";;
- *) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-common"); sim_gen="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_gen" != x""; then
- echo "Setting sim_common = $sim_common" 6>&1
-fi],[sim_gen="-DWITH_COMMON=1"; mn10300_common="WITH"])dnl
-AC_SUBST(sim_gen)
-AC_SUBST(mn10300_common)
-
SIM_AC_OUTPUT
Index: sim/mn10300/interp.c
===================================================================
RCS file: /cvs/uberbaum/./sim/mn10300/interp.c,v
retrieving revision 1.2
diff -u -p -r1.2 interp.c
--- sim/mn10300/interp.c 27 Feb 2003 23:26:34 -0000 1.2
+++ sim/mn10300/interp.c 21 Jun 2004 13:55:34 -0000
@@ -1,12 +1,8 @@
#include <signal.h>
-#if WITH_COMMON
#include "sim-main.h"
#include "sim-options.h"
#include "sim-hw.h"
-#else
-#include "mn10300_sim.h"
-#endif
#include "sysdep.h"
#include "bfd.h"
@@ -86,857 +82,6 @@ static const OPTION mn10300_options[] =
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
-#if WITH_COMMON
-#else
-static void dispatch PARAMS ((uint32, uint32, int));
-static long hash PARAMS ((long));
-static void init_system PARAMS ((void));
-
-static SIM_OPEN_KIND sim_kind;
-static char *myname;
-#define MAX_HASH 127
-
-struct hash_entry
-{
- struct hash_entry *next;
- long opcode;
- long mask;
- struct simops *ops;
-#ifdef HASH_STAT
- unsigned long count;
-#endif
-};
-
-static int max_mem = 0;
-struct hash_entry hash_table[MAX_HASH+1];
-
-
-/* This probably doesn't do a very good job at bucket filling, but
- it's simple... */
-static INLINE long
-hash(insn)
- long insn;
-{
- /* These are one byte insns, we special case these since, in theory,
- they should be the most heavily used. */
- if ((insn & 0xffffff00) == 0)
- {
- switch (insn & 0xf0)
- {
- case 0x00:
- return 0x70;
-
- case 0x40:
- return 0x71;
-
- case 0x10:
- return 0x72;
-
- case 0x30:
- return 0x73;
-
- case 0x50:
- return 0x74;
-
- case 0x60:
- return 0x75;
-
- case 0x70:
- return 0x76;
-
- case 0x80:
- return 0x77;
-
- case 0x90:
- return 0x78;
-
- case 0xa0:
- return 0x79;
-
- case 0xb0:
- return 0x7a;
-
- case 0xe0:
- return 0x7b;
-
- default:
- return 0x7c;
- }
- }
-
- /* These are two byte insns */
- if ((insn & 0xffff0000) == 0)
- {
- if ((insn & 0xf000) == 0x2000
- || (insn & 0xf000) == 0x5000)
- return ((insn & 0xfc00) >> 8) & 0x7f;
-
- if ((insn & 0xf000) == 0x4000)
- return ((insn & 0xf300) >> 8) & 0x7f;
-
- if ((insn & 0xf000) == 0x8000
- || (insn & 0xf000) == 0x9000
- || (insn & 0xf000) == 0xa000
- || (insn & 0xf000) == 0xb000)
- return ((insn & 0xf000) >> 8) & 0x7f;
-
- if ((insn & 0xff00) == 0xf000
- || (insn & 0xff00) == 0xf100
- || (insn & 0xff00) == 0xf200
- || (insn & 0xff00) == 0xf500
- || (insn & 0xff00) == 0xf600)
- return ((insn & 0xfff0) >> 4) & 0x7f;
-
- if ((insn & 0xf000) == 0xc000)
- return ((insn & 0xff00) >> 8) & 0x7f;
-
- return ((insn & 0xffc0) >> 6) & 0x7f;
- }
-
- /* These are three byte insns. */
- if ((insn & 0xff000000) == 0)
- {
- if ((insn & 0xf00000) == 0x000000)
- return ((insn & 0xf30000) >> 16) & 0x7f;
-
- if ((insn & 0xf00000) == 0x200000
- || (insn & 0xf00000) == 0x300000)
- return ((insn & 0xfc0000) >> 16) & 0x7f;
-
- if ((insn & 0xff0000) == 0xf80000)
- return ((insn & 0xfff000) >> 12) & 0x7f;
-
- if ((insn & 0xff0000) == 0xf90000)
- return ((insn & 0xfffc00) >> 10) & 0x7f;
-
- return ((insn & 0xff0000) >> 16) & 0x7f;
- }
-
- /* These are four byte or larger insns. */
- if ((insn & 0xf0000000) == 0xf0000000)
- return ((insn & 0xfff00000) >> 20) & 0x7f;
-
- return ((insn & 0xff000000) >> 24) & 0x7f;
-}
-
-static INLINE void
-dispatch (insn, extension, length)
- uint32 insn;
- uint32 extension;
- int length;
-{
- struct hash_entry *h;
-
- h = &hash_table[hash(insn)];
-
- while ((insn & h->mask) != h->opcode
- || (length != h->ops->length))
- {
- if (!h->next)
- {
- (*mn10300_callback->printf_filtered) (mn10300_callback,
- "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC);
- exit(1);
- }
- h = h->next;
- }
-
-
-#ifdef HASH_STAT
- h->count++;
-#endif
-
- /* Now call the right function. */
- (h->ops->func)(insn, extension);
- PC += length;
-}
-
-void
-sim_size (power)
- int power;
-
-{
- if (State.mem)
- free (State.mem);
-
- max_mem = 1 << power;
- State.mem = (uint8 *) calloc (1, 1 << power);
- if (!State.mem)
- {
- (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n");
- exit (1);
- }
-}
-
-static void
-init_system ()
-{
- if (!State.mem)
- sim_size(19);
-}
-
-int
-sim_write (sd, addr, buffer, size)
- SIM_DESC sd;
- SIM_ADDR addr;
- unsigned char *buffer;
- int size;
-{
- int i;
-
- init_system ();
-
- for (i = 0; i < size; i++)
- store_byte (addr + i, buffer[i]);
-
- return size;
-}
-
-/* Compare two opcode table entries for qsort. */
-static int
-compare_simops (arg1, arg2)
- const PTR arg1;
- const PTR arg2;
-{
- unsigned long code1 = ((struct simops *)arg1)->opcode;
- unsigned long code2 = ((struct simops *)arg2)->opcode;
-
- if (code1 < code2)
- return -1;
- if (code2 < code1)
- return 1;
- return 0;
-}
-
-SIM_DESC
-sim_open (kind, cb, abfd, argv)
- SIM_OPEN_KIND kind;
- host_callback *cb;
- struct bfd *abfd;
- char **argv;
-{
- struct simops *s;
- struct hash_entry *h;
- char **p;
- int i;
-
- mn10300_callback = cb;
-
- /* Sort the opcode array from smallest opcode to largest.
- This will generally improve simulator performance as the smaller
- opcodes are generally preferred to the larger opcodes. */
- for (i = 0, s = Simops; s->func; s++, i++)
- ;
- qsort (Simops, i, sizeof (Simops[0]), compare_simops);
-
- sim_kind = kind;
- myname = argv[0];
-
- for (p = argv + 1; *p; ++p)
- {
- if (strcmp (*p, "-E") == 0)
- ++p; /* ignore endian spec */
- else
-#ifdef DEBUG
- if (strcmp (*p, "-t") == 0)
- mn10300_debug = DEBUG;
- else
-#endif
- (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p);
- }
-
- /* put all the opcodes in the hash table */
- for (s = Simops; s->func; s++)
- {
- h = &hash_table[hash(s->opcode)];
-
- /* go to the last entry in the chain */
- while (h->next)
- {
- /* Don't insert the same opcode more than once. */
- if (h->opcode == s->opcode
- && h->mask == s->mask
- && h->ops == s)
- break;
- else
- h = h->next;
- }
-
- /* Don't insert the same opcode more than once. */
- if (h->opcode == s->opcode
- && h->mask == s->mask
- && h->ops == s)
- continue;
-
- if (h->ops)
- {
- h->next = calloc(1,sizeof(struct hash_entry));
- h = h->next;
- }
- h->ops = s;
- h->mask = s->mask;
- h->opcode = s->opcode;
-#if HASH_STAT
- h->count = 0;
-#endif
- }
-
-
- /* fudge our descriptor for now */
- return (SIM_DESC) 1;
-}
-
-
-void
-sim_close (sd, quitting)
- SIM_DESC sd;
- int quitting;
-{
- /* nothing to do */
-}
-
-void
-sim_set_profile (n)
- int n;
-{
- (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n);
-}
-
-void
-sim_set_profile_size (n)
- int n;
-{
- (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n);
-}
-
-int
-sim_stop (sd)
- SIM_DESC sd;
-{
- return 0;
-}
-
-void
-sim_resume (sd, step, siggnal)
- SIM_DESC sd;
- int step, siggnal;
-{
- uint32 inst;
- reg_t oldpc;
- struct hash_entry *h;
-
- if (step)
- State.exception = SIGTRAP;
- else
- State.exception = 0;
-
- State.exited = 0;
-
- do
- {
- unsigned long insn, extension;
-
- /* Fetch the current instruction. */
- inst = load_mem_big (PC, 2);
- oldpc = PC;
-
- /* Using a giant case statement may seem like a waste because of the
- code/rodata size the table itself will consume. However, using
- a giant case statement speeds up the simulator by 10-15% by avoiding
- cascading if/else statements or cascading case statements. */
-
- switch ((inst >> 8) & 0xff)
- {
- /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0
- which must be handled specially. */
- case 0x00:
- case 0x04:
- case 0x08:
- case 0x0c:
- case 0x10:
- case 0x11:
- case 0x12:
- case 0x13:
- case 0x14:
- case 0x15:
- case 0x16:
- case 0x17:
- case 0x18:
- case 0x19:
- case 0x1a:
- case 0x1b:
- case 0x1c:
- case 0x1d:
- case 0x1e:
- case 0x1f:
- case 0x3c:
- case 0x3d:
- case 0x3e:
- case 0x3f:
- case 0x40:
- case 0x41:
- case 0x44:
- case 0x45:
- case 0x48:
- case 0x49:
- case 0x4c:
- case 0x4d:
- case 0x50:
- case 0x51:
- case 0x52:
- case 0x53:
- case 0x54:
- case 0x55:
- case 0x56:
- case 0x57:
- case 0x60:
- case 0x61:
- case 0x62:
- case 0x63:
- case 0x64:
- case 0x65:
- case 0x66:
- case 0x67:
- case 0x68:
- case 0x69:
- case 0x6a:
- case 0x6b:
- case 0x6c:
- case 0x6d:
- case 0x6e:
- case 0x6f:
- case 0x70:
- case 0x71:
- case 0x72:
- case 0x73:
- case 0x74:
- case 0x75:
- case 0x76:
- case 0x77:
- case 0x78:
- case 0x79:
- case 0x7a:
- case 0x7b:
- case 0x7c:
- case 0x7d:
- case 0x7e:
- case 0x7f:
- case 0xcb:
- case 0xd0:
- case 0xd1:
- case 0xd2:
- case 0xd3:
- case 0xd4:
- case 0xd5:
- case 0xd6:
- case 0xd7:
- case 0xd8:
- case 0xd9:
- case 0xda:
- case 0xdb:
- case 0xe0:
- case 0xe1:
- case 0xe2:
- case 0xe3:
- case 0xe4:
- case 0xe5:
- case 0xe6:
- case 0xe7:
- case 0xe8:
- case 0xe9:
- case 0xea:
- case 0xeb:
- case 0xec:
- case 0xed:
- case 0xee:
- case 0xef:
- case 0xff:
- insn = (inst >> 8) & 0xff;
- extension = 0;
- dispatch (insn, extension, 1);
- break;
-
- /* Special cases where dm == dn is used to encode a different
- instruction. */
- case 0x80:
- case 0x85:
- case 0x8a:
- case 0x8f:
- case 0x90:
- case 0x95:
- case 0x9a:
- case 0x9f:
- case 0xa0:
- case 0xa5:
- case 0xaa:
- case 0xaf:
- case 0xb0:
- case 0xb5:
- case 0xba:
- case 0xbf:
- insn = inst;
- extension = 0;
- dispatch (insn, extension, 2);
- break;
-
- case 0x81:
- case 0x82:
- case 0x83:
- case 0x84:
- case 0x86:
- case 0x87:
- case 0x88:
- case 0x89:
- case 0x8b:
- case 0x8c:
- case 0x8d:
- case 0x8e:
- case 0x91:
- case 0x92:
- case 0x93:
- case 0x94:
- case 0x96:
- case 0x97:
- case 0x98:
- case 0x99:
- case 0x9b:
- case 0x9c:
- case 0x9d:
- case 0x9e:
- case 0xa1:
- case 0xa2:
- case 0xa3:
- case 0xa4:
- case 0xa6:
- case 0xa7:
- case 0xa8:
- case 0xa9:
- case 0xab:
- case 0xac:
- case 0xad:
- case 0xae:
- case 0xb1:
- case 0xb2:
- case 0xb3:
- case 0xb4:
- case 0xb6:
- case 0xb7:
- case 0xb8:
- case 0xb9:
- case 0xbb:
- case 0xbc:
- case 0xbd:
- case 0xbe:
- insn = (inst >> 8) & 0xff;
- extension = 0;
- dispatch (insn, extension, 1);
- break;
-
- /* The two byte instructions. */
- case 0x20:
- case 0x21:
- case 0x22:
- case 0x23:
- case 0x28:
- case 0x29:
- case 0x2a:
- case 0x2b:
- case 0x42:
- case 0x43:
- case 0x46:
- case 0x47:
- case 0x4a:
- case 0x4b:
- case 0x4e:
- case 0x4f:
- case 0x58:
- case 0x59:
- case 0x5a:
- case 0x5b:
- case 0x5c:
- case 0x5d:
- case 0x5e:
- case 0x5f:
- case 0xc0:
- case 0xc1:
- case 0xc2:
- case 0xc3:
- case 0xc4:
- case 0xc5:
- case 0xc6:
- case 0xc7:
- case 0xc8:
- case 0xc9:
- case 0xca:
- case 0xce:
- case 0xcf:
- case 0xf0:
- case 0xf1:
- case 0xf2:
- case 0xf3:
- case 0xf4:
- case 0xf5:
- case 0xf6:
- insn = inst;
- extension = 0;
- dispatch (insn, extension, 2);
- break;
-
- /* The three byte insns with a 16bit operand in little endian
- format. */
- case 0x01:
- case 0x02:
- case 0x03:
- case 0x05:
- case 0x06:
- case 0x07:
- case 0x09:
- case 0x0a:
- case 0x0b:
- case 0x0d:
- case 0x0e:
- case 0x0f:
- case 0x24:
- case 0x25:
- case 0x26:
- case 0x27:
- case 0x2c:
- case 0x2d:
- case 0x2e:
- case 0x2f:
- case 0x30:
- case 0x31:
- case 0x32:
- case 0x33:
- case 0x34:
- case 0x35:
- case 0x36:
- case 0x37:
- case 0x38:
- case 0x39:
- case 0x3a:
- case 0x3b:
- case 0xcc:
- insn = load_byte (PC);
- insn <<= 16;
- insn |= load_half (PC + 1);
- extension = 0;
- dispatch (insn, extension, 3);
- break;
-
- /* The three byte insns without 16bit operand. */
- case 0xde:
- case 0xdf:
- case 0xf8:
- case 0xf9:
- insn = load_mem_big (PC, 3);
- extension = 0;
- dispatch (insn, extension, 3);
- break;
-
- /* Four byte insns. */
- case 0xfa:
- case 0xfb:
- if ((inst & 0xfffc) == 0xfaf0
- || (inst & 0xfffc) == 0xfaf4
- || (inst & 0xfffc) == 0xfaf8)
- insn = load_mem_big (PC, 4);
- else
- {
- insn = inst;
- insn <<= 16;
- insn |= load_half (PC + 2);
- extension = 0;
- }
- dispatch (insn, extension, 4);
- break;
-
- /* Five byte insns. */
- case 0xcd:
- insn = load_byte (PC);
- insn <<= 24;
- insn |= (load_half (PC + 1) << 8);
- insn |= load_byte (PC + 3);
- extension = load_byte (PC + 4);
- dispatch (insn, extension, 5);
- break;
-
- case 0xdc:
- insn = load_byte (PC);
- insn <<= 24;
- extension = load_word (PC + 1);
- insn |= (extension & 0xffffff00) >> 8;
- extension &= 0xff;
- dispatch (insn, extension, 5);
- break;
-
- /* Six byte insns. */
- case 0xfc:
- case 0xfd:
- insn = (inst << 16);
- extension = load_word (PC + 2);
- insn |= ((extension & 0xffff0000) >> 16);
- extension &= 0xffff;
- dispatch (insn, extension, 6);
- break;
-
- case 0xdd:
- insn = load_byte (PC) << 24;
- extension = load_word (PC + 1);
- insn |= ((extension >> 8) & 0xffffff);
- extension = (extension & 0xff) << 16;
- extension |= load_byte (PC + 5) << 8;
- extension |= load_byte (PC + 6);
- dispatch (insn, extension, 7);
- break;
-
- case 0xfe:
- insn = inst << 16;
- extension = load_word (PC + 2);
- insn |= ((extension >> 16) & 0xffff);
- extension <<= 8;
- extension &= 0xffff00;
- extension |= load_byte (PC + 6);
- dispatch (insn, extension, 7);
- break;
-
- default:
- abort ();
- }
- }
- while (!State.exception);
-
-#ifdef HASH_STAT
- {
- int i;
- for (i = 0; i < MAX_HASH; i++)
- {
- struct hash_entry *h;
- h = &hash_table[i];
-
- printf("hash 0x%x:\n", i);
-
- while (h)
- {
- printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count);
- h = h->next;
- }
-
- printf("\n\n");
- }
- fflush (stdout);
- }
-#endif
-
-}
-
-int
-sim_trace (sd)
- SIM_DESC sd;
-{
-#ifdef DEBUG
- mn10300_debug = DEBUG;
-#endif
- sim_resume (sd, 0, 0);
- return 1;
-}
-
-void
-sim_info (sd, verbose)
- SIM_DESC sd;
- int verbose;
-{
- (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n");
-}
-
-SIM_RC
-sim_create_inferior (sd, abfd, argv, env)
- SIM_DESC sd;
- struct bfd *abfd;
- char **argv;
- char **env;
-{
- if (abfd != NULL)
- PC = bfd_get_start_address (abfd);
- else
- PC = 0;
- return SIM_RC_OK;
-}
-
-void
-sim_set_callbacks (p)
- host_callback *p;
-{
- mn10300_callback = p;
-}
-
-/* All the code for exiting, signals, etc needs to be revamped.
-
- This is enough to get c-torture limping though. */
-
-void
-sim_stop_reason (sd, reason, sigrc)
- SIM_DESC sd;
- enum sim_stop *reason;
- int *sigrc;
-{
- if (State.exited)
- *reason = sim_exited;
- else
- *reason = sim_stopped;
-
- if (State.exception == SIGQUIT)
- *sigrc = 0;
- else
- *sigrc = State.exception;
-}
-
-int
-sim_read (sd, addr, buffer, size)
- SIM_DESC sd;
- SIM_ADDR addr;
- unsigned char *buffer;
- int size;
-{
- int i;
- for (i = 0; i < size; i++)
- buffer[i] = load_byte (addr + i);
-
- return size;
-}
-
-void
-sim_do_command (sd, cmd)
- SIM_DESC sd;
- char *cmd;
-{
- (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd);
-}
-
-SIM_RC
-sim_load (sd, prog, abfd, from_tty)
- SIM_DESC sd;
- char *prog;
- bfd *abfd;
- int from_tty;
-{
- extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
- bfd *prog_bfd;
-
- prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd,
- sim_kind == SIM_OPEN_DEBUG,
- 0, sim_write);
- if (prog_bfd == NULL)
- return SIM_RC_FAIL;
- if (abfd == NULL)
- bfd_close (prog_bfd);
- return SIM_RC_OK;
-}
-#endif /* not WITH_COMMON */
-
-
-#if WITH_COMMON
-
/* For compatibility */
SIM_DESC simulator;
@@ -1203,7 +348,6 @@ sim_do_command (sd, cmd)
sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
}
}
-#endif /* WITH_COMMON */
/* FIXME These would more efficient to use than load_mem/store_mem,
but need to be changed to use the memory map. */
Index: sim/mn10300/mn10300_sim.h
===================================================================
RCS file: /cvs/uberbaum/./sim/mn10300/mn10300_sim.h,v
retrieving revision 1.3
diff -u -p -r1.3 mn10300_sim.h
--- sim/mn10300/mn10300_sim.h 9 Jun 2002 15:45:50 -0000 1.3
+++ sim/mn10300/mn10300_sim.h 21 Jun 2004 13:55:34 -0000
@@ -123,42 +123,11 @@ extern struct simops Simops[];
#define REG_MCRL 27
#define REG_MCVF 28
-#if WITH_COMMON
-/* These definitions conflict with similar macros in common. */
-#else
-#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
-
-/* sign-extend a 4-bit number */
-#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
-
-/* sign-extend a 5-bit number */
-#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
-
-/* sign-extend an 8-bit number */
-#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
-
-/* sign-extend a 9-bit number */
-#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
-
-/* sign-extend a 16-bit number */
-#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
-
-/* sign-extend a 22-bit number */
-#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
-
-#define MAX32 0x7fffffffLL
-#define MIN32 0xff80000000LL
-#define MASK32 0xffffffffLL
-#define MASK40 0xffffffffffLL
-#endif /* not WITH_COMMON */
-
#ifdef _WIN32
#define SIGTRAP 5
#define SIGQUIT 3
#endif
-#if WITH_COMMON
-
#define FETCH32(a,b,c,d) \
((a)+((b)<<8)+((c)<<16)+((d)<<24))
@@ -189,171 +158,6 @@ sim_core_write_unaligned_2 (STATE_CPU (s
#define store_word(ADDR, DATA) \
sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), (DATA))
-#endif /* WITH_COMMON */
-
-#if WITH_COMMON
-#else
-#define load_mem_big(addr,len) \
- (len == 1 ? *((addr) + State.mem) : \
- len == 2 ? ((*((addr) + State.mem) << 8) \
- | *(((addr) + 1) + State.mem)) : \
- len == 3 ? ((*((addr) + State.mem) << 16) \
- | (*(((addr) + 1) + State.mem) << 8) \
- | *(((addr) + 2) + State.mem)) : \
- ((*((addr) + State.mem) << 24) \
- | (*(((addr) + 1) + State.mem) << 16) \
- | (*(((addr) + 2) + State.mem) << 8) \
- | *(((addr) + 3) + State.mem)))
-
-static INLINE uint32
-load_byte (addr)
- SIM_ADDR addr;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- return p[0];
-}
-
-static INLINE uint32
-load_half (addr)
- SIM_ADDR addr;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- return p[1] << 8 | p[0];
-}
-
-static INLINE uint32
-load_3_byte (addr)
- SIM_ADDR addr;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- return p[2] << 16 | p[1] << 8 | p[0];
-}
-
-static INLINE uint32
-load_word (addr)
- SIM_ADDR addr;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
-}
-
-static INLINE uint32
-load_mem (addr, len)
- SIM_ADDR addr;
- int len;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- switch (len)
- {
- case 1:
- return p[0];
- case 2:
- return p[1] << 8 | p[0];
- case 3:
- return p[2] << 16 | p[1] << 8 | p[0];
- case 4:
- return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
- default:
- abort ();
- }
-}
-
-static INLINE void
-store_byte (addr, data)
- SIM_ADDR addr;
- uint32 data;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- p[0] = data;
-}
-
-static INLINE void
-store_half (addr, data)
- SIM_ADDR addr;
- uint32 data;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- p[0] = data;
- p[1] = data >> 8;
-}
-
-static INLINE void
-store_3_byte (addr, data)
- SIM_ADDR addr;
- uint32 data;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- p[0] = data;
- p[1] = data >> 8;
- p[2] = data >> 16;
-}
-
-static INLINE void
-store_word (addr, data)
- SIM_ADDR addr;
- uint32 data;
-{
- uint8 *p = (addr & 0xffffff) + State.mem;
-
-#ifdef CHECK_ADDR
- if ((addr & 0xffffff) > max_mem)
- abort ();
-#endif
-
- p[0] = data;
- p[1] = data >> 8;
- p[2] = data >> 16;
- p[3] = data >> 24;
-}
-#endif /* not WITH_COMMON */
/* Function declarations. */
[-- Attachment #3: Type: text/plain, Size: 188 bytes --]
--
Alexandre Oliva http://www.ic.unicamp.br/~oliva/
Red Hat Compiler Engineer aoliva@{redhat.com, gcc.gnu.org}
Free Software Evangelist oliva@{lsd.ic.unicamp.br, gnu.org}
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2004-06-21 13:59 ` Alexandre Oliva
@ 2004-06-25 21:41 ` Andrew Cagney
2004-06-26 22:00 ` Alexandre Oliva
1 sibling, 0 replies; 12+ messages in thread
From: Andrew Cagney @ 2004-06-25 21:41 UTC (permalink / raw)
To: Alexandre Oliva; +Cc: gdb-patches
> On Aug 2, 2003, Andrew Cagney <ac131313@redhat.com> wrote:
>
>
>>> + store_word (addr + 4, data.high);
>>> +}
>>> #endif /* not WITH_COMMON */
>
>
>>> The MN10300 switched to sim/common long ago, the #if !WITH_COMMON code
>>> should be deleted.
>
>
>>> they can both be considered pretty "obvious".
>
>
>>> Other than that, its approved.
>
>
> Here's a patch that removes the non-COMMON bits from the mn10300 sim.
> Ok to install them, and then the AM33/2.0 sim patches I posted back on
> Jul 10, 2003, with the other refinements you requested on Aug 2, 2003?
M'kay.
Andrew
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2004-06-21 13:59 ` Alexandre Oliva
2004-06-25 21:41 ` Andrew Cagney
@ 2004-06-26 22:00 ` Alexandre Oliva
1 sibling, 0 replies; 12+ messages in thread
From: Alexandre Oliva @ 2004-06-26 22:00 UTC (permalink / raw)
To: Andrew Cagney; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 346 bytes --]
On Jun 21, 2004, Alexandre Oliva <aoliva@redhat.com> wrote:
> Here's a patch that removes the non-COMMON bits from the mn10300 sim.
This patch completes the removal of the non-COMMON bits, taking out
some source files and Makefile rules that are no longer used since the
previous patch went in. I'm going ahead and checking it in as
obvious.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: mn10300-sim-common-more.patch --]
[-- Type: text/x-patch, Size: 92191 bytes --]
Index: sim/mn10300/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* gencode.c, simops.c: Delete.
* Makefile.in: Remove non-COMMON dependencies and commands.
Index: sim/mn10300/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mn10300/Makefile.in,v
retrieving revision 1.7
diff -u -p -r1.7 Makefile.in
--- sim/mn10300/Makefile.in 26 Jun 2004 18:45:53 -0000 1.7
+++ sim/mn10300/Makefile.in 26 Jun 2004 21:44:02 -0000
@@ -29,14 +29,13 @@ MN10300_OBJS = \
sim-reason.o \
sim-stop.o \
dv-sockser.o
-MN10300_INTERP_DEP =
SIM_OBJS = $(MN10300_OBJS) interp.o
# List of main object files for `run'.
SIM_RUN_OBJS = nrun.o
-SIM_EXTRA_CLEAN = clean-extra
+SIM_EXTRA_CLEAN = clean-igen
# Extra dependencies for "sim-main.h"
SIM_EXTRA_DEPS = mn10300_sim.h itable.h idecode.h
@@ -50,28 +49,7 @@ SIM_EXTRA_CFLAGS = -DPOLL_QUIT_INTERVAL=
## COMMON_POST_CONFIG_FRAG
-
-#
-# Old generator (default)
-#
-
-simops.h: gencode
- ./gencode -h >$@
-
-table.c: gencode simops.h
- ./gencode >$@
-
-gencode.o: gencode.c $(INCLUDE)
- $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/gencode.c
-
-m10300-opc.o: $(srcdir)/../../opcodes/m10300-opc.c
- $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/../../opcodes/m10300-opc.c
-
-gencode: gencode.o m10300-opc.o
- $(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode gencode.o m10300-opc.o $(BUILD_LIB)
-
-idecode.o op_utils.o semantics.o simops.o: targ-vals.h
-
+idecode.o op_utils.o semantics.o: targ-vals.h
BUILT_SRC_FROM_IGEN = \
icache.h \
@@ -145,10 +123,4 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../ige
$(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
touch tmp-igen
-
-interp.o: interp.c $(MN10300_INTERP_DEP) $(INCLUDE)
-simops.o: simops.c simops.h $(INCLUDE)
-table.o: table.c
-
-clean-extra: clean-igen
- rm -f table.c simops.h gencode
+interp.o: interp.c $(INCLUDE)
Index: sim/mn10300/gencode.c
===================================================================
RCS file: sim/mn10300/gencode.c
diff -N sim/mn10300/gencode.c
--- sim/mn10300/gencode.c 16 Apr 1999 01:35:07 -0000 1.1.1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,163 +0,0 @@
-#include "mn10300_sim.h"
-
-static void write_header PARAMS ((void));
-static void write_opcodes PARAMS ((void));
-static void write_template PARAMS ((void));
-
-long Opcodes[512];
-static int curop=0;
-
-int
-main (argc, argv)
- int argc;
- char *argv[];
-{
- if ((argc > 1) && (strcmp (argv[1], "-h") == 0))
- write_header();
- else if ((argc > 1) && (strcmp (argv[1], "-t") == 0))
- write_template ();
- else
- write_opcodes();
- return 0;
-}
-
-
-static void
-write_header ()
-{
- struct mn10300_opcode *opcode;
-
- for (opcode = (struct mn10300_opcode *)mn10300_opcodes; opcode->name; opcode++)
- printf("void OP_%X PARAMS ((unsigned long, unsigned long));\t\t/* %s */\n",
- opcode->opcode, opcode->name);
-}
-
-
-/* write_template creates a file all required functions, ready */
-/* to be filled out */
-
-static void
-write_template ()
-{
- struct mn10300_opcode *opcode;
- int i,j;
-
- printf ("#include \"mn10300_sim.h\"\n");
- printf ("#include \"simops.h\"\n");
-
- for (opcode = (struct mn10300_opcode *)mn10300_opcodes; opcode->name; opcode++)
- {
- printf("/* %s */\nvoid\nOP_%X (insn, extension)\n unsigned long insn, extension;\n{\n", opcode->name, opcode->opcode);
-
- /* count operands */
- j = 0;
- for (i = 0; i < 6; i++)
- {
- int flags = mn10300_operands[opcode->operands[i]].flags;
-
- if (flags)
- j++;
- }
- switch (j)
- {
- case 0:
- printf ("printf(\" %s\\n\");\n", opcode->name);
- break;
- case 1:
- printf ("printf(\" %s\\t%%x\\n\", OP[0]);\n", opcode->name);
- break;
- case 2:
- printf ("printf(\" %s\\t%%x,%%x\\n\",OP[0],OP[1]);\n",
- opcode->name);
- break;
- case 3:
- printf ("printf(\" %s\\t%%x,%%x,%%x\\n\",OP[0],OP[1],OP[2]);\n",
- opcode->name);
- break;
- default:
- fprintf (stderr,"Too many operands: %d\n", j);
- }
- printf ("}\n\n");
- }
-}
-
-static void
-write_opcodes ()
-{
- struct mn10300_opcode *opcode;
- int i, j;
- int numops;
-
- /* write out opcode table */
- printf ("#include \"mn10300_sim.h\"\n");
- printf ("#include \"simops.h\"\n\n");
- printf ("struct simops Simops[] = {\n");
-
- for (opcode = (struct mn10300_opcode *)mn10300_opcodes; opcode->name; opcode++)
- {
- int size;
-
- if (opcode->format == FMT_S0)
- size = 1;
- else if (opcode->format == FMT_S1
- || opcode->format == FMT_D0)
- size = 2;
- else if (opcode->format == FMT_S2
- || opcode->format == FMT_D1)
- size = 3;
- else if (opcode->format == FMT_S4)
- size = 5;
- else if (opcode->format == FMT_D2)
- size = 4;
- else if (opcode->format == FMT_D4)
- size = 6;
- else
- size = 7;
-
- printf (" { 0x%x,0x%x,OP_%X,%d,%d,",
- opcode->opcode, opcode->mask, opcode->opcode,
- size, opcode->format);
-
- Opcodes[curop++] = opcode->opcode;
-
- /* count operands */
- j = 0;
- for (i = 0; i < 6; i++)
- {
- int flags = mn10300_operands[opcode->operands[i]].flags;
-
- if (flags)
- j++;
- }
- printf ("%d,{",j);
-
- j = 0;
- numops = 0;
- for (i = 0; i < 6; i++)
- {
- int flags = mn10300_operands[opcode->operands[i]].flags;
- int shift = mn10300_operands[opcode->operands[i]].shift;
-
- if (flags)
- {
- if (j)
- printf (", ");
- printf ("%d,%d,%d", shift,
- mn10300_operands[opcode->operands[i]].bits,flags);
- j = 1;
- numops++;
- }
- }
-
- switch (numops)
- {
- case 0:
- printf ("0,0,0");
- case 1:
- printf (",0,0,0");
- }
-
- printf ("}},\n");
- }
- printf ("{ 0,0,NULL,0,0,0,{0,0,0,0,0,0}},\n};\n");
-}
Index: sim/mn10300/simops.c
===================================================================
RCS file: sim/mn10300/simops.c
diff -N sim/mn10300/simops.c
--- sim/mn10300/simops.c 16 Apr 1999 01:35:07 -0000 1.1.1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,3239 +0,0 @@
-#include "config.h"
-
-#include <signal.h>
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>
-#endif
-#include "mn10300_sim.h"
-#include "simops.h"
-#include "sim-types.h"
-#include "targ-vals.h"
-#include "bfd.h"
-#include <errno.h>
-#include <sys/stat.h>
-#include <sys/times.h>
-#include <sys/time.h>
-
-#define REG0(X) ((X) & 0x3)
-#define REG1(X) (((X) & 0xc) >> 2)
-#define REG0_4(X) (((X) & 0x30) >> 4)
-#define REG0_8(X) (((X) & 0x300) >> 8)
-#define REG1_8(X) (((X) & 0xc00) >> 10)
-#define REG0_16(X) (((X) & 0x30000) >> 16)
-#define REG1_16(X) (((X) & 0xc0000) >> 18)
-\f
-/* mov imm8, dn */
-void OP_8000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
-}
-
-/* mov dm, dn */
-void OP_80 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
-}
-
-/* mov dm, an */
-void OP_F1E0 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
-}
-
-/* mov am, dn */
-void OP_F1D0 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
-}
-
-/* mov imm8, an */
-void OP_9000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff;
-}
-
-/* mov am, an */
-void OP_90 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
-}
-
-/* mov sp, an */
-void OP_3C (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP];
-}
-
-/* mov am, sp */
-void OP_F2F0 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)];
-}
-
-/* mov psw, dn */
-void OP_F2E4 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0 (insn)] = PSW;
-}
-
-/* mov dm, psw */
-void OP_F2F3 (insn, extension)
- unsigned long insn, extension;
-{
- PSW = State.regs[REG_D0 + REG1 (insn)];
-}
-
-/* mov mdr, dn */
-void OP_F2E0 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR];
-}
-
-/* mov dm, mdr */
-void OP_F2F2 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)];
-}
-
-/* mov (am), dn */
-void OP_70 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1 (insn)]
- = load_word (State.regs[REG_A0 + REG0 (insn)]);
-}
-
-/* mov (d8,am), dn */
-void OP_F80000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_8 (insn)]
- = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)));
-}
-
-/* mov (d16,am), dn */
-void OP_FA000000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_16 (insn)]
- = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)));
-}
-
-/* mov (d32,am), dn */
-void OP_FC000000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_16 (insn)]
- = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension));
-}
-
-/* mov (d8,sp), dn */
-void OP_5800 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_8 (insn)]
- = load_word (State.regs[REG_SP] + (insn & 0xff));
-}
-
-/* mov (d16,sp), dn */
-void OP_FAB40000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_word (State.regs[REG_SP] + (insn & 0xffff));
-}
-
-/* mov (d32,sp), dn */
-void OP_FCB40000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
-}
-
-/* mov (di,am), dn */
-void OP_F300 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_4 (insn)]
- = load_word ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]));
-}
-
-/* mov (abs16), dn */
-void OP_300000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
-}
-
-/* mov (abs32), dn */
-void OP_FCA40000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_word ((((insn & 0xffff) << 16) + extension));
-}
-
-/* mov (am), an */
-void OP_F000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG1 (insn)]
- = load_word (State.regs[REG_A0 + REG0 (insn)]);
-}
-
-/* mov (d8,am), an */
-void OP_F82000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG1_8 (insn)]
- = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)));
-}
-
-/* mov (d16,am), an */
-void OP_FA200000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG1_16 (insn)]
- = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)));
-}
-
-/* mov (d32,am), an */
-void OP_FC200000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG1_16 (insn)]
- = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension));
-}
-
-/* mov (d8,sp), an */
-void OP_5C00 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0_8 (insn)]
- = load_word (State.regs[REG_SP] + (insn & 0xff));
-}
-
-/* mov (d16,sp), an */
-void OP_FAB00000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0_16 (insn)]
- = load_word (State.regs[REG_SP] + (insn & 0xffff));
-}
-
-/* mov (d32,sp), an */
-void OP_FCB00000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0_16 (insn)]
- = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
-}
-
-/* mov (di,am), an */
-void OP_F380 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0_4 (insn)]
- = load_word ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]));
-}
-
-/* mov (abs16), an */
-void OP_FAA00000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
-}
-
-/* mov (abs32), an */
-void OP_FCA00000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0_16 (insn)]
- = load_word ((((insn & 0xffff) << 16) + extension));
-}
-
-/* mov (d8,am), sp */
-void OP_F8F000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_SP]
- = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)));
-}
-
-/* mov dm, (an) */
-void OP_60 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_A0 + REG0 (insn)],
- State.regs[REG_D0 + REG1 (insn)]);
-}
-
-/* mov dm, (d8,an) */
-void OP_F81000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
- State.regs[REG_D0 + REG1_8 (insn)]);
-}
-
-/* mov dm (d16,an) */
-void OP_FA100000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* mov dm (d32,an) */
-void OP_FC100000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* mov dm, (d8,sp) */
-void OP_4200 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_SP] + (insn & 0xff),
- State.regs[REG_D0 + REG1_8 (insn)]);
-}
-
-/* mov dm, (d16,sp) */
-void OP_FA910000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_SP] + (insn & 0xffff),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* mov dm, (d32,sp) */
-void OP_FC910000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* mov dm, (di,an) */
-void OP_F340 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]),
- State.regs[REG_D0 + REG0_4 (insn)]);
-}
-
-/* mov dm, (abs16) */
-void OP_10000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* mov dm, (abs32) */
-void OP_FC810000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((((insn & 0xffff) << 16) + extension),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* mov am, (an) */
-void OP_F010 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_A0 + REG0 (insn)],
- State.regs[REG_A0 + REG1 (insn)]);
-}
-
-/* mov am, (d8,an) */
-void OP_F83000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
- State.regs[REG_A0 + REG1_8 (insn)]);
-}
-
-/* mov am, (d16,an) */
-void OP_FA300000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
- State.regs[REG_A0 + REG1_16 (insn)]);
-}
-
-/* mov am, (d32,an) */
-void OP_FC300000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension),
- State.regs[REG_A0 + REG1_16 (insn)]);
-}
-
-/* mov am, (d8,sp) */
-void OP_4300 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_SP] + (insn & 0xff),
- State.regs[REG_A0 + REG1_8 (insn)]);
-}
-
-/* mov am, (d16,sp) */
-void OP_FA900000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_SP] + (insn & 0xffff),
- State.regs[REG_A0 + REG1_16 (insn)]);
-}
-
-/* mov am, (d32,sp) */
-void OP_FC900000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
- State.regs[REG_A0 + REG1_16 (insn)]);
-}
-
-/* mov am, (di,an) */
-void OP_F3C0 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]),
- State.regs[REG_A0 + REG0_4 (insn)]);
-}
-
-/* mov am, (abs16) */
-void OP_FA800000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((insn & 0xffff), State.regs[REG_A0 + REG1_16 (insn)]);
-}
-
-/* mov am, (abs32) */
-void OP_FC800000 (insn, extension)
- unsigned long insn, extension;
-{
- store_word ((((insn & 0xffff) << 16) + extension), State.regs[REG_A0 + REG1_16 (insn)]);
-}
-
-/* mov sp, (d8,an) */
-void OP_F8F400 (insn, extension)
- unsigned long insn, extension;
-{
- store_word (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
- State.regs[REG_SP]);
-}
-
-/* mov imm16, dn */
-void OP_2C0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long value;
-
- value = SEXT16 (insn & 0xffff);
- State.regs[REG_D0 + REG0_16 (insn)] = value;
-}
-
-/* mov imm32,dn */
-void OP_FCCC0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long value;
-
- value = ((insn & 0xffff) << 16) + extension;
- State.regs[REG_D0 + REG0_16 (insn)] = value;
-}
-
-/* mov imm16, an */
-void OP_240000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long value;
-
- value = insn & 0xffff;
- State.regs[REG_A0 + REG0_16 (insn)] = value;
-}
-
-/* mov imm32, an */
-void OP_FCDC0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long value;
-
- value = ((insn & 0xffff) << 16) + extension;
- State.regs[REG_A0 + REG0_16 (insn)] = value;
-}
-
-/* movbu (am), dn */
-void OP_F040 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1 (insn)]
- = load_byte (State.regs[REG_A0 + REG0 (insn)]);
-}
-
-/* movbu (d8,am), dn */
-void OP_F84000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_8 (insn)]
- = load_byte ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)));
-}
-
-/* movbu (d16,am), dn */
-void OP_FA400000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_16 (insn)]
- = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)));
-}
-
-/* movbu (d32,am), dn */
-void OP_FC400000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_16 (insn)]
- = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension));
-}
-
-/* movbu (d8,sp), dn */
-void OP_F8B800 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_8 (insn)]
- = load_byte ((State.regs[REG_SP] + (insn & 0xff)));
-}
-
-/* movbu (d16,sp), dn */
-void OP_FAB80000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_byte ((State.regs[REG_SP] + (insn & 0xffff)));
-}
-
-/* movbu (d32,sp), dn */
-void OP_FCB80000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
-}
-
-/* movbu (di,am), dn */
-void OP_F400 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_4 (insn)]
- = load_byte ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]));
-}
-
-/* movbu (abs16), dn */
-void OP_340000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff));
-}
-
-/* movbu (abs32), dn */
-void OP_FCA80000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_byte ((((insn & 0xffff) << 16) + extension));
-}
-
-/* movbu dm, (an) */
-void OP_F050 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte (State.regs[REG_A0 + REG0 (insn)],
- State.regs[REG_D0 + REG1 (insn)]);
-}
-
-/* movbu dm, (d8,an) */
-void OP_F85000 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
- State.regs[REG_D0 + REG1_8 (insn)]);
-}
-
-/* movbu dm, (d16,an) */
-void OP_FA500000 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movbu dm, (d32,an) */
-void OP_FC500000 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movbu dm, (d8,sp) */
-void OP_F89200 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte (State.regs[REG_SP] + (insn & 0xff),
- State.regs[REG_D0 + REG1_8 (insn)]);
-}
-
-/* movbu dm, (d16,sp) */
-void OP_FA920000 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte (State.regs[REG_SP] + (insn & 0xffff),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movbu dm (d32,sp) */
-void OP_FC920000 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movbu dm, (di,an) */
-void OP_F440 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]),
- State.regs[REG_D0 + REG0_4 (insn)]);
-}
-
-/* movbu dm, (abs16) */
-void OP_20000 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movbu dm, (abs32) */
-void OP_FC820000 (insn, extension)
- unsigned long insn, extension;
-{
- store_byte ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movhu (am), dn */
-void OP_F060 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1 (insn)]
- = load_half (State.regs[REG_A0 + REG0 (insn)]);
-}
-
-/* movhu (d8,am), dn */
-void OP_F86000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_8 (insn)]
- = load_half ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)));
-}
-
-/* movhu (d16,am), dn */
-void OP_FA600000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_16 (insn)]
- = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)));
-}
-
-/* movhu (d32,am), dn */
-void OP_FC600000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1_16 (insn)]
- = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension));
-}
-
-/* movhu (d8,sp) dn */
-void OP_F8BC00 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_8 (insn)]
- = load_half ((State.regs[REG_SP] + (insn & 0xff)));
-}
-
-/* movhu (d16,sp), dn */
-void OP_FABC0000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_half ((State.regs[REG_SP] + (insn & 0xffff)));
-}
-
-/* movhu (d32,sp), dn */
-void OP_FCBC0000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
-}
-
-/* movhu (di,am), dn */
-void OP_F480 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_4 (insn)]
- = load_half ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]));
-}
-
-/* movhu (abs16), dn */
-void OP_380000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)] = load_half ((insn & 0xffff));
-}
-
-/* movhu (abs32), dn */
-void OP_FCAC0000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0_16 (insn)]
- = load_half ((((insn & 0xffff) << 16) + extension));
-}
-
-/* movhu dm, (an) */
-void OP_F070 (insn, extension)
- unsigned long insn, extension;
-{
- store_half (State.regs[REG_A0 + REG0 (insn)],
- State.regs[REG_D0 + REG1 (insn)]);
-}
-
-/* movhu dm, (d8,an) */
-void OP_F87000 (insn, extension)
- unsigned long insn, extension;
-{
- store_half ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
- State.regs[REG_D0 + REG1_8 (insn)]);
-}
-
-/* movhu dm, (d16,an) */
-void OP_FA700000 (insn, extension)
- unsigned long insn, extension;
-{
- store_half ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movhu dm, (d32,an) */
-void OP_FC700000 (insn, extension)
- unsigned long insn, extension;
-{
- store_half ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movhu dm,(d8,sp) */
-void OP_F89300 (insn, extension)
- unsigned long insn, extension;
-{
- store_half (State.regs[REG_SP] + (insn & 0xff),
- State.regs[REG_D0 + REG1_8 (insn)]);
-}
-
-/* movhu dm,(d16,sp) */
-void OP_FA930000 (insn, extension)
- unsigned long insn, extension;
-{
- store_half (State.regs[REG_SP] + (insn & 0xffff),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movhu dm,(d32,sp) */
-void OP_FC930000 (insn, extension)
- unsigned long insn, extension;
-{
- store_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
- State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movhu dm, (di,an) */
-void OP_F4C0 (insn, extension)
- unsigned long insn, extension;
-{
- store_half ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]),
- State.regs[REG_D0 + REG0_4 (insn)]);
-}
-
-/* movhu dm, (abs16) */
-void OP_30000 (insn, extension)
- unsigned long insn, extension;
-{
- store_half ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* movhu dm, (abs32) */
-void OP_FC830000 (insn, extension)
- unsigned long insn, extension;
-{
- store_half ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
-}
-
-/* ext dn */
-void OP_F2D0 (insn, extension)
- unsigned long insn, extension;
-{
- if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000)
- State.regs[REG_MDR] = -1;
- else
- State.regs[REG_MDR] = 0;
-}
-
-/* extb dn */
-void OP_10 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
-}
-
-/* extbu dn */
-void OP_14 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0 (insn)] &= 0xff;
-}
-
-/* exth dn */
-void OP_18 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0 (insn)]
- = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
-}
-
-/* exthu dn */
-void OP_1C (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG0 (insn)] &= 0xffff;
-}
-
-/* movm (sp), reg_list */
-void OP_CE00 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long sp = State.regs[REG_SP];
- unsigned long mask;
-
- mask = insn & 0xff;
-
- if (mask & 0x8)
- {
- sp += 4;
- State.regs[REG_LAR] = load_word (sp);
- sp += 4;
- State.regs[REG_LIR] = load_word (sp);
- sp += 4;
- State.regs[REG_MDR] = load_word (sp);
- sp += 4;
- State.regs[REG_A0 + 1] = load_word (sp);
- sp += 4;
- State.regs[REG_A0] = load_word (sp);
- sp += 4;
- State.regs[REG_D0 + 1] = load_word (sp);
- sp += 4;
- State.regs[REG_D0] = load_word (sp);
- sp += 4;
- }
-
- if (mask & 0x10)
- {
- State.regs[REG_A0 + 3] = load_word (sp);
- sp += 4;
- }
-
- if (mask & 0x20)
- {
- State.regs[REG_A0 + 2] = load_word (sp);
- sp += 4;
- }
-
- if (mask & 0x40)
- {
- State.regs[REG_D0 + 3] = load_word (sp);
- sp += 4;
- }
-
- if (mask & 0x80)
- {
- State.regs[REG_D0 + 2] = load_word (sp);
- sp += 4;
- }
-
- /* And make sure to update the stack pointer. */
- State.regs[REG_SP] = sp;
-}
-
-/* movm reg_list, (sp) */
-void OP_CF00 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long sp = State.regs[REG_SP];
- unsigned long mask;
-
- mask = insn & 0xff;
-
- if (mask & 0x80)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 2]);
- }
-
- if (mask & 0x40)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 3]);
- }
-
- if (mask & 0x20)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 2]);
- }
-
- if (mask & 0x10)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 3]);
- }
-
- if (mask & 0x8)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0]);
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 1]);
- sp -= 4;
- store_word (sp, State.regs[REG_A0]);
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 1]);
- sp -= 4;
- store_word (sp, State.regs[REG_MDR]);
- sp -= 4;
- store_word (sp, State.regs[REG_LIR]);
- sp -= 4;
- store_word (sp, State.regs[REG_LAR]);
- sp -= 4;
- }
-
- /* And make sure to update the stack pointer. */
- State.regs[REG_SP] = sp;
-}
-
-/* clr dn */
-void OP_0 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_D0 + REG1 (insn)] = 0;
-
- PSW |= PSW_Z;
- PSW &= ~(PSW_V | PSW_C | PSW_N);
-}
-
-/* add dm,dn */
-void OP_E0 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- reg2 = State.regs[REG_D0 + REG0 (insn)];
- value = reg1 + reg2;
- State.regs[REG_D0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < reg2);
- v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add dm, an */
-void OP_F160 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- reg2 = State.regs[REG_A0 + REG0 (insn)];
- value = reg1 + reg2;
- State.regs[REG_A0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < reg2);
- v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add am, dn */
-void OP_F150 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_A0 + REG1 (insn)];
- reg2 = State.regs[REG_D0 + REG0 (insn)];
- value = reg1 + reg2;
- State.regs[REG_D0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < reg2);
- v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add am,an */
-void OP_F170 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_A0 + REG1 (insn)];
- reg2 = State.regs[REG_A0 + REG0 (insn)];
- value = reg1 + reg2;
- State.regs[REG_A0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < reg2);
- v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add imm8, dn */
-void OP_2800 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_D0 + REG0_8 (insn)];
- imm = SEXT8 (insn & 0xff);
- value = reg1 + imm;
- State.regs[REG_D0 + REG0_8 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < imm);
- v = ((reg1 & 0x80000000) == (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add imm16, dn */
-void OP_FAC00000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_D0 + REG0_16 (insn)];
- imm = SEXT16 (insn & 0xffff);
- value = reg1 + imm;
- State.regs[REG_D0 + REG0_16 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < imm);
- v = ((reg1 & 0x80000000) == (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add imm32,dn */
-void OP_FCC00000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_D0 + REG0_16 (insn)];
- imm = ((insn & 0xffff) << 16) + extension;
- value = reg1 + imm;
- State.regs[REG_D0 + REG0_16 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < imm);
- v = ((reg1 & 0x80000000) == (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add imm8, an */
-void OP_2000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_A0 + REG0_8 (insn)];
- imm = SEXT8 (insn & 0xff);
- value = reg1 + imm;
- State.regs[REG_A0 + REG0_8 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < imm);
- v = ((reg1 & 0x80000000) == (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add imm16, an */
-void OP_FAD00000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_A0 + REG0_16 (insn)];
- imm = SEXT16 (insn & 0xffff);
- value = reg1 + imm;
- State.regs[REG_A0 + REG0_16 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < imm);
- v = ((reg1 & 0x80000000) == (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add imm32, an */
-void OP_FCD00000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_A0 + REG0_16 (insn)];
- imm = ((insn & 0xffff) << 16) + extension;
- value = reg1 + imm;
- State.regs[REG_A0 + REG0_16 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < imm);
- v = ((reg1 & 0x80000000) == (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* add imm8, sp */
-void OP_F8FE00 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_SP];
- imm = SEXT8 (insn & 0xff);
- value = reg1 + imm;
- State.regs[REG_SP] = value;
-}
-
-/* add imm16,sp */
-void OP_FAFE0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_SP];
- imm = SEXT16 (insn & 0xffff);
- value = reg1 + imm;
- State.regs[REG_SP] = value;
-}
-
-/* add imm32, sp */
-void OP_FCFE0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_SP];
- imm = ((insn & 0xffff) << 16) + extension;
- value = reg1 + imm;
- State.regs[REG_SP] = value;
-}
-
-/* addc dm,dn */
-void OP_F140 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- reg2 = State.regs[REG_D0 + REG0 (insn)];
- value = reg1 + reg2 + ((PSW & PSW_C) != 0);
- State.regs[REG_D0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < reg1) || (value < reg2);
- v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* sub dm, dn */
-void OP_F100 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- reg2 = State.regs[REG_D0 + REG0 (insn)];
- value = reg2 - reg1;
- State.regs[REG_D0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* sub dm, an */
-void OP_F120 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- reg2 = State.regs[REG_A0 + REG0 (insn)];
- value = reg2 - reg1;
- State.regs[REG_A0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* sub am, dn */
-void OP_F110 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_A0 + REG1 (insn)];
- reg2 = State.regs[REG_D0 + REG0 (insn)];
- value = reg2 - reg1;
- State.regs[REG_D0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* sub am, an */
-void OP_F130 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_A0 + REG1 (insn)];
- reg2 = State.regs[REG_A0 + REG0 (insn)];
- value = reg2 - reg1;
- State.regs[REG_A0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* sub imm32, dn */
-void OP_FCC40000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_D0 + REG0_16 (insn)];
- imm = ((insn & 0xffff) << 16) + extension;
- value = reg1 - imm;
- State.regs[REG_D0 + REG0_16 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 < imm);
- v = ((reg1 & 0x80000000) != (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* sub imm32, an */
-void OP_FCD40000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_A0 + REG0_16 (insn)];
- imm = ((insn & 0xffff) << 16) + extension;
- value = reg1 - imm;
- State.regs[REG_A0 + REG0_16 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 < imm);
- v = ((reg1 & 0x80000000) != (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* subc dm, dn */
-void OP_F180 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- reg2 = State.regs[REG_D0 + REG0 (insn)];
- value = reg2 - reg1 - ((PSW & PSW_C) != 0);
- State.regs[REG_D0 + REG0 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* mul dm, dn */
-void OP_F240 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)]
- * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]);
- State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* mulu dm, dn */
-void OP_F250 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((unsigned64)State.regs[REG_D0 + REG0 (insn)]
- * (unsigned64)State.regs[REG_D0 + REG1 (insn)]);
- State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* div dm, dn */
-void OP_F260 (insn, extension)
- unsigned long insn, extension;
-{
- long long temp;
- int n, z;
-
- temp = State.regs[REG_MDR];
- temp <<= 32;
- temp |= State.regs[REG_D0 + REG0 (insn)];
- State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)];
- temp /= (long)State.regs[REG_D0 + REG1 (insn)];
- State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* divu dm, dn */
-void OP_F270 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = State.regs[REG_MDR];
- temp <<= 32;
- temp |= State.regs[REG_D0 + REG0 (insn)];
- State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)];
- temp /= State.regs[REG_D0 + REG1 (insn)];
- State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* inc dn */
-void OP_40 (insn, extension)
- unsigned long insn, extension;
-{
- int z,n,c,v;
- unsigned int value, imm, reg1;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- imm = 1;
- value = reg1 + imm;
- State.regs[REG_D0 + REG1 (insn)] = value;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (value < imm);
- v = ((reg1 & 0x80000000) == (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* inc an */
-void OP_41 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG1 (insn)] += 1;
-}
-
-/* inc4 an */
-void OP_50 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_A0 + REG0 (insn)] += 4;
-}
-
-/* cmp imm8, dn */
-void OP_A000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_D0 + REG0_8 (insn)];
- imm = SEXT8 (insn & 0xff);
- value = reg1 - imm;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 < imm);
- v = ((reg1 & 0x80000000) != (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp dm, dn */
-void OP_A0 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- reg2 = State.regs[REG_D0 + REG0 (insn)];
- value = reg2 - reg1;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp dm, an */
-void OP_F1A0 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_D0 + REG1 (insn)];
- reg2 = State.regs[REG_A0 + REG0 (insn)];
- value = reg2 - reg1;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp am, dn */
-void OP_F190 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_A0 + REG1 (insn)];
- reg2 = State.regs[REG_D0 + REG0 (insn)];
- value = reg2 - reg1;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp imm8, an */
-void OP_B000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_A0 + REG0_8 (insn)];
- imm = insn & 0xff;
- value = reg1 - imm;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 < imm);
- v = ((reg1 & 0x80000000) != (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp am, an */
-void OP_B0 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, reg2, value;
-
- reg1 = State.regs[REG_A0 + REG1 (insn)];
- reg2 = State.regs[REG_A0 + REG0 (insn)];
- value = reg2 - reg1;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 > reg2);
- v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
- && (reg2 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp imm16, dn */
-void OP_FAC80000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_D0 + REG0_16 (insn)];
- imm = SEXT16 (insn & 0xffff);
- value = reg1 - imm;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 < imm);
- v = ((reg1 & 0x80000000) != (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp imm32, dn */
-void OP_FCC80000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_D0 + REG0_16 (insn)];
- imm = ((insn & 0xffff) << 16) + extension;
- value = reg1 - imm;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 < imm);
- v = ((reg1 & 0x80000000) != (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp imm16, an */
-void OP_FAD80000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_A0 + REG0_16 (insn)];
- imm = insn & 0xffff;
- value = reg1 - imm;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 < imm);
- v = ((reg1 & 0x80000000) != (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* cmp imm32, an */
-void OP_FCD80000 (insn, extension)
- unsigned long insn, extension;
-{
- int z, c, n, v;
- unsigned long reg1, imm, value;
-
- reg1 = State.regs[REG_A0 + REG0_16 (insn)];
- imm = ((insn & 0xffff) << 16) + extension;
- value = reg1 - imm;
-
- z = (value == 0);
- n = (value & 0x80000000);
- c = (reg1 < imm);
- v = ((reg1 & 0x80000000) != (imm & 0x80000000)
- && (reg1 & 0x80000000) != (value & 0x80000000));
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
- | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-}
-
-/* and dm, dn */
-void OP_F200 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)];
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* and imm8, dn */
-void OP_F8E000 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff);
- z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* and imm16, dn */
-void OP_FAE00000 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff);
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* and imm32, dn */
-void OP_FCE00000 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_16 (insn)]
- &= ((insn & 0xffff) << 16) + extension;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* and imm16, psw */
-void OP_FAFC0000 (insn, extension)
- unsigned long insn, extension;
-{
- PSW &= (insn & 0xffff);
-}
-
-/* or dm, dn*/
-void OP_F210 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)];
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* or imm8, dn */
-void OP_F8E400 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff;
- z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* or imm16, dn*/
-void OP_FAE40000 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* or imm32, dn */
-void OP_FCE40000 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_16 (insn)]
- |= ((insn & 0xffff) << 16) + extension;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* or imm16,psw */
-void OP_FAFD0000 (insn, extension)
- unsigned long insn, extension;
-{
- PSW |= (insn & 0xffff);
-}
-
-/* xor dm, dn */
-void OP_F220 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)];
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* xor imm16, dn */
-void OP_FAE80000 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* xor imm32, dn */
-void OP_FCE80000 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_16 (insn)]
- ^= ((insn & 0xffff) << 16) + extension;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* not dn */
-void OP_F230 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)];
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* btst imm8, dn */
-void OP_F8EC00 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z, n;
-
- temp = State.regs[REG_D0 + REG0_8 (insn)];
- temp &= (insn & 0xff);
- n = (temp & 0x80000000) != 0;
- z = (temp == 0);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
-}
-
-/* btst imm16, dn */
-void OP_FAEC0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z, n;
-
- temp = State.regs[REG_D0 + REG0_16 (insn)];
- temp &= (insn & 0xffff);
- n = (temp & 0x80000000) != 0;
- z = (temp == 0);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
-}
-
-/* btst imm32, dn */
-void OP_FCEC0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z, n;
-
- temp = State.regs[REG_D0 + REG0_16 (insn)];
- temp &= ((insn & 0xffff) << 16) + extension;
- n = (temp & 0x80000000) != 0;
- z = (temp == 0);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
-}
-
-/* btst imm8,(abs32) */
-void OP_FE020000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int n, z;
-
- temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
- temp &= (extension & 0xff);
- n = (temp & 0x80000000) != 0;
- z = (temp == 0);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
-}
-
-/* btst imm8,(d8,an) */
-void OP_FAF80000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int n, z;
-
- temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)));
- temp &= (insn & 0xff);
- n = (temp & 0x80000000) != 0;
- z = (temp == 0);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
-}
-
-/* bset dm, (an) */
-void OP_F080 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z;
-
- temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
- z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
- temp |= State.regs[REG_D0 + REG1 (insn)];
- store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0);
-}
-
-/* bset imm8, (abs32) */
-void OP_FE000000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z;
-
- temp = load_byte (((insn & 0xffff) << 16 | (extension >> 8)));
- z = (temp & (extension & 0xff)) == 0;
- temp |= (extension & 0xff);
- store_byte ((((insn & 0xffff) << 16) | (extension >> 8)), temp);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0);
-}
-
-/* bset imm8,(d8,an) */
-void OP_FAF00000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z;
-
- temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)));
- z = (temp & (insn & 0xff)) == 0;
- temp |= (insn & 0xff);
- store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)), temp);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0);
-}
-
-/* bclr dm, (an) */
-void OP_F090 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z;
-
- temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
- z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
- temp = temp & ~State.regs[REG_D0 + REG1 (insn)];
- store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0);
-}
-
-/* bclr imm8, (abs32) */
-void OP_FE010000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z;
-
- temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
- z = (temp & (extension & 0xff)) == 0;
- temp = temp & ~(extension & 0xff);
- store_byte (((insn & 0xffff) << 16) | (extension >> 8), temp);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0);
-}
-
-/* bclr imm8,(d8,an) */
-void OP_FAF40000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long temp;
- int z;
-
- temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)));
- z = (temp & (insn & 0xff)) == 0;
- temp = temp & ~(insn & 0xff);
- store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)), temp);
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0);
-}
-
-/* asr dm, dn */
-void OP_F2B0 (insn, extension)
- unsigned long insn, extension;
-{
- long temp;
- int z, n, c;
-
- temp = State.regs[REG_D0 + REG0 (insn)];
- c = temp & 1;
- temp >>= State.regs[REG_D0 + REG1 (insn)];
- State.regs[REG_D0 + REG0 (insn)] = temp;
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
-}
-
-/* asr imm8, dn */
-void OP_F8C800 (insn, extension)
- unsigned long insn, extension;
-{
- long temp;
- int z, n, c;
-
- temp = State.regs[REG_D0 + REG0_8 (insn)];
- c = temp & 1;
- temp >>= (insn & 0xff);
- State.regs[REG_D0 + REG0_8 (insn)] = temp;
- z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
-}
-
-/* lsr dm, dn */
-void OP_F2A0 (insn, extension)
- unsigned long insn, extension;
-{
- int z, n, c;
-
- c = State.regs[REG_D0 + REG0 (insn)] & 1;
- State.regs[REG_D0 + REG0 (insn)]
- >>= State.regs[REG_D0 + REG1 (insn)];
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
-}
-
-/* lsr imm8, dn */
-void OP_F8C400 (insn, extension)
- unsigned long insn, extension;
-{
- int z, n, c;
-
- c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
- State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff);
- z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
-}
-
-/* asl dm, dn */
-void OP_F290 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0 (insn)]
- <<= State.regs[REG_D0 + REG1 (insn)];
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* asl imm8, dn */
-void OP_F8C000 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff);
- z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* asl2 dn */
-void OP_54 (insn, extension)
- unsigned long insn, extension;
-{
- int n, z;
-
- State.regs[REG_D0 + REG0 (insn)] <<= 2;
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* ror dn */
-void OP_F284 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long value;
- int c,n,z;
-
- value = State.regs[REG_D0 + REG0 (insn)];
- c = (value & 0x1);
-
- value >>= 1;
- value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
- State.regs[REG_D0 + REG0 (insn)] = value;
- z = (value == 0);
- n = (value & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
-}
-
-/* rol dn */
-void OP_F280 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long value;
- int c,n,z;
-
- value = State.regs[REG_D0 + REG0 (insn)];
- c = (value & 0x80000000) ? 1 : 0;
-
- value <<= 1;
- value |= ((PSW & PSW_C) != 0);
- State.regs[REG_D0 + REG0 (insn)] = value;
- z = (value == 0);
- n = (value & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
-}
-
-/* beq label:8 */
-void OP_C800 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (PSW & PSW_Z)
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* bne label:8 */
-void OP_C900 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (!(PSW & PSW_Z))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* bgt label:8 */
-void OP_C100 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (!((PSW & PSW_Z)
- || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* bge label:8 */
-void OP_C200 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* ble label:8 */
-void OP_C300 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if ((PSW & PSW_Z)
- || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* blt label:8 */
-void OP_C000 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* bhi label:8 */
-void OP_C500 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* bcc label:8 */
-void OP_C600 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (!(PSW & PSW_C))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* bls label:8 */
-void OP_C700 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* bcs label:8 */
-void OP_C400 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- if (PSW & PSW_C)
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* bvc label:8 */
-void OP_F8E800 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 3 after we return, so
- we subtract two here to make things right. */
- if (!(PSW & PSW_V))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
-}
-
-/* bvs label:8 */
-void OP_F8E900 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 3 after we return, so
- we subtract two here to make things right. */
- if (PSW & PSW_V)
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
-}
-
-/* bnc label:8 */
-void OP_F8EA00 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 3 after we return, so
- we subtract two here to make things right. */
- if (!(PSW & PSW_N))
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
-}
-
-/* bns label:8 */
-void OP_F8EB00 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 3 after we return, so
- we subtract two here to make things right. */
- if (PSW & PSW_N)
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
-}
-
-/* bra label:8 */
-void OP_CA00 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 2 after we return, so
- we subtract two here to make things right. */
- State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
-}
-
-/* leq */
-void OP_D8 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (PSW & PSW_Z)
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lne */
-void OP_D9 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (!(PSW & PSW_Z))
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lgt */
-void OP_D1 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (!((PSW & PSW_Z)
- || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lge */
-void OP_D2 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lle */
-void OP_D3 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if ((PSW & PSW_Z)
- || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* llt */
-void OP_D0 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lhi */
-void OP_D5 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lcc */
-void OP_D6 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (!(PSW & PSW_C))
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lls */
-void OP_D7 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lcs */
-void OP_D4 (insn, extension)
- unsigned long insn, extension;
-{
- /* The dispatching code will add 1 after we return, so
- we subtract one here to make things right. */
- if (PSW & PSW_C)
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* lra */
-void OP_DA (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
-}
-
-/* setlb */
-void OP_DB (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4);
- State.regs[REG_LAR] = State.regs[REG_PC] + 5;
-}
-
-/* jmp (an) */
-void OP_F0F4 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
-}
-
-/* jmp label:16 */
-void OP_CC0000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
-}
-
-/* jmp label:32 */
-void OP_DC000000 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
-}
-
-/* call label:16,reg_list,imm8 */
-void OP_CD000000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int next_pc, sp;
- unsigned long mask;
-
- sp = State.regs[REG_SP];
- next_pc = State.regs[REG_PC] + 5;
- State.mem[sp] = next_pc & 0xff;
- State.mem[sp+1] = (next_pc & 0xff00) >> 8;
- State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
- State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
-
- mask = insn & 0xff;
-
- if (mask & 0x80)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 2]);
- }
-
- if (mask & 0x40)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 3]);
- }
-
- if (mask & 0x20)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 2]);
- }
-
- if (mask & 0x10)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 3]);
- }
-
- if (mask & 0x8)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0]);
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 1]);
- sp -= 4;
- store_word (sp, State.regs[REG_A0]);
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 1]);
- sp -= 4;
- store_word (sp, State.regs[REG_MDR]);
- sp -= 4;
- store_word (sp, State.regs[REG_LIR]);
- sp -= 4;
- store_word (sp, State.regs[REG_LAR]);
- sp -= 4;
- }
-
- /* Update the stack pointer, note that the register saves to do not
- modify SP. The SP adjustment is derived totally from the imm8
- field. */
- State.regs[REG_SP] -= extension;
- State.regs[REG_MDR] = next_pc;
- State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5;
-}
-
-/* call label:32,reg_list,imm8*/
-void OP_DD000000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int next_pc, sp, adjust;
- unsigned long mask;
-
- sp = State.regs[REG_SP];
- next_pc = State.regs[REG_PC] + 7;
- State.mem[sp] = next_pc & 0xff;
- State.mem[sp+1] = (next_pc & 0xff00) >> 8;
- State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
- State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
-
- mask = (extension & 0xff00) >> 8;
-
- if (mask & 0x80)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 2]);
- }
-
- if (mask & 0x40)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 3]);
- }
-
- if (mask & 0x20)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 2]);
- }
-
- if (mask & 0x10)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 3]);
- }
-
- if (mask & 0x8)
- {
- sp -= 4;
- store_word (sp, State.regs[REG_D0]);
- sp -= 4;
- store_word (sp, State.regs[REG_D0 + 1]);
- sp -= 4;
- store_word (sp, State.regs[REG_A0]);
- sp -= 4;
- store_word (sp, State.regs[REG_A0 + 1]);
- sp -= 4;
- store_word (sp, State.regs[REG_MDR]);
- sp -= 4;
- store_word (sp, State.regs[REG_LIR]);
- sp -= 4;
- store_word (sp, State.regs[REG_LAR]);
- sp -= 4;
- }
-
- /* Update the stack pointer, note that the register saves to do not
- modify SP. The SP adjustment is derived totally from the imm8
- field. */
- State.regs[REG_SP] -= (extension & 0xff);
- State.regs[REG_MDR] = next_pc;
- State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
-}
-
-/* calls (an) */
-void OP_F0F0 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int next_pc, sp;
-
- sp = State.regs[REG_SP];
- next_pc = State.regs[REG_PC] + 2;
- State.mem[sp] = next_pc & 0xff;
- State.mem[sp+1] = (next_pc & 0xff00) >> 8;
- State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
- State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
- State.regs[REG_MDR] = next_pc;
- State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
-}
-
-/* calls label:16 */
-void OP_FAFF0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int next_pc, sp;
-
- sp = State.regs[REG_SP];
- next_pc = State.regs[REG_PC] + 4;
- State.mem[sp] = next_pc & 0xff;
- State.mem[sp+1] = (next_pc & 0xff00) >> 8;
- State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
- State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
- State.regs[REG_MDR] = next_pc;
- State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4;
-}
-
-/* calls label:32 */
-void OP_FCFF0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int next_pc, sp;
-
- sp = State.regs[REG_SP];
- next_pc = State.regs[REG_PC] + 6;
- State.mem[sp] = next_pc & 0xff;
- State.mem[sp+1] = (next_pc & 0xff00) >> 8;
- State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
- State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
- State.regs[REG_MDR] = next_pc;
- State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6;
-}
-
-/* ret reg_list, imm8 */
-void OP_DF0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int sp, offset;
- unsigned long mask;
-
- State.regs[REG_SP] += insn & 0xff;
- sp = State.regs[REG_SP];
-
- offset = -4;
- mask = (insn & 0xff00) >> 8;
-
- if (mask & 0x80)
- {
- State.regs[REG_D0 + 2] = load_word (sp + offset);
- offset -= 4;
- }
-
- if (mask & 0x40)
- {
- State.regs[REG_D0 + 3] = load_word (sp + offset);
- offset -= 4;
- }
-
- if (mask & 0x20)
- {
- State.regs[REG_A0 + 2] = load_word (sp + offset);
- offset -= 4;
- }
-
- if (mask & 0x10)
- {
- State.regs[REG_A0 + 3] = load_word (sp + offset);
- offset -= 4;
- }
-
- if (mask & 0x8)
- {
- State.regs[REG_D0] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_D0 + 1] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_A0] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_A0 + 1] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_MDR] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_LIR] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_LAR] = load_word (sp + offset);
- offset -= 4;
- }
-
- /* Restore the PC value. */
- State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
- | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
- State.regs[REG_PC] -= 3;
-}
-
-/* retf reg_list,imm8 */
-void OP_DE0000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int sp, offset;
- unsigned long mask;
-
- State.regs[REG_SP] += (insn & 0xff);
- sp = State.regs[REG_SP];
- State.regs[REG_PC] = State.regs[REG_MDR] - 3;
-
- offset = -4;
- mask = (insn & 0xff00) >> 8;
-
- if (mask & 0x80)
- {
- State.regs[REG_D0 + 2] = load_word (sp + offset);
- offset -= 4;
- }
-
- if (mask & 0x40)
- {
- State.regs[REG_D0 + 3] = load_word (sp + offset);
- offset -= 4;
- }
-
- if (mask & 0x20)
- {
- State.regs[REG_A0 + 2] = load_word (sp + offset);
- offset -= 4;
- }
-
- if (mask & 0x10)
- {
- State.regs[REG_A0 + 3] = load_word (sp + offset);
- offset -= 4;
- }
-
- if (mask & 0x8)
- {
- State.regs[REG_D0] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_D0 + 1] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_A0] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_A0 + 1] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_MDR] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_LIR] = load_word (sp + offset);
- offset -= 4;
- State.regs[REG_LAR] = load_word (sp + offset);
- offset -= 4;
- }
-}
-
-/* rets */
-void OP_F0FC (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int sp;
-
- sp = State.regs[REG_SP];
- State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
- | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
- State.regs[REG_PC] -= 2;
-}
-
-/* rti */
-void OP_F0FD (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int sp, next_pc;
-
- sp = State.regs[REG_SP];
- PSW = State.mem[sp] | (State.mem[sp + 1] << 8);
- State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8)
- | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24));
- State.regs[REG_SP] += 8;
-}
-
-/* trap */
-void OP_F0FE (insn, extension)
- unsigned long insn, extension;
-{
- unsigned int sp, next_pc;
-
- sp = State.regs[REG_SP];
- next_pc = State.regs[REG_PC] + 2;
- State.mem[sp] = next_pc & 0xff;
- State.mem[sp+1] = (next_pc & 0xff00) >> 8;
- State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
- State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
- State.regs[REG_PC] = 0x40000010 - 2;
-}
-
-/* syscall */
-void OP_F0C0 (insn, extension)
- unsigned long insn, extension;
-{
- /* We use this for simulated system calls; we may need to change
- it to a reserved instruction if we conflict with uses at
- Matsushita. */
- int save_errno = errno;
- errno = 0;
-
-/* Registers passed to trap 0 */
-
-/* Function number. */
-#define FUNC (State.regs[0])
-
-/* Parameters. */
-#define PARM1 (State.regs[1])
-#define PARM2 (load_word (State.regs[REG_SP] + 12))
-#define PARM3 (load_word (State.regs[REG_SP] + 16))
-
-/* Registers set by trap 0 */
-
-#define RETVAL State.regs[0] /* return value */
-#define RETERR State.regs[1] /* return error code */
-
-/* Turn a pointer in a register into a pointer into real memory. */
-
-#define MEMPTR(x) (State.mem + x)
-
- switch (FUNC)
- {
-#if !defined(__GO32__) && !defined(_WIN32)
-#ifdef TARGET_SYS_fork
- case TARGET_SYS_fork:
- RETVAL = fork ();
- break;
-#endif
-#ifdef TARGET_SYS_execve
- case TARGET_SYS_execve:
- RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
- (char **)MEMPTR (PARM3));
- break;
-#endif
-#ifdef TARGET_SYS_execv
- case TARGET_SYS_execv:
- RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
- break;
-#endif
-#endif /* ! GO32 and ! WIN32 */
-
- case TARGET_SYS_read:
- RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
- MEMPTR (PARM2), PARM3);
- break;
- case TARGET_SYS_write:
- RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
- MEMPTR (PARM2), PARM3);
- break;
- case TARGET_SYS_lseek:
- RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
- break;
- case TARGET_SYS_close:
- RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
- break;
- case TARGET_SYS_open:
- RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
- break;
- case TARGET_SYS_exit:
- /* EXIT - caller can look in PARM1 to work out the
- reason */
- if (PARM1 == 0xdead)
- State.exception = SIGABRT;
- else
- State.exception = SIGQUIT;
- State.exited = 1;
- break;
-
- case TARGET_SYS_stat: /* added at hmsi */
- /* stat system call */
- {
- struct stat host_stat;
- reg_t buf;
-
- RETVAL = stat (MEMPTR (PARM1), &host_stat);
-
- buf = PARM2;
-
- /* Just wild-assed guesses. */
- store_half (buf, host_stat.st_dev);
- store_half (buf + 2, host_stat.st_ino);
- store_word (buf + 4, host_stat.st_mode);
- store_half (buf + 8, host_stat.st_nlink);
- store_half (buf + 10, host_stat.st_uid);
- store_half (buf + 12, host_stat.st_gid);
- store_half (buf + 14, host_stat.st_rdev);
- store_word (buf + 16, host_stat.st_size);
- store_word (buf + 20, host_stat.st_atime);
- store_word (buf + 28, host_stat.st_mtime);
- store_word (buf + 36, host_stat.st_ctime);
- }
- break;
-
-#ifdef TARGET_SYS_chown
- case TARGET_SYS_chown:
- RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
- break;
-#endif
- case TARGET_SYS_chmod:
- RETVAL = chmod (MEMPTR (PARM1), PARM2);
- break;
-#ifdef TARGET_SYS_time
- case TARGET_SYS_time:
- RETVAL = time ((void*) MEMPTR (PARM1));
- break;
-#endif
-#ifdef TARGET_SYS_times
- case TARGET_SYS_times:
- {
- struct tms tms;
- RETVAL = times (&tms);
- store_word (PARM1, tms.tms_utime);
- store_word (PARM1 + 4, tms.tms_stime);
- store_word (PARM1 + 8, tms.tms_cutime);
- store_word (PARM1 + 12, tms.tms_cstime);
- break;
- }
-#endif
-#ifdef TARGET_SYS_gettimeofday
- case TARGET_SYS_gettimeofday:
- {
- struct timeval t;
- struct timezone tz;
- RETVAL = gettimeofday (&t, &tz);
- store_word (PARM1, t.tv_sec);
- store_word (PARM1 + 4, t.tv_usec);
- store_word (PARM2, tz.tz_minuteswest);
- store_word (PARM2 + 4, tz.tz_dsttime);
- break;
- }
-#endif
-#ifdef TARGET_SYS_utime
- case TARGET_SYS_utime:
- /* Cast the second argument to void *, to avoid type mismatch
- if a prototype is present. */
- RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
- break;
-#endif
- default:
- abort ();
- }
- RETERR = errno;
- errno = save_errno;
-}
-
-/* rtm */
-void OP_F0FF (insn, extension)
- unsigned long insn, extension;
-{
- abort ();
-}
-
-/* nop */
-void OP_CB (insn, extension)
- unsigned long insn, extension;
-{
-}
-
-/* putx dm,dm */
-void OP_F500 (insn, extension)
- unsigned long insn, extension;
-{
- State.regs[REG_MDRQ] = State.regs[REG_D0 + REG0 (insn)];
-}
-
-/* getx dm,dm */
-void OP_F6F0 (insn, extension)
- unsigned long insn, extension;
-{
- int z, n;
- z = (State.regs[REG_MDRQ] == 0);
- n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
- State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDRQ];
-
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
-}
-
-/* mulq dm,dn */
-void OP_F600 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)]
- * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]);
- State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* mulq imm8,dn */
-void OP_F90000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_8 (insn)]
- * (signed64)(signed32)SEXT8 (insn & 0xff));
- State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* mulq imm16,dn */
-void OP_FB000000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)]
- * (signed64)(signed32)SEXT16 (insn & 0xffff));
- State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* mulq imm32,dn */
-void OP_FD000000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)]
- * (signed64)(signed32)(((insn & 0xffff) << 16) + extension));
- State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* mulqu dm,dn */
-void OP_F610 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((unsigned64) State.regs[REG_D0 + REG0 (insn)]
- * (unsigned64) State.regs[REG_D0 + REG1 (insn)]);
- State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* mulqu imm8,dn */
-void OP_F91400 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((unsigned64)State.regs[REG_D0 + REG0_8 (insn)]
- * (unsigned64)SEXT8 (insn & 0xff));
- State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* mulqu imm16,dn */
-void OP_FB140000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)]
- * (unsigned64) SEXT16 (insn & 0xffff));
- State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* mulqu imm32,dn */
-void OP_FD140000 (insn, extension)
- unsigned long insn, extension;
-{
- unsigned long long temp;
- int n, z;
-
- temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)]
- * (unsigned64)(((insn & 0xffff) << 16) + extension));
- State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
- State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
- z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
- n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
- PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
- PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
-}
-
-/* sat16 dm,dn */
-void OP_F640 (insn, extension)
- unsigned long insn, extension;
-{
- int temp;
-
- temp = State.regs[REG_D0 + REG1 (insn)];
- temp = (temp > 0x7fff ? 0x7fff : temp);
- temp = (temp < -0x8000 ? -0x8000 : temp);
- State.regs[REG_D0 + REG0 (insn)] = temp;
-}
-
-/* sat24 dm,dn */
-void OP_F650 (insn, extension)
- unsigned long insn, extension;
-{
- int temp;
-
- temp = State.regs[REG_D0 + REG1 (insn)];
- temp = (temp > 0x7fffff ? 0x7fffff : temp);
- temp = (temp < -0x800000 ? -0x800000 : temp);
- State.regs[REG_D0 + REG0 (insn)] = temp;
-}
-
-/* bsch dm,dn */
-void OP_F670 (insn, extension)
- unsigned long insn, extension;
-{
- int temp, c;
-
- temp = State.regs[REG_D0 + REG1 (insn)];
- temp <<= (State.regs[REG_D0 + REG0 (insn)] & 0x1f);
- c = (temp != 0 ? 1 : 0);
- PSW &= ~(PSW_C);
- PSW |= (c ? PSW_C : 0);
-}
-
-/* breakpoint */
-void
-OP_FF (insn, extension)
- unsigned long insn, extension;
-{
- State.exception = SIGTRAP;
- PC -= 1;
-}
-
[-- Attachment #3: Type: text/plain, Size: 188 bytes --]
--
Alexandre Oliva http://www.ic.unicamp.br/~oliva/
Red Hat Compiler Engineer aoliva@{redhat.com, gcc.gnu.org}
Free Software Evangelist oliva@{lsd.ic.unicamp.br, gnu.org}
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2003-08-02 14:26 ` Andrew Cagney
2004-06-21 13:59 ` Alexandre Oliva
@ 2004-06-26 22:00 ` Alexandre Oliva
2004-06-26 22:18 ` Alexandre Oliva
2 siblings, 0 replies; 12+ messages in thread
From: Alexandre Oliva @ 2004-06-26 22:00 UTC (permalink / raw)
To: Andrew Cagney; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 264 bytes --]
On Aug 2, 2003, Andrew Cagney <ac131313@redhat.com> wrote:
> The code needs to use strict ISO C. It might be easier to just
> convert everything.
This patch completes the conversion of the current code in sim/mn10300
to ISO C. I'm checking it in as obvious.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: mn10300-sim-isoc.patch --]
[-- Type: text/x-patch, Size: 7520 bytes --]
Index: sim/mn10300/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* interp.c, mn10300_sim.h, op_utils.c: Convert function prototypes
and definitions to ISO C.
Index: sim/mn10300/interp.c
===================================================================
RCS file: /cvs/src/src/sim/mn10300/interp.c,v
retrieving revision 1.3
diff -u -p -r1.3 interp.c
--- sim/mn10300/interp.c 26 Jun 2004 18:45:53 -0000 1.3
+++ sim/mn10300/interp.c 26 Jun 2004 21:50:02 -0000
@@ -47,12 +47,11 @@ enum {
};
static SIM_RC
-mn10300_option_handler (sd, cpu, opt, arg, is_command)
- SIM_DESC sd;
- sim_cpu *cpu;
- int opt;
- char *arg;
- int is_command;
+mn10300_option_handler (SIM_DESC sd,
+ sim_cpu *cpu,
+ int opt,
+ char *arg,
+ int is_command)
{
int cpu_nr;
switch (opt)
@@ -88,11 +87,10 @@ SIM_DESC simulator;
/* These default values correspond to expected usage for the chip. */
SIM_DESC
-sim_open (kind, cb, abfd, argv)
- SIM_OPEN_KIND kind;
- host_callback *cb;
- struct bfd *abfd;
- char **argv;
+sim_open (SIM_OPEN_KIND kind,
+ host_callback *cb,
+ struct bfd *abfd,
+ char **argv)
{
SIM_DESC sd = sim_state_alloc (kind, cb);
mn10300_callback = cb;
@@ -304,20 +302,17 @@ sim_open (kind, cb, abfd, argv)
void
-sim_close (sd, quitting)
- SIM_DESC sd;
- int quitting;
+sim_close (SIM_DESC sd, int quitting)
{
sim_module_uninstall (sd);
}
SIM_RC
-sim_create_inferior (sd, prog_bfd, argv, env)
- SIM_DESC sd;
- struct bfd *prog_bfd;
- char **argv;
- char **env;
+sim_create_inferior (SIM_DESC sd,
+ struct bfd *prog_bfd,
+ char **argv,
+ char **env)
{
memset (&State, 0, sizeof (State));
if (prog_bfd != NULL) {
@@ -331,9 +326,7 @@ sim_create_inferior (sd, prog_bfd, argv,
}
void
-sim_do_command (sd, cmd)
- SIM_DESC sd;
- char *cmd;
+sim_do_command (SIM_DESC sd, char *cmd)
{
char *mm_cmd = "memory-map";
char *int_cmd = "interrupt";
@@ -353,41 +346,34 @@ sim_do_command (sd, cmd)
but need to be changed to use the memory map. */
uint8
-get_byte (x)
- uint8 *x;
+get_byte (uint8 *x)
{
return *x;
}
uint16
-get_half (x)
- uint8 *x;
+get_half (uint8 *x)
{
uint8 *a = x;
return (a[1] << 8) + (a[0]);
}
uint32
-get_word (x)
- uint8 *x;
+get_word (uint8 *x)
{
uint8 *a = x;
return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
}
void
-put_byte (addr, data)
- uint8 *addr;
- uint8 data;
+put_byte (uint8 *addr, uint8 data)
{
uint8 *a = addr;
a[0] = data;
}
void
-put_half (addr, data)
- uint8 *addr;
- uint16 data;
+put_half (uint8 *addr, uint16 data)
{
uint8 *a = addr;
a[0] = data & 0xff;
@@ -395,9 +381,7 @@ put_half (addr, data)
}
void
-put_word (addr, data)
- uint8 *addr;
- uint32 data;
+put_word (uint8 *addr, uint32 data)
{
uint8 *a = addr;
a[0] = data & 0xff;
@@ -407,22 +391,20 @@ put_word (addr, data)
}
int
-sim_fetch_register (sd, rn, memory, length)
- SIM_DESC sd;
- int rn;
- unsigned char *memory;
- int length;
+sim_fetch_register (SIM_DESC sd,
+ int rn,
+ unsigned char *memory,
+ int length)
{
put_word (memory, State.regs[rn]);
return -1;
}
int
-sim_store_register (sd, rn, memory, length)
- SIM_DESC sd;
- int rn;
- unsigned char *memory;
- int length;
+sim_store_register (SIM_DESC sd,
+ int rn,
+ unsigned char *memory,
+ int length)
{
State.regs[rn] = get_word (memory);
return -1;
@@ -431,13 +413,13 @@ sim_store_register (sd, rn, memory, leng
void
mn10300_core_signal (SIM_DESC sd,
- sim_cpu *cpu,
- sim_cia cia,
- unsigned map,
- int nr_bytes,
- address_word addr,
- transfer_type transfer,
- sim_core_signals sig)
+ sim_cpu *cpu,
+ sim_cia cia,
+ unsigned map,
+ int nr_bytes,
+ address_word addr,
+ transfer_type transfer,
+ sim_core_signals sig)
{
const char *copy = (transfer == read_transfer ? "read" : "write");
address_word ip = CIA_ADDR (cia);
Index: sim/mn10300/mn10300_sim.h
===================================================================
RCS file: /cvs/src/src/sim/mn10300/mn10300_sim.h,v
retrieving revision 1.4
diff -u -p -r1.4 mn10300_sim.h
--- sim/mn10300/mn10300_sim.h 26 Jun 2004 18:45:53 -0000 1.4
+++ sim/mn10300/mn10300_sim.h 26 Jun 2004 21:50:02 -0000
@@ -161,32 +161,32 @@ sim_core_write_unaligned_4 (STATE_CPU (s
/* Function declarations. */
-uint32 get_word PARAMS ((uint8 *));
-uint16 get_half PARAMS ((uint8 *));
-uint8 get_byte PARAMS ((uint8 *));
-void put_word PARAMS ((uint8 *, uint32));
-void put_half PARAMS ((uint8 *, uint16));
-void put_byte PARAMS ((uint8 *, uint8));
+uint32 get_word (uint8 *);
+uint16 get_half (uint8 *);
+uint8 get_byte (uint8 *);
+void put_word (uint8 *, uint32);
+void put_half (uint8 *, uint16);
+void put_byte (uint8 *, uint8);
-extern uint8 *map PARAMS ((SIM_ADDR addr));
+extern uint8 *map (SIM_ADDR addr);
-INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned32 source, unsigned32 destReg));
-INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned32 source, unsigned32 destReg));
-INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned32 leftOpnd, unsigned32 rightOpnd));
-INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned32 source, unsigned32 destReg));
-INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned32 source, unsigned32 destReg));
-INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned32 leftOpnd, unsigned32 rightOpnd));
-INLINE_SIM_MAIN (int) syscall_read_mem PARAMS ((host_callback *cb,
- struct cb_syscall *sc,
- unsigned long taddr,
- char *buf,
- int bytes));
-INLINE_SIM_MAIN (int) syscall_write_mem PARAMS ((host_callback *cb,
- struct cb_syscall *sc,
- unsigned long taddr,
- const char *buf,
- int bytes));
-INLINE_SIM_MAIN (void) do_syscall PARAMS ((void));
+INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg);
+INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg);
+INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd);
+INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg);
+INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg);
+INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd);
+INLINE_SIM_MAIN (int) syscall_read_mem (host_callback *cb,
+ struct cb_syscall *sc,
+ unsigned long taddr,
+ char *buf,
+ int bytes);
+INLINE_SIM_MAIN (int) syscall_write_mem (host_callback *cb,
+ struct cb_syscall *sc,
+ unsigned long taddr,
+ const char *buf,
+ int bytes);
+INLINE_SIM_MAIN (void) do_syscall (void);
void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
Index: sim/mn10300/op_utils.c
===================================================================
RCS file: /cvs/src/src/sim/mn10300/op_utils.c,v
retrieving revision 1.2
diff -u -p -r1.2 op_utils.c
--- sim/mn10300/op_utils.c 18 May 2000 22:56:28 -0000 1.2
+++ sim/mn10300/op_utils.c 26 Jun 2004 21:50:02 -0000
@@ -164,7 +164,7 @@ syscall_write_mem (host_callback *cb, st
/* syscall */
INLINE_SIM_MAIN (void)
-do_syscall ()
+do_syscall (void)
{
/* We use this for simulated system calls; we may need to change
[-- Attachment #3: Type: text/plain, Size: 188 bytes --]
--
Alexandre Oliva http://www.ic.unicamp.br/~oliva/
Red Hat Compiler Engineer aoliva@{redhat.com, gcc.gnu.org}
Free Software Evangelist oliva@{lsd.ic.unicamp.br, gnu.org}
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: AM33/2.0 support for mn10300-elf
2003-08-02 14:26 ` Andrew Cagney
2004-06-21 13:59 ` Alexandre Oliva
2004-06-26 22:00 ` Alexandre Oliva
@ 2004-06-26 22:18 ` Alexandre Oliva
2 siblings, 0 replies; 12+ messages in thread
From: Alexandre Oliva @ 2004-06-26 22:18 UTC (permalink / raw)
To: Andrew Cagney; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 602 bytes --]
On Aug 2, 2003, Andrew Cagney <ac131313@redhat.com> wrote:
> For the simulator, two refinements:
> +void fpu_disabled_exception PARAMS ((SIM_DESC, sim_cpu *,
> address_word));
> The code needs to use strict ISO C. It might be easier to just
> convert everything.
> + store_word (addr + 4, data.high);
> +}
> #endif /* not WITH_COMMON */
> The MN10300 switched to sim/common long ago, the #if !WITH_COMMON code
> should be deleted.
> they can both be considered pretty "obvious".
> Other than that, its approved.
Having fixed the two items above, I'm going ahead and checking this
in.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: mn10300-sim-am33-2.patch --]
[-- Type: text/x-patch, Size: 160128 bytes --]
Index: sim/mn10300/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2000-08-07 Graham Stott <grahams@cygnus.co.uk>
* am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo.
2000-05-29 Alexandre Oliva <aoliva@cygnus.com>
* interp.c (fpu_disabled_exception, fpu_unimp_exception,
fpu_check_signal_exception): Take additional state arguments.
Print exception type and call program_interrupt. Adjust callers.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional
arguments.
* mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception,
fpu_check_signal_exception): Adjust prototypes.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise.
* am33-2.igen: Adjust calls.
2000-05-19 Alexandre Oliva <aoliva@cygnus.com>
* op_utils.c (cmp2fcc): Moved...
* interp.c: ... here.
2000-05-18 Alexandre Oliva <aoliva@cygnus.com>
* am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or
`signed64' where type width is relevant.
2000-05-15 Alexandre Oliva <aoliva@cygnus.com>
* mn10300_sim.h: Include sim-fpu.h.
(FD2FPU, FPU2FD): Enclose the FD argument in parentheses.
(fpu_check_signal_exception): Declare.
(struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise.
(FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare.
* interp.c (fpu_disabled_exception): Document.
(fpu_unimp_exception): Likewise.
(fpu_check_signal_exception): Define.
(reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise.
(reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise.
(REG2VAL, ROUND, VAL2REG): Define shorthands.
(fpu_status_ok): Define.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define.
* am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv,
fmadd, fmsub, fnmadd, fnmsub): Use new functions.
2000-04-27 Alexandre Oliva <aoliva@cygnus.com>
* interp.c (sim_create_inferior): Set PSW bit to enable FP insns
if architecture is AM33/2.0.
* am33.igen: Include am33-2.igen.
2000-04-23 Alexandre Oliva <aoliva@cygnus.com>
* mn10300.igen (movm, call, ret, retf): Check for am33_2 too.
* am33.igen (movm): Likewise.
2000-04-19 Alexandre Oliva <aoliva@cygnus.com>
* am33.igen: Added `*am33_2' to some instructions that were
missing it.
2000-04-07 Alexandre Oliva <aoliva@cygnus.com>
* am33-2.igen: New file. All insns implemented, but FP flags are
only set for fcmp, exceptional conditions are not handled yet.
* Makefile.in (IGEN_INSN): Added am33-2.igen.
(tmp-igen): Added -M am33_2.
* mn10300.igen, am33.igen: Added `*am33_2' to all insns.
* gencode.c: Support FMT_D3.
* mn10300_sim.h (dword): New type.
(struct _state): Added fpregs.
(REG_FPCR, FPCR): New define. All assorted bitmaps.
(XS2FS, AS2FS, Xf2FD): New macros.
(FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise.
(load_dword, store_dword): New functions or macros.
(u642dw, dw2u64): New functions.
(fpu_disabled_exception, fpu_unimp_exception): Declared.
* interp.c (fpu_disabled_exception): Defined; no actual
implementation.
(fpu_unimp_exception): Likewise.
* op_utils.c (cmp2fcc): New function.
Index: sim/mn10300/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mn10300/Makefile.in,v
retrieving revision 1.8
diff -u -p -r1.8 Makefile.in
--- sim/mn10300/Makefile.in 26 Jun 2004 21:44:56 -0000 1.8
+++ sim/mn10300/Makefile.in 26 Jun 2004 22:15:58 -0000
@@ -79,7 +79,7 @@ clean-igen:
cd ../igen && $(MAKE)
IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
-IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen
+IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen $(srcdir)/am33-2.igen
IGEN_DC=$(srcdir)/mn10300.dc
tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
cd ../igen && $(MAKE)
@@ -87,6 +87,7 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../ige
$(IGEN_TRACE) \
-G gen-direct-access \
-M mn10300,am33 -G gen-multi-sim=am33 \
+ -M am33_2 \
-I $(srcdir) \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
Index: sim/mn10300/am33-2.igen
===================================================================
RCS file: sim/mn10300/am33-2.igen
diff -N sim/mn10300/am33-2.igen
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sim/mn10300/am33-2.igen 26 Jun 2004 22:15:59 -0000
@@ -0,0 +1,2285 @@
+// data cache pre-fetch:
+
+// 1111 1001 1010 0110 Rm.. 0000; dcpf (Rm)
+8.0xf9+8.0xa6+4.RN2,4.0000:D1a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+ load_word (State.regs[srcreg]);
+}
+
+// 1111 1001 1010 0111 0000 0000; dcpf (sp)
+8.0xf9+8.0xa7+8.0x00:D1b:::dcpf
+"dcpf"
+*am33_2
+{
+ PC = cia;
+
+ load_word (SP);
+}
+
+// 1111 1011 1010 0110 Ri.. Rm.. 0000 0000; dcpf (Ri,Rm)
+8.0xfb+8.0xa6+4.RN2,4.RN0+8.0x00:D2a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srci, srcm;
+
+ PC = cia;
+
+ srci = translate_rreg (SD_, RN2);
+ srcm = translate_rreg (SD_, RN0);
+
+ load_word (State.regs[srci] + State.regs[srcm]);
+}
+
+// 1111 1011 1010 0111 Rm.. 0000 IMM8; dcpf (d8,Rm)
+8.0xfb+8.0xa7+4.RN2,4.0000+8.IMM8:D2b:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
+8.0xfd+8.0xa7+4.RN2,4.0000+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg] + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1110 0100 0110 Rm.. 0000 IMM32; dcpf (d32,Rm)
+8.0xfe+8.0x46+4.RN2,4.0000+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// bit operations with imm8,(abs16) addressing mode:
+
+// 1111 1110 1000 0010 ABS16 IMM8; btst imm8,(abs16)
+8.0xfe+8.0x82+8.IMM16A+8.IMM16B+8.IMM8:D3:::btst
+"btst"
+*am33_2
+{
+ PC = cia;
+ genericBtst (IMM8, FETCH16 (IMM16A, IMM16B));
+}
+
+// 1111 1110 1000 0000 ABS16 IMM8; bset imm8,(abs16)
+8.0xfe+8.0x80+8.IMM16A+8.IMM16B+8.IMM8:D3:::bset
+"bset"
+*am33_2
+{
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH16 (IMM16A, IMM16B));
+ z = (temp & IMM8) == 0;
+ temp |= IMM8;
+ store_byte (FETCH16 (IMM16A, IMM16B), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+// 1111 1110 1000 0001 ABS16 IMM8; bclr imm8,(abs16)
+8.0xfe+8.0x81+8.IMM16A+8.IMM16B+8.IMM8:D3:::bclr
+"bclr"
+*am33_2
+{
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH16 (IMM16A, IMM16B));
+ z = (temp & IMM8) == 0;
+ temp = temp & ~(IMM8);
+ store_byte (FETCH16 (IMM16A, IMM16B), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+// single precision fmov:
+
+// 1111 1001 0010 000X Rm.. Sn..; fmov (Rm),FSn
+8.0xf9+4.2,3.0,1.X+4.Rm,4.Sn:D1a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ }
+}
+
+// 1111 1001 0010 001X Rm.. Sn..; fmov (Rm+),FSn
+8.0xf9+4.2,3.1,1.X+4.Rm,4.Sn:D1b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1001 0010 010X ---- Sn..; fmov (SP),FSn
+8.0xf9+4.2,3.2,1.X+4.0,4.Sn:D1c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ }
+}
+
+// 1111 1001 0010 011X Rm.. Sn..; fmov Rm,FSn
+8.0xf9+4.2,3.3,1.X+4.Rm,4.Sn:D1d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = State.regs[reg];
+ }
+}
+
+// 1111 1001 0011 00Y0 Sm.. Rn..; fmov FSm,(Rn)
+8.0xf9+4.3,2.0,1.Y,1.0+4.Sm,4.Rn:D1e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ }
+}
+
+// 1111 1001 0011 00Y1 Sm.. Rn..; fmov FSm,(Rn+)
+8.0xf9+4.3,2.0,1.Y,1.1+4.Sm,4.Rn:D1f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1001 0011 01Y0 Sm.. ----; fmov FSm,(SP)
+8.0xf9+4.3,2.1,1.Y,1.0+4.Sm,4.0:D1g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ }
+}
+
+// 1111 1001 0011 01Y1 Sm.. Rn..; fmov FSm,Rn
+8.0xf9+4.3,2.1,1.Y,1.1+4.Sm,4.Rn:D1h:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ State.regs[reg] = XS2FS (Y,Sm);
+ }
+}
+
+// 1111 1001 0100 00YX Sm.. Sn..; fmov FSm,FSn
+8.0xf9+4.4,2.0,1.Y,1.X+4.Sm,4.Sn:D1i:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ XS2FS (X,Sn) = XS2FS (Y,Sm);
+}
+
+// 1111 1011 0010 000X Rm.. Sn.. d8; fmov (d8,Rm),FSn
+8.0xfb+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM8:D2a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+ }
+}
+
+// 1111 1011 0010 001X Rm.. Sn.. d8; fmov (Rm+,imm8),FSn
+8.0xfb+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM8:D2b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1011 0010 010X ---- Sn.. d8; fmov (d8,SP),FSn
+8.0xfb+4.2,3.2,1.X+4.0,4.Sn+8.IMM8:D2c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg] + IMM8);
+ }
+}
+
+// 1111 1011 0010 0111 Ri.. Rm.. Sn.. --Z-; fmov (Ri,Rm),FSn
+8.0xfb+8.0x27+4.Ri,4.Rm+4.Sn,2.0,1.Z,1.0:D2d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ XS2FS (Z, Sn) = load_word (State.regs[ri] + State.regs[rm]);
+ }
+}
+
+// 1111 1011 0011 00Y0 Sm.. Rn.. d8; fmov FSm,(d8,Rn)
+8.0xfb+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM8:D2e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1011 0011 00Y1 Sm.. Rn.. d8; fmov FSm,(Rn+,d8)
+8.0xfb+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM8:D2f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1011 0011 01Y0 Sm.. ---- d8; fmov FSm,(d8,SP)
+8.0xfb+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM8:D2g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg] + IMM8, XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1011 0011 0111 Ri.. Rm.. Sm.. --Z-; fmov FSm,(Ri,Rm)
+8.0xfb+8.0x37+4.Ri,4.Rm+4.Sm,2.0,1.Z,1.0:D2h:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ store_word (State.regs[ri] + State.regs[rm], XS2FS (Z, Sm));
+ }
+}
+
+// 1111 1101 0010 000X Rm.. Sn.. d24; fmov (d24,Rm),FSn
+8.0xfd+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ }
+}
+
+// 1111 1101 0010 001X Rm.. Sn.. d24; fmov (Rm+,imm24),FSn
+8.0xfd+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1101 0010 010X ---- Sn.. d24; fmov (d24,SP),FSn
+8.0xfd+4.2,3.2,1.X+4.0,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg] + FETCH24 (IMM24A,
+ IMM24B, IMM24C));
+ }
+}
+
+// 1111 1101 0011 00Y0 Sm.. Rn.. d24; fmov FSm,(d24,Rn)
+8.0xfd+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1101 0011 00Y1 Sm.. Rn.. d24; fmov FSm,(Rn+,d24)
+8.0xfd+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1101 0011 01Y0 Sm.. ---- d24; fmov FSm,(d24,SP)
+8.0xfd+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg]
+ + FETCH24 (IMM24A,
+ IMM24B, IMM24C), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1110 0010 000X Rm.. Sn.. d32; fmov (d32,Rm),FSn
+8.0xfe+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ }
+}
+
+// 1111 1110 0010 001X Rm.. Sn.. d32; fmov (Rm+,imm32),FSn
+8.0xfe+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1110 0010 010X ---- Sn.. d32; fmov (d32,SP),FSn
+8.0xfe+4.2,3.2,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D));
+ }
+}
+
+// 1111 1110 0010 011X ---- Sn.. d32; fmov imm32,FSn
+8.0xfe+4.2,3.3,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ XS2FS (X, Sn) = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0011 00Y0 Sm.. Rn.. d32; fmov FSm,(d32,Rn)
+8.0xfe+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1110 0011 00Y1 Sm.. Rn.. d32; fmov FSm,(Rn+,d32)
+8.0xfe+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1110 0011 01Y0 Sm.. ---- d32; fmov FSm,(d32,SP)
+8.0xfe+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D), XS2FS (Y, Sm));
+ }
+}
+
+// double precision fmov:
+
+// 1111 1001 1010 000X Rm.. fn.-; fmov (Rm),FDn
+8.0xf9+4.0xa,3.0,1.X+4.Rm,3.fn,1.0:D1j:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ }
+}
+
+// 1111 1001 1010 001X Rm.. fn.-; fmov (Rm+),FDn
+8.0xf9+4.0xa,3.1,1.X+4.Rm,3.fn,1.0:D1k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1001 1010 010X ---- fn.-; fmov (SP),FDn
+8.0xf9+4.0xa,3.2,1.X+4.0,3.fn,1.0:D1l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ }
+}
+
+// 1111 1001 1011 00Y0 fm.- Rn..; fmov FDm,(Rn)
+8.0xf9+4.0xb,2.0,1.Y,1.0+3.fm,1.0,4.Rn:D1m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ }
+}
+
+// 1111 1001 1011 00Y1 fm.- Rn..; fmov FDm,(Rn+)
+8.0xf9+4.0xb,2.0,1.Y,1.1+3.fm,1.0,4.Rn:D1n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1001 1011 01Y0 fm.- ----; fmov FDm,(SP)
+8.0xf9+4.0xb,2.1,1.Y,1.0+3.fm,1.0,4.0:D1o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ }
+}
+
+// 1111 1001 1100 00YX fm.- fn.-; fmov FDm,FDn
+8.0xf9+4.0xc,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0111 Ri.. Rm.. fn.- --Z-; fmov (Ri,Rm),FDn
+8.0xfb+8.0x47+4.Ri,4.Rm+3.fn,1.0,2.0,1.Z,1.0:D2i:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ Xf2FD (Z,fn) = load_dword (State.regs[ri] + State.regs[rm]);
+ }
+}
+
+// 1111 1011 0101 0111 Ri.. Rn.. fm.- --Z-; fmov FDm,(Ri,Rn)
+8.0xfb+8.0x57+4.Ri,4.Rn+3.fm,1.0,2.0,1.Z,1.0:D2j:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rn = translate_rreg (SD_, Rn);
+ store_dword (State.regs[ri] + State.regs[rn], Xf2FD (Z,fm));
+ }
+}
+
+// 1111 1011 1010 000X Rm.. fn.- d8; fmov (d8,Rm),FDn
+8.0xfb+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM8:D2k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+ }
+}
+
+// 1111 1011 1010 001X Rm.. fn.- d8; fmov (Rm+,imm8),FDn
+8.0xfb+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM8:D2l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1011 1010 010X ---- fn.- d8; fmov (d8,SP),FDn
+8.0xfb+4.0xa,3.2,1.X+4.0,4.fn+8.IMM8:D2m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + IMM8);
+ }
+}
+
+// 1111 1011 1011 00Y0 fm.- Rn.. d8; fmov FDm,(d8,Rn)
+8.0xfb+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM8:D2n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1011 1011 00Y1 fm.- Rn.. d8; fmov FDm,(Rn+,d8)
+8.0xfb+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM8:D2o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1011 1011 01Y0 fm.- ---- d8; fmov FDm,(d8,SP)
+8.0xfb+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM8:D2p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg] + IMM8, Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1101 1010 000X Rm.. fn.- d24; fmov (d24,Rm),FDn
+8.0xfd+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ }
+}
+
+// 1111 1101 1010 001X Rm.. fn.- d24; fmov (Rm+,imm24),FDn
+8.0xfd+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1101 1010 010X ---- fn.- d24; fmov (d24,SP),FDn
+8.0xfd+4.0xa,3.2,1.X+4.0,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + FETCH24 (IMM24A,
+ IMM24B, IMM24C));
+ }
+}
+
+// 1111 1101 1011 00Y0 fm.- Rn.. d24; fmov FDm,(d24,Rn)
+8.0xfd+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1101 1011 00Y1 fm.- Rn.. d24; fmov FDm,(Rn+,d24)
+8.0xfd+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1101 1011 01Y0 fm.- ---- d24; fmov FDm,(d24,SP)
+8.0xfd+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg] + FETCH24 (IMM24A,
+ IMM24B, IMM24C), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1110 1010 000X Rm.. fn.- d32; fmov (d32,Rm),FDn
+8.0xfe+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ }
+}
+
+// 1111 1110 1010 001X Rm.. fn.- d32; fmov (Rm+,imm32),FDn
+8.0xfe+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1110 1010 010X ---- fn.- d32; fmov (d32,SP),FDn
+8.0xfe+4.0xa,3.2,1.X+4.0,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D));
+ }
+}
+
+// 1111 1110 1011 00Y0 fm.- Rn.. d32; fmov FDm,(d32,Rn)
+8.0xfe+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1110 1011 00Y1 fm.- Rn.. d32; fmov FDm,(Rn+,d32)
+8.0xfe+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1110 1011 01Y0 fm.- ---- d32; fmov FDm,(d32,SP)
+8.0xfe+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D), Xf2FD (Y, fm));
+ }
+}
+
+// FPCR fmov:
+
+// 1111 1001 1011 0101 Rm.. ----; fmov Rm,FPCR
+8.0xf9+8.0xb5+4.Rm,4.0:D1q:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ unsigned32 val = State.regs[reg];
+ FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+ | ((FPCR & ~val) & EF_MASK);
+ }
+}
+
+// 1111 1001 1011 0111 ---- Rn..; fmov FPCR,Rn
+8.0xf9+8.0xb7+4.0,4.Rn:D1r:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ State.regs[reg] = FPCR & FPCR_MASK;
+ }
+}
+
+// 1111 1101 1011 0101 imm32; fmov imm32,FPCR
+8.0xfd+8.0xb5+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+ | ((FPCR & ~val) & EF_MASK);
+ }
+}
+
+// fabs:
+
+// 1111 1001 0100 010X ---- Sn..; fabs FSn
+8.0xf9+4.4,3.2,1.X+4.0,4.Sn:D1a:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sn), in);
+ sim_fpu_abs (&out, &in);
+ FPU2FS (out, XS2FS (X,Sn));
+ }
+}
+
+// 1111 1001 1100 010X ---- Sn..; fabs FDn
+8.0xf9+4.0xc,3.2,1.X+4.0,3.fn,1.0:D1b:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0100 Sm.. ---- Sn.. X-Z-; fabs FSm,FSn
+8.0xfb+8.0x44+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sm), in);
+ sim_fpu_abs (&out, &in);
+ FPU2FS (out, XS2FS (Z,Sn));
+ }
+}
+
+// 1111 1011 1100 0100 fm.- ---- fn.- X-Z-; fabs FDm,FDn
+8.0xfb+8.0xc4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0100 011X ---- Sn..; fneg FSn
+8.0xf9+4.4,3.3,1.X+4.0,4.Sn:D1a:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sn), in);
+ sim_fpu_neg (&out, &in);
+ FPU2FS (out, XS2FS (X,Sn));
+ }
+}
+
+// 1111 1001 1100 011X ---- Sn..; fneg FDn
+8.0xf9+4.0xc,3.3,1.X+4.0,3.fn,1.0:D1b:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0110 Sm.. ---- Sn.. X-Z-; fneg FSm,FSn
+8.0xfb+8.0x46+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sm), in);
+ sim_fpu_neg (&out, &in);
+ FPU2FS (out, XS2FS (Z,Sn));
+ }
+}
+
+// 1111 1011 1100 0110 fm.- ---- fn.- X-Z-; fneg FDm,FDn
+8.0xfb+8.0xc6+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 000X ---- Sn..; frsqrt FSn
+8.0xf9+4.5,3.0,1.X+4.0,4.Sn:D1a:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1101 000X ---- fn.-; frsqrt FDn
+8.0xf9+4.0xd,3.0,1.X+4.0,3.fn,1.0:D1b:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0000 Sm.. ---- Sn.. X-Z-; frsqrt FSm,FSn
+8.0xfb+8.0x50+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sm), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1101 0000 fm.- ---- fn.- X-Z-; frsqrt FDm,FDn
+8.0xfb+8.0xd0+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 001X ---- Sn..; fsqrt FSn
+8.0xf9+4.5,3.1,1.X+4.0,4.Sn:D1a:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 1101 001X ---- fn.-; fsqrt FDn
+8.0xf9+4.0xd,3.1,1.X+4.0,3.fn,1.0:D1b:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0100 Sm.. ---- Sn.. X-Z-; fsqrt FSm,FSn
+8.0xfb+8.0x54+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 1101 0100 fm.- ---- fn.- X-Z-; fsqrt FDm,FDn
+8.0xfb+8.0xd4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 01YX Sm.. Sn..; fcmp FSm, FSn
+8.0xf9+4.5,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_cmp (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (Y,Sm), FP_SINGLE);
+}
+
+// 1111 1001 1101 01YX fm.- fn.-; fcmp FDm, FDn
+8.0xf9+4.0xd,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1110 0011 01Y1 Sm.. ---- IMM32; fcmp imm32, FSm
+8.0xfe+4.3,2.1,1.Y,1.1+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
+ }
+}
+
+// 1111 1001 0110 00YX Sm.. Sn..; fadd FSm, FSn
+8.0xf9+4.6,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_add (SD, CPU, cia,
+ &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 00YX fm.- fn.-; fadd FDm, FDn
+8.0xf9+4.0xe,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0000 Sm1. Sm2. Sn.. XYZ-; fadd FSm1, FSm2, FSn
+8.0xfb+8.0x60+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_add (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0000 fm1- fm2- fn.- XYZ-; fadd FDm1, FDm2, FDn
+8.0xfb+8.0xe0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 00YX Sm.. Sn.. IMM32; fadd imm32, FSm, FSn
+8.0xfe+4.6,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_add (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0110 01YX Sm.. Sn..; fsub FSm, FSn
+8.0xf9+4.6,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 01YX fm.- fn.-; fsub FDm, FDn
+8.0xf9+4.0xe,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0100 Sm1. Sm2. Sn.. XYZ-; fsub FSm1, FSm2, FSn
+8.0xfb+8.0x64+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0100 fm1- fm2- fn.- XYZ-; fsub FDm1, FDm2, FDn
+8.0xfb+8.0xe4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 01YX Sm.. Sn.. IMM32; fsub imm32, FSm, FSn
+8.0xfe+4.6,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0111 00YX Sm.. Sn..; fmul FSm, FSn
+8.0xf9+4.7,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_mul (SD, CPU, cia,
+ &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 00YX fm.- fn.-; fmul FDm, FDn
+8.0xf9+4.0xf,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0000 Sm1. Sm2. Sn.. XYZ-; fmul FSm1, FSm2, FSn
+8.0xfb+8.0x70+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_mul (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0000 fm1- fm2- fn.- XYZ-; fmul FDm1, FDm2, FDn
+8.0xfb+8.0xf0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 00YX Sm.. Sn.. IMM32; fmul imm32, FSm, FSn
+8.0xfe+4.7,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_mul (SD, CPU, cia,
+ &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0111 01YX Sm.. Sn..; fdiv FSm, FSn
+8.0xf9+4.7,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_div (SD, CPU, cia,
+ &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 01YX fm.- fn.-; fdiv FDm, FDn
+8.0xf9+4.0xf,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0100 Sm1. Sm2. Sn.. XYZ-; fdiv FSm1, FSm2, FSn
+8.0xfb+8.0x74+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_div (SD, CPU, cia,
+ &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0100 fm1- fm2- fn.- XYZ-; fdiv FDm1, FDm2, FDn
+8.0xfb+8.0xf4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 01YX Sm.. Sn.. IMM32; fdiv imm32, FSm, FSn
+8.0xfe+4.7,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_div (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1011 1000 00Sn Sm1. Sm2. Sm3. XYZA; fmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmadd
+"fmadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fmadd (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1000 01Sn Sm1. Sm2. Sm3. XYZA; fmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmsub
+"fmsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fmsub (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 00Sn Sm1. Sm2. Sm3. XYZA; fnmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmadd
+"fnmadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fnmadd (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 01Sn Sm1. Sm2. Sm3. XYZA; fnmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmsub
+"fnmsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fnmsub (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// conversion:
+
+// 1111 1011 0100 0000 Sm.. ---- Sn.. X-Z-; ftoi FSm,FSn
+8.0xfb+8.0x40+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::ftoi
+"ftoi"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0010 Sm.. ---- Sn.. X-Z-; itof FSm,FSn
+8.0xfb+8.0x42+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::itof
+"itof"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0010 Sm.. ---- fn.- X-Z-; ftod FSm,FDn
+8.0xfb+8.0x52+4.Sm,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2:::ftod
+"ftod"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0110 fm.- ---- Sn.. X-Z-; dtof FDm,FSn
+8.0xfb+8.0x56+3.fm,1.0,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::dtof
+"dtof"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// branching:
+
+// 1111 1000 1101 0000 d8; fbeq (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd0+8.D8:D1:::fbeq
+"fbeq"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_E))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0001 d8; fbne (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd1+8.D8:D1:::fbne
+"fbne"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0010 d8; fbgt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd2+8.D8:D1:::fbgt
+"fbgt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_G))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0011 d8; fbge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd3+8.D8:D1:::fbge
+"fbge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0100 d8; fblt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd4+8.D8:D1:::fblt
+"fblt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_L))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0101 d8; fble (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd5+8.D8:D1:::fble
+"fble"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0110 d8; fbuo (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd6+8.D8:D1:::fbuo
+"fbuo"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_U))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0111 d8; fblg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd7+8.D8:D1:::fblg
+"fblg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+// 1111 1000 1101 1000 d8; fbleg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd8+8.D8:D1:::fbleg
+"fbleg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1001 d8; fbug (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd9+8.D8:D1:::fbug
+"fbug"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1010 d8; fbuge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xda+8.D8:D1:::fbuge
+"fbuge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1011 d8; fbul (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdb+8.D8:D1:::fbul
+"fbul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1100 d8; fbule (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdc+8.D8:D1:::fbule
+"fbule"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1101 d8; fbue (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdd+8.D8:D1:::fbue
+"fbue"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0000; fleq
+8.0xf0+8.0xd0:D0:::fleq
+"fleq"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_E))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0001; flne
+8.0xf0+8.0xd1:D0:::flne
+"flne"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0010; flgt
+8.0xf0+8.0xd2:D0:::flgt
+"flgt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_G))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0011; flge
+8.0xf0+8.0xd3:D0:::flge
+"flge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0100; fllt
+8.0xf0+8.0xd4:D0:::fllt
+"fllt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_L))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0101; flle
+8.0xf0+8.0xd5:D0:::flle
+"flle"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0110; fluo
+8.0xf0+8.0xd6:D0:::fluo
+"fluo"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_U))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0111; fllg
+8.0xf0+8.0xd7:D0:::fllg
+"fllg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+// 1111 0000 1101 1000; flleg
+8.0xf0+8.0xd8:D0:::flleg
+"flleg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1001; flug
+8.0xf0+8.0xd9:D0:::flug
+"flug"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1010; fluge
+8.0xf0+8.0xda:D0:::fluge
+"fluge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1011; flul
+8.0xf0+8.0xdb:D0:::flul
+"flul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1100; flule
+8.0xf0+8.0xdc:D0:::flule
+"flule"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1101; flue
+8.0xf0+8.0xdd:D0:::flue
+"flue"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
Index: sim/mn10300/am33.igen
===================================================================
RCS file: /cvs/src/src/sim/mn10300/am33.igen,v
retrieving revision 1.8
diff -u -p -r1.8 am33.igen
--- sim/mn10300/am33.igen 26 Feb 2003 23:27:09 -0000 1.8
+++ sim/mn10300/am33.igen 26 Jun 2004 22:16:00 -0000
@@ -42,6 +42,7 @@
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_USP];
@@ -52,6 +53,7 @@
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
@@ -62,6 +64,7 @@
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
@@ -72,6 +75,7 @@
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = PC;
@@ -82,6 +86,7 @@
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_USP] = State.regs[REG_A0 + AM1];
@@ -91,6 +96,7 @@
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
@@ -100,6 +106,7 @@
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
@@ -110,6 +117,7 @@
8.0xf0+4.0xe,IMM4:D0t:::syscall
"syscall"
*am33
+*am33_2
{
unsigned32 sp, next_pc;
@@ -127,6 +135,7 @@
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_D0 + DN0] = PSW;
@@ -137,6 +146,7 @@
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
PSW = State.regs[REG_D0 + DM1];
@@ -146,6 +156,7 @@
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
@@ -157,6 +168,7 @@
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
@@ -168,6 +180,7 @@
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
@@ -179,6 +192,7 @@
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
@@ -191,6 +205,7 @@
8.0xf8+8.0xce+8.REGS:D1a:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
@@ -242,6 +257,7 @@
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x1)
@@ -283,6 +299,7 @@
8.0xf8+8.0xcf+8.REGS:D1b:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
@@ -291,6 +308,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
@@ -375,6 +393,7 @@
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
"and"
*am33
+*am33_2
{
PC = cia;
PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -384,6 +403,7 @@
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
"or"
*am33
+*am33_2
{
PC = cia;
PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -393,6 +413,7 @@
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -407,6 +428,7 @@
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -422,6 +444,7 @@
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
"extb"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -435,6 +458,7 @@
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
"extbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -448,6 +472,7 @@
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
"exth"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -461,6 +486,7 @@
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
"exthu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -474,6 +500,7 @@
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
"clr"
*am33
+*am33_2
{
int dstreg;
@@ -488,6 +515,7 @@
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
"add"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -501,6 +529,7 @@
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
"addc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
@@ -530,6 +559,7 @@
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
"sub"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -543,6 +573,7 @@
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
"subc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
@@ -572,6 +603,7 @@
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
"inc"
*am33
+*am33_2
{
int dstreg;
@@ -584,6 +616,7 @@
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
"inc4"
*am33
+*am33_2
{
int dstreg;
@@ -596,6 +629,7 @@
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2;
@@ -609,6 +643,7 @@
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
"mov"
*am33
+*am33_2
{
int dstreg, srcreg;
@@ -623,6 +658,7 @@
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -637,6 +673,7 @@
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
"and"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
@@ -657,6 +694,7 @@
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
"or"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
@@ -676,6 +714,7 @@
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
"xor"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
@@ -695,6 +734,7 @@
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
"not"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -713,6 +753,7 @@
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
"asr"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
@@ -736,6 +777,7 @@
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
"lsr"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n, c;
@@ -757,6 +799,7 @@
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
"asl"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
@@ -776,6 +819,7 @@
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
"asl2"
*am33
+*am33_2
{
int dstreg;
int n, z;
@@ -794,6 +838,7 @@
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
"ror"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
@@ -818,6 +863,7 @@
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
"rol"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
@@ -842,6 +888,7 @@
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
"mul"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
@@ -865,6 +912,7 @@
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
@@ -888,6 +936,7 @@
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
"div"
*am33
+*am33_2
{
int srcreg, dstreg;
signed64 temp;
@@ -913,6 +962,7 @@
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
"divu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
@@ -939,6 +989,7 @@
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -952,6 +1003,7 @@
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -965,6 +1017,7 @@
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -978,6 +1031,7 @@
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -991,6 +1045,7 @@
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1004,6 +1059,7 @@
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1017,6 +1073,7 @@
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1031,6 +1088,7 @@
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1045,6 +1103,7 @@
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -1057,6 +1116,7 @@
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -1069,6 +1129,7 @@
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -1081,6 +1142,7 @@
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -1093,6 +1155,7 @@
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -1105,6 +1168,7 @@
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -1117,6 +1181,7 @@
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1131,6 +1196,7 @@
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1146,6 +1212,7 @@
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@ -1174,6 +1241,7 @@
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned64 temp, sum;
@@ -1202,6 +1270,7 @@
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, sum;
@@ -1225,6 +1294,7 @@
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@ -1248,6 +1318,7 @@
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@ -1276,6 +1347,7 @@
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@ -1304,6 +1376,7 @@
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, temp2, sum;
@@ -1329,6 +1402,7 @@
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned32 temp, temp2, sum;
@@ -1354,6 +1428,7 @@
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
@@ -1374,6 +1449,7 @@
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
"dmachu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned32 temp;
@@ -1394,6 +1470,7 @@
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
"sat16"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, z, n;
@@ -1421,6 +1498,7 @@
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
"mcste"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1518,6 +1596,7 @@
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
"swap"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1535,6 +1614,7 @@
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
"swaph"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1552,6 +1632,7 @@
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
"swhw"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1567,6 +1648,7 @@
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg, dstreg;
@@ -1606,6 +1688,7 @@
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -1618,6 +1701,7 @@
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
@@ -1630,6 +1714,7 @@
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
"add"
*am33
+*am33_2
{
int dstreg;
@@ -1642,6 +1727,7 @@
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
"addc"
*am33
+*am33_2
{
int dstreg, imm;
int z, c, n, v;
@@ -1670,6 +1756,7 @@
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
@@ -1683,6 +1770,7 @@
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
"subc"
*am33
+*am33_2
{
int imm, dstreg;
int z, c, n, v;
@@ -1711,6 +1799,7 @@
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
@@ -1723,6 +1812,7 @@
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -1736,6 +1826,7 @@
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -1754,6 +1845,7 @@
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -1772,6 +1864,7 @@
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -1790,6 +1883,7 @@
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
@@ -1812,6 +1906,7 @@
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
@@ -1831,6 +1926,7 @@
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -1849,6 +1945,7 @@
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -1871,6 +1968,7 @@
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -1893,6 +1991,7 @@
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
@@ -1905,6 +2004,7 @@
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1918,6 +2018,7 @@
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1931,6 +2032,7 @@
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1944,6 +2046,7 @@
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1957,6 +2060,7 @@
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1970,6 +2074,7 @@
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1983,6 +2088,7 @@
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -1997,6 +2103,7 @@
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -2012,6 +2119,7 @@
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -2024,6 +2132,7 @@
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -2036,6 +2145,7 @@
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -2048,6 +2158,7 @@
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -2060,6 +2171,7 @@
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -2072,6 +2184,7 @@
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -2084,6 +2197,7 @@
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -2098,6 +2212,7 @@
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -2113,6 +2228,7 @@
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2140,6 +2256,7 @@
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2167,6 +2284,7 @@
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2194,6 +2312,7 @@
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2221,6 +2340,7 @@
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2248,6 +2368,7 @@
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -2275,6 +2396,7 @@
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
"mcste"
*am33
+*am33_2
{
int dstreg;
@@ -2371,6 +2493,7 @@
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
"add"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
@@ -2401,6 +2524,7 @@
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
"addc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
@@ -2431,6 +2555,7 @@
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
"sub"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
@@ -2461,6 +2586,7 @@
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
"subc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
@@ -2491,6 +2617,7 @@
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
"and"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@ -2513,6 +2640,7 @@
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
"or"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@ -2535,6 +2663,7 @@
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
"xor"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@ -2557,6 +2686,7 @@
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
"asr"
*am33
+*am33_2
{
int z, c, n;
signed32 temp;
@@ -2583,6 +2713,7 @@
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
"lsr"
*am33
+*am33_2
{
int z, c, n;
int srcreg1, srcreg2, dstreg;
@@ -2606,6 +2737,7 @@
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
"asl"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@ -2628,6 +2760,7 @@
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
"mul"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -2655,6 +2788,7 @@
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -2682,6 +2816,7 @@
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -2694,6 +2829,7 @@
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -2706,6 +2842,7 @@
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -2718,6 +2855,7 @@
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -2730,6 +2868,7 @@
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -2742,6 +2881,7 @@
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -2754,6 +2894,7 @@
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
"mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
@@ -2768,6 +2909,7 @@
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
@@ -2782,6 +2924,7 @@
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
@@ -2796,6 +2939,7 @@
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
@@ -2810,6 +2954,7 @@
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
@@ -2824,6 +2969,7 @@
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
@@ -2838,6 +2984,7 @@
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -2874,6 +3021,7 @@
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -2910,6 +3058,7 @@
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
@@ -2938,6 +3087,7 @@
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
@@ -2966,6 +3116,7 @@
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
@@ -2996,6 +3147,7 @@
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
@@ -3026,6 +3178,7 @@
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
@@ -3056,6 +3209,7 @@
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
@@ -3086,6 +3240,7 @@
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -3108,6 +3263,7 @@
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@ -3130,6 +3286,7 @@
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
"sat24"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, n, z;
@@ -3157,6 +3314,7 @@
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg1, srcreg2, dstreg;
@@ -3196,6 +3354,7 @@
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3208,6 +3367,7 @@
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
@@ -3220,6 +3380,7 @@
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
"add"
*am33
+*am33_2
{
int dstreg;
@@ -3232,6 +3393,7 @@
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
"addc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 sum, imm, reg2;
@@ -3259,6 +3421,7 @@
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
@@ -3271,6 +3434,7 @@
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
"subc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 difference, imm, reg2;
@@ -3298,6 +3462,7 @@
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
@@ -3310,6 +3475,7 @@
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3323,6 +3489,7 @@
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -3341,6 +3508,7 @@
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -3359,6 +3527,7 @@
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -3377,6 +3546,7 @@
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
@@ -3400,6 +3570,7 @@
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
@@ -3419,6 +3590,7 @@
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -3437,6 +3609,7 @@
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -3459,6 +3632,7 @@
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -3481,6 +3655,7 @@
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
@@ -3493,6 +3668,7 @@
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3508,6 +3684,7 @@
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3522,6 +3699,7 @@
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3537,6 +3715,7 @@
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3551,6 +3730,7 @@
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3566,6 +3746,7 @@
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3580,6 +3761,7 @@
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3594,6 +3776,7 @@
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3609,6 +3792,7 @@
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3622,6 +3806,7 @@
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -3635,6 +3820,7 @@
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -3648,6 +3834,7 @@
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -3661,6 +3848,7 @@
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -3674,6 +3862,7 @@
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -3687,6 +3876,7 @@
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3701,6 +3891,7 @@
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -3715,6 +3906,7 @@
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3742,6 +3934,7 @@
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3769,6 +3962,7 @@
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3796,6 +3990,7 @@
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3823,6 +4018,7 @@
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3850,6 +4046,7 @@
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
@@ -3877,6 +4074,7 @@
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3889,6 +4087,7 @@
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -3902,6 +4101,7 @@
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -3914,6 +4114,7 @@
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -3927,6 +4128,7 @@
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -3939,6 +4141,7 @@
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -3952,6 +4155,7 @@
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -3964,6 +4168,7 @@
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
@@ -3976,6 +4181,7 @@
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
"add"
*am33
+*am33_2
{
int dstreg;
@@ -3988,6 +4194,7 @@
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
"addc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, sum;
@@ -4016,6 +4223,7 @@
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
@@ -4028,6 +4236,7 @@
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
"subc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, difference;
@@ -4056,6 +4265,7 @@
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
@@ -4068,6 +4278,7 @@
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -4081,6 +4292,7 @@
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -4099,6 +4311,7 @@
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -4117,6 +4330,7 @@
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
@@ -4135,6 +4349,7 @@
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
@@ -4157,6 +4372,7 @@
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
@@ -4176,6 +4392,7 @@
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
@@ -4194,6 +4411,7 @@
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -4216,6 +4434,7 @@
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
@@ -4238,6 +4457,7 @@
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
@@ -4250,6 +4470,7 @@
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4264,6 +4485,7 @@
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4278,6 +4500,7 @@
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4292,6 +4515,7 @@
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4306,6 +4530,7 @@
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4320,6 +4545,7 @@
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4334,6 +4560,7 @@
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4348,6 +4575,7 @@
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4363,6 +4591,7 @@
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -4376,6 +4605,7 @@
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -4389,6 +4619,7 @@
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -4402,6 +4633,7 @@
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -4415,6 +4647,7 @@
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -4428,6 +4661,7 @@
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -4442,6 +4676,7 @@
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4456,6 +4691,7 @@
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -4471,6 +4707,7 @@
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
"mac"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
@@ -4499,6 +4736,7 @@
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
"macu"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
@@ -4527,6 +4765,7 @@
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
"macb"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
@@ -4550,6 +4789,7 @@
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
@@ -4573,6 +4813,7 @@
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
"mach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
@@ -4596,6 +4837,7 @@
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
"machu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
@@ -4619,6 +4861,7 @@
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
@@ -4644,6 +4887,7 @@
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
@@ -4669,6 +4913,7 @@
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
"dmulh"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
@@ -4689,6 +4934,7 @@
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
@@ -4709,6 +4955,7 @@
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
@@ -4721,6 +4968,7 @@
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
@@ -4733,6 +4981,7 @@
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
@@ -4745,6 +4994,7 @@
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
@@ -4757,6 +5007,7 @@
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
@@ -4769,6 +5020,7 @@
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
@@ -4781,6 +5033,7 @@
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4800,6 +5053,7 @@
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -4818,6 +5072,7 @@
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4837,6 +5092,7 @@
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -4855,6 +5111,7 @@
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -4872,6 +5129,7 @@
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -4888,6 +5146,7 @@
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4907,6 +5166,7 @@
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -4925,6 +5185,7 @@
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4947,6 +5208,7 @@
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -4968,6 +5230,7 @@
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -4987,6 +5250,7 @@
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5006,6 +5270,7 @@
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5025,6 +5290,7 @@
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5043,6 +5309,7 @@
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5060,6 +5327,7 @@
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5076,6 +5344,7 @@
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5093,6 +5362,7 @@
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5109,6 +5379,7 @@
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5126,6 +5397,7 @@
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5142,6 +5414,7 @@
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed int temp;
@@ -5162,6 +5435,7 @@
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed int temp;
@@ -5181,6 +5455,7 @@
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5198,6 +5473,7 @@
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5215,6 +5491,7 @@
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5232,6 +5509,7 @@
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5248,6 +5526,7 @@
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5267,6 +5546,7 @@
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5285,6 +5565,7 @@
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5304,6 +5585,7 @@
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5322,6 +5604,7 @@
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5339,6 +5622,7 @@
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5355,6 +5639,7 @@
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5374,6 +5659,7 @@
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5392,6 +5678,7 @@
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5414,6 +5701,7 @@
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5435,6 +5723,7 @@
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5454,6 +5743,7 @@
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5473,6 +5763,7 @@
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5492,6 +5783,7 @@
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5510,6 +5802,7 @@
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5529,6 +5822,7 @@
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5547,6 +5841,7 @@
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5566,6 +5861,7 @@
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5584,6 +5880,7 @@
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -5601,6 +5898,7 @@
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -5617,6 +5915,7 @@
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5636,6 +5935,7 @@
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5654,6 +5954,7 @@
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5676,6 +5977,7 @@
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5697,6 +5999,7 @@
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5716,6 +6019,7 @@
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5735,6 +6039,7 @@
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -5754,6 +6059,7 @@
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -5772,6 +6078,7 @@
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5790,6 +6097,7 @@
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
"add_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5807,6 +6115,7 @@
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5825,6 +6134,7 @@
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
"add_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5842,6 +6152,7 @@
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -5858,6 +6169,7 @@
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -5873,6 +6185,7 @@
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5891,6 +6204,7 @@
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
"add_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5908,6 +6222,7 @@
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5929,6 +6244,7 @@
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
"add_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5949,6 +6265,7 @@
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -5967,6 +6284,7 @@
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -5985,6 +6303,7 @@
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6003,6 +6322,7 @@
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
"add_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6020,6 +6340,7 @@
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6036,6 +6357,7 @@
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6051,6 +6373,7 @@
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6067,6 +6390,7 @@
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6082,6 +6406,7 @@
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6098,6 +6423,7 @@
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6113,6 +6439,7 @@
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
signed int temp;
@@ -6132,6 +6459,7 @@
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
signed int temp;
@@ -6150,6 +6478,7 @@
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6166,6 +6495,7 @@
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6182,6 +6512,7 @@
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6198,6 +6529,7 @@
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6213,6 +6545,7 @@
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6231,6 +6564,7 @@
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
"sub_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6248,6 +6582,7 @@
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6266,6 +6601,7 @@
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6283,6 +6619,7 @@
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6299,6 +6636,7 @@
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6314,6 +6652,7 @@
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6332,6 +6671,7 @@
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6349,6 +6689,7 @@
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6370,6 +6711,7 @@
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6390,6 +6732,7 @@
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6408,6 +6751,7 @@
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6426,6 +6770,7 @@
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6444,6 +6789,7 @@
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6461,6 +6807,7 @@
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6479,6 +6826,7 @@
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
"mov_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6496,6 +6844,7 @@
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6514,6 +6863,7 @@
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6531,6 +6881,7 @@
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
@@ -6547,6 +6898,7 @@
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
@@ -6562,6 +6914,7 @@
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6580,6 +6933,7 @@
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6597,6 +6951,7 @@
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6618,6 +6973,7 @@
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6638,6 +6994,7 @@
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6656,6 +7013,7 @@
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6674,6 +7032,7 @@
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@ -6692,6 +7051,7 @@
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
@@ -6709,6 +7069,7 @@
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6728,6 +7089,7 @@
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6746,6 +7108,7 @@
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6765,6 +7128,7 @@
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6783,6 +7147,7 @@
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -6800,6 +7165,7 @@
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -6816,6 +7182,7 @@
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6835,6 +7202,7 @@
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6853,6 +7221,7 @@
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6875,6 +7244,7 @@
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6896,6 +7266,7 @@
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6915,6 +7286,7 @@
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6934,6 +7306,7 @@
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -6953,6 +7326,7 @@
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -6971,6 +7345,7 @@
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -6995,6 +7370,7 @@
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7018,6 +7394,7 @@
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7042,6 +7419,7 @@
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7065,6 +7443,7 @@
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7089,6 +7468,7 @@
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7112,6 +7492,7 @@
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7136,6 +7517,7 @@
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7159,6 +7541,7 @@
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7185,6 +7568,7 @@
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7210,6 +7594,7 @@
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7234,6 +7619,7 @@
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7258,6 +7644,7 @@
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7282,6 +7669,7 @@
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@ -7305,6 +7693,7 @@
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7324,6 +7713,7 @@
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7342,6 +7732,7 @@
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7361,6 +7752,7 @@
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7379,6 +7771,7 @@
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -7396,6 +7789,7 @@
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -7412,6 +7806,7 @@
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7431,6 +7826,7 @@
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7449,6 +7845,7 @@
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7471,6 +7868,7 @@
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7492,6 +7890,7 @@
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7511,6 +7910,7 @@
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7530,6 +7930,7 @@
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7549,6 +7950,7 @@
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7567,6 +7969,7 @@
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7586,6 +7989,7 @@
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7605,6 +8009,7 @@
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7625,6 +8030,7 @@
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7644,6 +8050,7 @@
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -7662,6 +8069,7 @@
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -7679,6 +8087,7 @@
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7699,6 +8108,7 @@
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7718,6 +8128,7 @@
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7741,6 +8152,7 @@
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7763,6 +8175,7 @@
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7783,6 +8196,7 @@
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7803,6 +8217,7 @@
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7823,6 +8238,7 @@
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7842,6 +8258,7 @@
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7861,6 +8278,7 @@
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7879,6 +8297,7 @@
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7898,6 +8317,7 @@
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7916,6 +8336,7 @@
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -7933,6 +8354,7 @@
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -7949,6 +8371,7 @@
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -7968,6 +8391,7 @@
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -7986,6 +8410,7 @@
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8008,6 +8433,7 @@
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8029,6 +8455,7 @@
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8048,6 +8475,7 @@
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8067,6 +8495,7 @@
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8086,6 +8515,7 @@
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8104,6 +8534,7 @@
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8129,6 +8560,7 @@
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8153,6 +8585,7 @@
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8178,6 +8611,7 @@
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8202,6 +8636,7 @@
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@ -8224,6 +8659,7 @@
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
@@ -8245,6 +8681,7 @@
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8270,6 +8707,7 @@
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8294,6 +8732,7 @@
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8322,6 +8761,7 @@
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8349,6 +8789,7 @@
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8374,6 +8815,7 @@
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8399,6 +8841,7 @@
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@ -8424,6 +8867,7 @@
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@ -8448,6 +8892,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
"mov_llt"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8469,6 +8914,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
"mov_lgt"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8491,6 +8937,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
"mov_lge"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8512,6 +8959,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
"mov_lle"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8534,6 +8982,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
"mov_lcs"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8555,6 +9004,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
"mov_lhi"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8576,6 +9026,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
"mov_lcc"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8597,6 +9048,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
"mov_lls"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8618,6 +9070,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
"mov_leq"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8639,6 +9092,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
"mov_lne"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8660,6 +9114,7 @@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
"mov_lra"
*am33
+*am33_2
{
int srcreg, dstreg;
@@ -8674,3 +9129,4 @@
nia = PC;
}
+:include::am33_2:am33-2.igen
Index: sim/mn10300/interp.c
===================================================================
RCS file: /cvs/src/src/sim/mn10300/interp.c,v
retrieving revision 1.4
diff -u -p -r1.4 interp.c
--- sim/mn10300/interp.c 26 Jun 2004 21:53:47 -0000 1.4
+++ sim/mn10300/interp.c 26 Jun 2004 22:16:00 -0000
@@ -322,6 +322,9 @@ sim_create_inferior (SIM_DESC sd,
}
CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
+ PSW |= PSW_FE;
+
return SIM_RC_OK;
}
@@ -546,3 +549,569 @@ mn10300_cpu_exception_resume(SIM_DESC sd
}
State.exc_suspended = 0;
}
+
+/* This is called when an FP instruction is issued when the FP unit is
+ disabled, i.e., the FE bit of PSW is zero. It raises interrupt
+ code 0x1c0. */
+void
+fpu_disabled_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ sim_io_eprintf(sd, "FPU disabled exception\n");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called when the FP unit is enabled but one of the
+ unimplemented insns is issued. It raises interrupt code 0x1c8. */
+void
+fpu_unimp_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ sim_io_eprintf(sd, "Unimplemented FPU instruction exception\n");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called at the end of any FP insns that may have triggered
+ FP exceptions. If no exception is enabled, it returns immediately.
+ Otherwise, it raises an exception code 0x1d0. */
+void
+fpu_check_signal_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ if ((FPCR & EC_MASK) == 0)
+ return;
+
+ sim_io_eprintf(sd, "FPU %s%s%s%s%s exception\n",
+ (FPCR & EC_V) ? "V" : "",
+ (FPCR & EC_Z) ? "Z" : "",
+ (FPCR & EC_O) ? "O" : "",
+ (FPCR & EC_U) ? "U" : "",
+ (FPCR & EC_I) ? "I" : "");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* Convert a 32-bit single-precision FP value in the target platform
+ format to a sim_fpu value. */
+static void
+reg2val_32 (const void *reg, sim_fpu *val)
+{
+ FS2FPU (*(reg_t *)reg, *val);
+}
+
+/* Round the given sim_fpu value to single precision, following the
+ target platform rounding and denormalization conventions. On
+ AM33/2.0, round_near is the only rounding mode. */
+static int
+round_32 (sim_fpu *val)
+{
+ return sim_fpu_round_32 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 32-bit single-precision target
+ representation. */
+static void
+val2reg_32 (const sim_fpu *val, void *reg)
+{
+ FPU2FS (*val, *(reg_t *)reg);
+}
+
+/* Define the 32-bit single-precision conversion and rounding uniform
+ interface. */
+const struct fp_prec_t
+fp_single_prec = {
+ reg2val_32, round_32, val2reg_32
+};
+
+/* Convert a 64-bit double-precision FP value in the target platform
+ format to a sim_fpu value. */
+static void
+reg2val_64 (const void *reg, sim_fpu *val)
+{
+ FD2FPU (*(dword *)reg, *val);
+}
+
+/* Round the given sim_fpu value to double precision, following the
+ target platform rounding and denormalization conventions. On
+ AM33/2.0, round_near is the only rounding mode. */
+int
+round_64 (sim_fpu *val)
+{
+ return sim_fpu_round_64 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 64-bit double-precision target
+ representation. */
+static void
+val2reg_64 (const sim_fpu *val, void *reg)
+{
+ FPU2FD (*val, *(dword *)reg);
+}
+
+/* Define the 64-bit single-precision conversion and rounding uniform
+ interface. */
+const struct fp_prec_t
+fp_double_prec = {
+ reg2val_64, round_64, val2reg_64
+};
+
+/* Define shortcuts to the uniform interface operations. */
+#define REG2VAL(reg,val) (*ops->reg2val) (reg,val)
+#define ROUND(val) (*ops->round) (val)
+#define VAL2REG(val,reg) (*ops->val2reg) (val,reg)
+
+/* Check whether overflow, underflow or inexact exceptions should be
+ raised. */
+int
+fpu_status_ok (sim_fpu_status stat)
+{
+ if ((stat & sim_fpu_status_overflow)
+ && (FPCR & EE_O))
+ FPCR |= EC_O;
+ else if ((stat & (sim_fpu_status_underflow | sim_fpu_status_denorm))
+ && (FPCR & EE_U))
+ FPCR |= EC_U;
+ else if ((stat & (sim_fpu_status_inexact | sim_fpu_status_rounded))
+ && (FPCR & EE_I))
+ FPCR |= EC_I;
+ else if (stat & ~ (sim_fpu_status_overflow
+ | sim_fpu_status_underflow
+ | sim_fpu_status_denorm
+ | sim_fpu_status_inexact
+ | sim_fpu_status_rounded))
+ abort ();
+ else
+ return 1;
+ return 0;
+}
+
+/* Implement a 32/64 bit reciprocal square root, signaling FP
+ exceptions when appropriate. */
+void
+fpu_rsqrt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in, void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu in, med, out;
+
+ REG2VAL (reg_in, &in);
+ ROUND (&in);
+ FPCR &= ~ EC_MASK;
+ switch (sim_fpu_is (&in))
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NINF:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ break;
+
+ case SIM_FPU_IS_QNAN:
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ break;
+
+ case SIM_FPU_IS_PINF:
+ VAL2REG (&sim_fpu_zero, reg_out);
+ break;
+
+ case SIM_FPU_IS_PNUMBER:
+ {
+ /* Since we don't have a function to compute rsqrt directly,
+ use sqrt and inv. */
+ sim_fpu_status stat = 0;
+ stat |= sim_fpu_sqrt (&med, &in);
+ stat |= sim_fpu_inv (&out, &med);
+ stat |= ROUND (&out);
+ if (fpu_status_ok (stat))
+ VAL2REG (&out, reg_out);
+ }
+ break;
+
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ if (FPCR & EE_Z)
+ FPCR |= EC_Z;
+ else
+ {
+ /* Generate an INF with the same sign. */
+ sim_fpu_inv (&out, &in);
+ VAL2REG (&out, reg_out);
+ }
+ break;
+
+ default:
+ abort ();
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+static inline reg_t
+cmp2fcc (int res)
+{
+ switch (res)
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ return FCC_U;
+
+ case SIM_FPU_IS_NINF:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NDENORM:
+ return FCC_L;
+
+ case SIM_FPU_IS_PINF:
+ case SIM_FPU_IS_PNUMBER:
+ case SIM_FPU_IS_PDENORM:
+ return FCC_G;
+
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ return FCC_E;
+
+ default:
+ abort ();
+ }
+}
+
+/* Implement a 32/64 bit FP compare, setting the FPCR status and/or
+ exception bits as specified. */
+void
+fpu_cmp (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ const struct fp_prec_t *ops)
+{
+ sim_fpu m, n;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ FPCR &= ~ EC_MASK;
+ FPCR &= ~ FCC_MASK;
+ ROUND (&m);
+ ROUND (&n);
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ FPCR |= FCC_U;
+ }
+ else
+ FPCR |= cmp2fcc (sim_fpu_cmp (&m, &n));
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP add, setting FP exception bits when
+ appropriate. */
+void
+fpu_add (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_NINF)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_PINF))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_add (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP sub, setting FP exception bits when
+ appropriate. */
+void
+fpu_sub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_PINF)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_NINF))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_sub (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP mul, setting FP exception bits when
+ appropriate. */
+void
+fpu_mul (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m) && sim_fpu_is_zero (&n))
+ || (sim_fpu_is_zero (&m) && sim_fpu_is_infinity (&n)))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP div, setting FP exception bits when
+ appropriate. */
+void
+fpu_div (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n))
+ || (sim_fpu_is_zero (&m) && sim_fpu_is_zero (&n)))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else if (sim_fpu_is_number (&m) && sim_fpu_is_zero (&n)
+ && (FPCR & EE_Z))
+ FPCR |= EC_Z;
+ else
+ {
+ sim_fpu_status stat = sim_fpu_div (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP madd, setting FP exception bits when
+ appropriate. */
+void
+fpu_fmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_add (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP msub, setting FP exception bits when
+ appropriate. */
+void
+fpu_fmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_sub (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmadd, setting FP exception bits when
+ appropriate. */
+void
+fpu_fnmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, mm, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_neg (&mm, &m);
+ stat |= sim_fpu_add (&r, &mm, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmsub, setting FP exception bits when
+ appropriate. */
+void
+fpu_fnmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, mm, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_neg (&mm, &m);
+ stat |= sim_fpu_sub (&r, &mm, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
Index: sim/mn10300/mn10300.igen
===================================================================
RCS file: /cvs/src/src/sim/mn10300/mn10300.igen,v
retrieving revision 1.4
diff -u -p -r1.4 mn10300.igen
--- sim/mn10300/mn10300.igen 7 May 2001 04:52:00 -0000 1.4
+++ sim/mn10300/mn10300.igen 26 Jun 2004 22:16:01 -0000
@@ -4,6 +4,7 @@
:option:::hi-bit-nr:7
:model:::mn10300:mn10300:
:model:::am33:am33:
+:model:::am33_2:am33_2:
// What do we do with an illegal instruction?
:internal::::illegal:
@@ -17,6 +18,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_8000 (); */
signed32 immed = EXTEND8 (IMM8);
@@ -29,6 +31,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_80 (); */
@@ -41,6 +44,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F1E0 (); */
PC = cia;
@@ -53,6 +57,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F1D0 (); */
PC = cia;
@@ -65,6 +70,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_9000 (); */
@@ -77,6 +83,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_90 (); */
@@ -89,6 +96,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_3C (); */
PC = cia;
@@ -101,6 +109,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F0 (); */
PC = cia;
@@ -113,6 +122,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2E4 (); */
PC = cia;
@@ -125,6 +135,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F3 (); */
PC = cia;
@@ -137,6 +148,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2E0 (); */
PC = cia;
@@ -149,6 +161,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F2 (); */
PC = cia;
@@ -161,6 +174,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_70 (); */
PC = cia;
@@ -173,6 +187,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F80000 (); */
PC = cia;
@@ -186,6 +201,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA000000 (); */
PC = cia;
@@ -199,6 +215,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC000000 (); */
PC = cia;
@@ -213,6 +230,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_5800 (); */
PC = cia;
@@ -225,6 +243,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAB40000 (); */
PC = cia;
@@ -238,6 +257,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCB40000 (); */
PC = cia;
@@ -251,6 +271,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F300 (); */
PC = cia;
@@ -264,6 +285,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_300000 (); */
PC = cia;
@@ -275,6 +297,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCA40000 (); */
PC = cia;
@@ -287,6 +310,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F000 (); */
PC = cia;
@@ -299,6 +323,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F82000 (); */
PC = cia;
@@ -312,6 +337,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA200000 (); */
PC = cia;
@@ -326,6 +352,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC200000 (); */
PC = cia;
@@ -340,6 +367,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_5C00 (); */
PC = cia;
@@ -353,6 +381,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAB00000 (); */
PC = cia;
@@ -366,6 +395,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCB00000 (); */
PC = cia;
@@ -380,6 +410,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F380 (); */
PC = cia;
@@ -394,6 +425,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAA00000 (); */
PC = cia;
@@ -406,6 +438,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCA00000 (); */
PC = cia;
@@ -419,6 +452,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F8F000 (); */
PC = cia;
@@ -432,6 +466,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_60 (); */
PC = cia;
@@ -444,6 +479,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F81000 (); */
PC = cia;
@@ -457,6 +493,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA100000 (); */
PC = cia;
@@ -470,6 +507,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC100000 (); */
PC = cia;
@@ -484,6 +522,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_4200 (); */
PC = cia;
@@ -496,6 +535,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA910000 (); */
PC = cia;
@@ -509,6 +549,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC910000 (); */
PC = cia;
@@ -522,6 +563,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F340 (); */
PC = cia;
@@ -535,6 +577,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_10000 (); */
PC = cia;
@@ -547,6 +590,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC810000 (); */
PC = cia;
@@ -560,6 +604,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F010 (); */
PC = cia;
@@ -572,6 +617,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F83000 (); */
PC = cia;
@@ -585,6 +631,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA300000 (); */
PC = cia;
@@ -598,6 +645,7 @@
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC300000 (); */
PC = cia;
@@ -613,6 +661,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_4300 (); */
@@ -627,6 +676,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA900000 (); */
@@ -642,6 +692,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC900000 (); */
@@ -657,6 +708,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F3C0 (); */
@@ -672,6 +724,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA800000 (); */
@@ -687,6 +740,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC800000 (); */
@@ -702,6 +756,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8F400 (); */
@@ -717,6 +772,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_2C0000 (); */
@@ -734,6 +790,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCCC0000 (); */
@@ -751,6 +808,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_240000 (); */
@@ -768,6 +826,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCDC0000 (); */
@@ -782,6 +841,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F040 (); */
@@ -797,6 +857,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F84000 (); */
@@ -812,6 +873,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA400000 (); */
@@ -828,6 +890,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC400000 (); */
@@ -844,6 +907,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8B800 (); */
@@ -859,6 +923,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAB80000 (); */
@@ -875,6 +940,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCB80000 (); */
@@ -891,6 +957,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F400 (); */
@@ -907,6 +974,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_340000 (); */
@@ -921,6 +989,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCA80000 (); */
@@ -936,6 +1005,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F050 (); */
@@ -950,6 +1020,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F85000 (); */
@@ -965,6 +1036,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA500000 (); */
@@ -980,6 +1052,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC500000 (); */
@@ -996,6 +1069,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F89200 (); */
@@ -1010,6 +1084,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA920000 (); */
@@ -1025,6 +1100,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC920000 (); */
@@ -1040,6 +1116,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F440 (); */
@@ -1055,6 +1132,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_20000 (); */
@@ -1070,6 +1148,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC820000 (); */
@@ -1085,6 +1164,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F060 (); */
@@ -1100,6 +1180,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F86000 (); */
@@ -1115,6 +1196,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA600000 (); */
@@ -1131,6 +1213,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC600000 (); */
@@ -1147,6 +1230,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8BC00 (); */
@@ -1162,6 +1246,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FABC0000 (); */
@@ -1177,6 +1262,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCBC0000 (); */
@@ -1192,6 +1278,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F480 (); */
@@ -1207,6 +1294,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_380000 (); */
@@ -1221,6 +1309,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCAC0000 (); */
@@ -1236,6 +1325,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F070 (); */
@@ -1251,6 +1341,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F87000 (); */
@@ -1266,6 +1357,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA700000 (); */
@@ -1281,6 +1373,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC700000 (); */
@@ -1297,6 +1390,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F89300 (); */
@@ -1312,6 +1406,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FA930000 (); */
@@ -1327,6 +1422,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC930000 (); */
@@ -1342,6 +1438,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F4C0 (); */
@@ -1357,6 +1454,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_30000 (); */
@@ -1371,6 +1469,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FC830000 (); */
@@ -1386,6 +1485,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F2D0 (); */
@@ -1403,6 +1503,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_10 (); */
@@ -1417,6 +1518,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_14 (); */
@@ -1431,6 +1533,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_18 (); */
@@ -1445,6 +1548,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_1C (); */
@@ -1459,6 +1563,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_0 (); */
@@ -1476,6 +1581,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_E0 (); */
@@ -1489,6 +1595,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F160 (); */
@@ -1503,6 +1610,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F150 (); */
@@ -1517,6 +1625,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F170 (); */
@@ -1531,6 +1640,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_2800 (); */
@@ -1545,6 +1655,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAC00000 (); */
@@ -1559,6 +1670,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCC00000 (); */
@@ -1573,6 +1685,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_2000 (); */
@@ -1587,6 +1700,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAD00000 (); */
@@ -1601,6 +1715,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCD00000 (); */
@@ -1615,6 +1730,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8FE00 (); */
@@ -1633,6 +1749,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAFE0000 (); */
@@ -1651,6 +1768,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCFE0000 (); */
@@ -1669,6 +1787,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F140 (); */
@@ -1699,6 +1818,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F100 (); */
@@ -1712,6 +1832,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F120 (); */
@@ -1726,6 +1847,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F110 (); */
@@ -1740,6 +1862,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F130 (); */
@@ -1754,6 +1877,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCC40000 (); */
@@ -1768,6 +1892,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCD40000 (); */
@@ -1782,6 +1907,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F180 (); */
@@ -1812,6 +1938,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F240 (); */
@@ -1836,6 +1963,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F250 (); */
@@ -1860,6 +1988,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F260 (); */
@@ -1897,6 +2026,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F270 (); */
@@ -1933,6 +2063,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_40 (); */
@@ -1950,6 +2081,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_41 (); */
@@ -1964,6 +2096,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_50 (); */
@@ -1978,6 +2111,7 @@
*mn10300
*am33
+*am33_2
{
PC = cia;
@@ -1992,6 +2126,7 @@
*mn10300
*am33
+*am33_2
{
PC = cia;
@@ -2006,6 +2141,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F1A0 (); */
@@ -2020,6 +2156,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F190 (); */
@@ -2034,6 +2171,7 @@
*mn10300
*am33
+*am33_2
{
PC = cia;
@@ -2049,6 +2187,7 @@
*mn10300
*am33
+*am33_2
{
PC = cia;
@@ -2063,6 +2202,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAC80000 (); */
@@ -2078,6 +2218,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCC80000 (); */
@@ -2093,6 +2234,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAD80000 (); */
@@ -2108,6 +2250,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCD80000 (); */
@@ -2123,6 +2266,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F200 (); */
@@ -2143,6 +2287,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8E000 (); */
@@ -2163,6 +2308,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAE00000 (); */
@@ -2183,6 +2329,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCE00000 (); */
@@ -2204,6 +2351,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAFC0000 (); */
@@ -2219,6 +2367,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F210 (); */
@@ -2233,6 +2382,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8E400 (); */
@@ -2247,6 +2397,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAE40000 (); */
@@ -2261,6 +2412,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCE40000 (); */
@@ -2275,6 +2427,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAFD0000 (); */
@@ -2289,6 +2442,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F220 (); */
@@ -2303,6 +2457,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAE80000 (); */
@@ -2317,6 +2472,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCE80000 (); */
@@ -2331,6 +2487,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F230 (); */
@@ -2351,6 +2508,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8EC00 (); */
@@ -2365,6 +2523,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAEC0000 (); */
@@ -2379,6 +2538,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCEC0000 (); */
@@ -2394,6 +2554,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FE020000 (); */
@@ -2410,6 +2571,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAF80000 (); */
@@ -2425,6 +2587,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F080 (); */
@@ -2448,6 +2611,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FE000000 (); */
@@ -2471,6 +2635,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAF00000 (); */
@@ -2493,6 +2658,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F090 (); */
@@ -2516,6 +2682,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FE010000 (); */
@@ -2539,6 +2706,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAF40000 (); */
@@ -2561,6 +2729,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F2B0 (); */
@@ -2585,6 +2754,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8C800 (); */
@@ -2609,6 +2779,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F2A0 (); */
@@ -2631,6 +2802,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8C400 (); */
@@ -2652,6 +2824,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F290 (); */
@@ -2673,6 +2846,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8C000 (); */
@@ -2693,6 +2867,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_54 (); */
@@ -2713,6 +2888,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F284 (); */
@@ -2739,6 +2915,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F280 (); */
@@ -2765,6 +2942,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C800 (); */
@@ -2783,6 +2961,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C900 (); */
@@ -2801,6 +2980,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C100 (); */
@@ -2820,6 +3000,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C200 (); */
@@ -2838,6 +3019,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C300 (); */
@@ -2857,6 +3039,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C000 (); */
@@ -2875,6 +3058,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C500 (); */
@@ -2893,6 +3077,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C600 (); */
@@ -2911,6 +3096,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C700 (); */
@@ -2929,6 +3115,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_C400 (); */
@@ -2947,6 +3134,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8E800 (); */
@@ -2965,6 +3153,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8E900 (); */
@@ -2983,6 +3172,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8EA00 (); */
@@ -3001,6 +3191,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F8EB00 (); */
@@ -3019,6 +3210,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CA00 (); */
@@ -3034,6 +3226,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D8 (); */
@@ -3052,6 +3245,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D9 (); */
@@ -3070,6 +3264,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D1 (); */
@@ -3089,6 +3284,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D2 (); */
@@ -3107,6 +3303,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D3 (); */
@@ -3126,6 +3323,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D0 (); */
@@ -3144,6 +3342,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D5 (); */
@@ -3162,6 +3361,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D6 (); */
@@ -3180,6 +3380,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D7 (); */
@@ -3198,6 +3399,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_D4 (); */
@@ -3216,6 +3418,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DA (); */
@@ -3231,6 +3434,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DB (); */
@@ -3246,6 +3450,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0F4 (); */
@@ -3260,6 +3465,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CC0000 (); */
@@ -3274,6 +3480,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DC000000 (); */
@@ -3288,6 +3495,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0F0 (); */
@@ -3309,6 +3517,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FAFF0000 (); */
@@ -3330,6 +3539,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FCFF0000 (); */
@@ -3351,6 +3561,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0FC (); */
@@ -3368,6 +3579,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0FD (); */
@@ -3387,6 +3599,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0FE (); */
@@ -3406,6 +3619,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0FF (); */
@@ -3420,6 +3634,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CB (); */
@@ -3444,6 +3659,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F6F0 (); */
@@ -3465,6 +3681,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F600 (); */
@@ -3489,6 +3706,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F90000 (); */
@@ -3513,6 +3731,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FB000000 (); */
@@ -3537,6 +3756,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FD000000 (); */
@@ -3561,6 +3781,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F610 (); */
@@ -3585,6 +3806,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F91400 (); */
@@ -3609,6 +3831,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FB140000 (); */
@@ -3633,6 +3856,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FD140000 (); */
@@ -3657,6 +3881,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F640 (); */
@@ -3676,6 +3901,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F650 (); */
@@ -3695,6 +3921,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F670 (); */
@@ -3715,6 +3942,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_F0C0 (); */
@@ -3729,6 +3957,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_FF (); */
@@ -3742,6 +3971,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CE00 (); */
@@ -3795,6 +4025,7 @@
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x1)
@@ -3839,6 +4070,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CF00 (); */
@@ -3849,6 +4081,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
@@ -3936,6 +4169,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_CD000000 (); */
@@ -3950,6 +4184,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
@@ -4043,6 +4278,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DD000000 (); */
@@ -4058,6 +4294,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
@@ -4150,6 +4387,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DF0000 (); */
@@ -4164,6 +4402,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
@@ -4253,6 +4492,7 @@
*mn10300
*am33
+*am33_2
{
/* OP_DE0000 (); */
@@ -4268,6 +4508,7 @@
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
Index: sim/mn10300/mn10300_sim.h
===================================================================
RCS file: /cvs/src/src/sim/mn10300/mn10300_sim.h,v
retrieving revision 1.5
diff -u -p -r1.5 mn10300_sim.h
--- sim/mn10300/mn10300_sim.h 26 Jun 2004 21:53:47 -0000 1.5
+++ sim/mn10300/mn10300_sim.h 26 Jun 2004 22:16:01 -0000
@@ -6,6 +6,7 @@
#include <limits.h>
#include "gdb/remote-sim.h"
#include "bfd.h"
+#include "sim-fpu.h"
#ifndef INLINE
#ifdef __GNUC__
@@ -53,6 +54,10 @@ typedef signed long int32;
# endif
#endif
+typedef struct
+{
+ uint32 low, high;
+} dword;
typedef uint32 reg_t;
struct simops
@@ -73,6 +78,11 @@ struct _state
reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
lir, lar, mdrq, plus some room for processor
specific regs. */
+ union
+ {
+ reg_t fs[32]; /* FS0-31 */
+ dword fd[16]; /* FD0,2,...,30 */
+ } fpregs;
uint8 *mem; /* main memory */
int exception;
int exited;
@@ -123,6 +133,52 @@ extern struct simops Simops[];
#define REG_MCRL 27
#define REG_MCVF 28
+#define REG_FPCR 29
+
+#define FPCR (State.regs[REG_FPCR])
+
+#define FCC_MASK LSMASK (21, 18)
+#define RM_MASK LSMASK (17, 16) /* Must always be zero. */
+#define EC_MASK LSMASK (14, 10)
+#define EE_MASK LSMASK ( 9, 5)
+#define EF_MASK LSMASK ( 4, 0)
+#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
+
+#define FCC_L LSBIT (21)
+#define FCC_G LSBIT (20)
+#define FCC_E LSBIT (19)
+#define FCC_U LSBIT (18)
+
+#define EC_V LSBIT (14)
+#define EC_Z LSBIT (13)
+#define EC_O LSBIT (12)
+#define EC_U LSBIT (11)
+#define EC_I LSBIT (10)
+
+#define EE_V LSBIT (9)
+#define EE_Z LSBIT (8)
+#define EE_O LSBIT (7)
+#define EE_U LSBIT (6)
+#define EE_I LSBIT (5)
+
+#define EF_V LSBIT (4)
+#define EF_Z LSBIT (3)
+#define EF_O LSBIT (2)
+#define EF_U LSBIT (1)
+#define EF_I LSBIT (0)
+
+#define PSW_FE LSBIT(20)
+#define FPU_DISABLED !(PSW & PSW_FE)
+
+#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
+#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
+#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
+
+#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
+#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
+#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
+#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
+
#ifdef _WIN32
#define SIGTRAP 5
#define SIGQUIT 3
@@ -145,6 +201,20 @@ sim_core_read_unaligned_2 (STATE_CPU (si
#define load_word(ADDR) \
sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+#define load_dword(ADDR) \
+u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
+ PC, read_map, (ADDR)))
+
+static INLINE dword
+u642dw (unsigned64 dw)
+{
+ dword r;
+
+ r.low = (unsigned32)dw;
+ r.high = (unsigned32)(dw >> 32);
+ return r;
+}
+
#define store_byte(ADDR, DATA) \
sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), (DATA))
@@ -158,6 +228,15 @@ sim_core_write_unaligned_2 (STATE_CPU (s
#define store_word(ADDR, DATA) \
sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), (DATA))
+#define store_dword(ADDR, DATA) \
+sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
+ PC, write_map, (ADDR), dw2u64 (DATA))
+
+static INLINE unsigned64
+dw2u64 (dword data)
+{
+ return data.low | (((unsigned64)data.high) << 32);
+}
/* Function declarations. */
@@ -192,3 +271,29 @@ void program_interrupt (SIM_DESC sd, sim
void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+
+void fpu_disabled_exception (SIM_DESC, sim_cpu *, address_word);
+void fpu_unimp_exception (SIM_DESC, sim_cpu *, address_word);
+void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
+
+extern const struct fp_prec_t
+{
+ void (* reg2val) (const void *, sim_fpu *);
+ int (* round) (sim_fpu *);
+ void (* val2reg) (const sim_fpu *, void *);
+} fp_single_prec, fp_double_prec;
+
+#define FP_SINGLE (&fp_single_prec)
+#define FP_DOUBLE (&fp_double_prec)
+
+void fpu_rsqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_sqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_cmp (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
+void fpu_add (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_sub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_mul (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_div (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
[-- Attachment #3: Type: text/plain, Size: 188 bytes --]
--
Alexandre Oliva http://www.ic.unicamp.br/~oliva/
Red Hat Compiler Engineer aoliva@{redhat.com, gcc.gnu.org}
Free Software Evangelist oliva@{lsd.ic.unicamp.br, gnu.org}
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2004-06-26 22:18 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2003-07-10 3:10 AM33/2.0 support for mn10300-elf Alexandre Oliva
2003-07-10 3:31 ` Alexandre Oliva
2003-07-10 4:59 ` Alexandre Oliva
2003-07-16 16:05 ` [Bug-dejagnu] " Rob Savoye
2003-07-22 20:02 ` Alexandre Oliva
2003-07-10 4:57 ` Alexandre Oliva
2003-08-02 14:26 ` Andrew Cagney
2004-06-21 13:59 ` Alexandre Oliva
2004-06-25 21:41 ` Andrew Cagney
2004-06-26 22:00 ` Alexandre Oliva
2004-06-26 22:00 ` Alexandre Oliva
2004-06-26 22:18 ` Alexandre Oliva
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