Re: [PATCH 4/5] RISC-V: Add native linux support.

[Palmer Dabbelt <palmer@sifive.com>]

On Thu, 25 Oct 2018 12:19:29 PDT (-0700), jhb@FreeBSD.org wrote:
> On 10/25/18 11:17 AM, Jim Wilson wrote:
>> On Thu, Oct 25, 2018 at 10:55 AM John Baldwin <jhb@freebsd.org> wrote:
>>> Now that the MISA defaults to 0 if not present, would it better to just remove
>>> this and not set it to 0 explicitly?  The FreeBSD native target for RISC-V
>>> doesn't set MISA to anything at all.
>>
>> There is still the issue of FP register size, which comes from MISA,
>> unless perhaps we can get it from auxvec/hw-cap info.  I was going to
>> look into that latter, and if the auxvec/hw-cap stuff works, then
>> remove the remaining MISA support in the riscv-linux-nat.c file.
>
> Ok.  I do agree that auxvec is probably the right way to handle this, as what
> really matters is what format the kernel exports.  You can find existing uses
> of auxvec for this on 32-bit arm support where AT_HWCAP flags are tested for
> both Linux and FreeBSD in the respective tdep.c files to determine which
> floating point registers are available.  You are free to use the same code
> in a nat.c file as well of course.

We have a very simple scheme here: there's a bit for every ISA extension that 
is set in HWCAP by the kernel when that extension is present as far as 
userspace is concerned.  The code is probably easier to understand

    https://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git/tree/arch/riscv/kernel/cpufeature.c#n33

We should probably but this in an ABI document somewhere... :)