From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 58723 invoked by alias); 27 Oct 2018 06:07:21 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 58713 invoked by uid 89); 27 Oct 2018 06:07:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=palmer, auxvec, tdepc, HCC:D*de X-HELO: mail-pf1-f196.google.com Received: from mail-pf1-f196.google.com (HELO mail-pf1-f196.google.com) (209.85.210.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 27 Oct 2018 06:07:18 +0000 Received: by mail-pf1-f196.google.com with SMTP id c25-v6so1540903pfe.6 for ; Fri, 26 Oct 2018 23:07:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=EjlweOb9aKosYk/m01rHZRGnD12Is2/Qt/it03sPJXI=; b=niPet4vtZ8I77FZ1NkoohTOvJmy5C+NO4SSrVlvdYwKGvzmPh8R5m6Sffo4trNN4XA 3lId1QtbKduz7zO5hEeGk3iLkjqI82ibRYSBeBetoAp3qAifV/NwF+81GnzzH6LU9ScQ DwxkI31Dd0C9B89NOkQmxFi+MIBWq4RclUon9fwp9OsmZxuE8tUFSo9F9AwyLUM+9F1e WhSHKTWMK2MmFhQiVCS65o4W2P/2vvrHkqYB5sB7NqPwpuYG3SHygKM9uGi+ZOU68syw UfhgFPBgSrCZHtBNxZBnYdVUbiWgwQekeDv2fxmA9Vq334IZwwO7Dsh3mmBasefNkupY P7Cw== Return-Path: Received: from localhost (c-67-161-15-180.hsd1.ca.comcast.net. [67.161.15.180]) by smtp.gmail.com with ESMTPSA id j19-v6sm14148181pfi.137.2018.10.26.23.07.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Oct 2018 23:07:16 -0700 (PDT) Date: Sat, 27 Oct 2018 06:07:00 -0000 X-Google-Original-Date: Fri, 26 Oct 2018 22:55:39 PDT (-0700) Subject: Re: [PATCH 4/5] RISC-V: Add native linux support. In-Reply-To: <0cc883c4-e304-c3a9-adba-55ea434ec238@FreeBSD.org> CC: Jim Wilson , andrew.burgess@embecosm.com, schwab@suse.de, gdb-patches@sourceware.org From: Palmer Dabbelt To: jhb@FreeBSD.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2018-10/txt/msg00643.txt.bz2 On Thu, 25 Oct 2018 12:19:29 PDT (-0700), jhb@FreeBSD.org wrote: > On 10/25/18 11:17 AM, Jim Wilson wrote: >> On Thu, Oct 25, 2018 at 10:55 AM John Baldwin wrote: >>> Now that the MISA defaults to 0 if not present, would it better to just remove >>> this and not set it to 0 explicitly? The FreeBSD native target for RISC-V >>> doesn't set MISA to anything at all. >> >> There is still the issue of FP register size, which comes from MISA, >> unless perhaps we can get it from auxvec/hw-cap info. I was going to >> look into that latter, and if the auxvec/hw-cap stuff works, then >> remove the remaining MISA support in the riscv-linux-nat.c file. > > Ok. I do agree that auxvec is probably the right way to handle this, as what > really matters is what format the kernel exports. You can find existing uses > of auxvec for this on 32-bit arm support where AT_HWCAP flags are tested for > both Linux and FreeBSD in the respective tdep.c files to determine which > floating point registers are available. You are free to use the same code > in a nat.c file as well of course. We have a very simple scheme here: there's a bit for every ISA extension that is set in HWCAP by the kernel when that extension is present as far as userspace is concerned. The code is probably easier to understand https://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git/tree/arch/riscv/kernel/cpufeature.c#n33 We should probably but this in an ABI document somewhere... :)