Re: [PATCH] gdb/riscv: add support for vector registers in target descriptions

[Palmer Dabbelt <palmer@dabbelt.com>]

On Wed, 05 May 2021 14:05:52 PDT (-0700), Jim Wilson wrote:
> On Wed, May 5, 2021 at 2:46 AM Andrew Burgess <andrew.burgess@embecosm.com>
> wrote:
>
>> This commit adds support to RISC-V GDB for vector registers in the
>> incoming target description.
>>
>
> It looks reasonable to me.  Though I did notice that you have two comments
> which mention f-register instead of v-register.
>
> The vector spec isn't official yet, and hasn't been frozen yet, so there is
> a chance that some things will still change, but very unlikely that this
> patch would be affected.  I can't imagine them changing the number of user
> registers at this point.

IMO that's fine: we can maintain a stable ABI for this, even in the 
unlikely event that the number of vector registers changes we'll just 
end up with some unused register indices.  We're already relying on an 
external mechanism to determine the semantics of the CSRs, as we've 
allocated register numbers for all of those despite most not being in 
any spec.