From: Jim Wilson <jimw@sifive.com>
To: Andrew Burgess <andrew.burgess@embecosm.com>
Cc: gdb-patches@sourceware.org
Subject: Re: [PATCH] gdb/riscv: add support for vector registers in target descriptions
Date: Wed, 5 May 2021 14:05:52 -0700 [thread overview]
Message-ID: <CAFyWVab8aJggRk7UX63s-9BMD19F==LMRQJtQMoA5knY49B-fg@mail.gmail.com> (raw)
In-Reply-To: <20210505094639.1551740-1-andrew.burgess@embecosm.com>
On Wed, May 5, 2021 at 2:46 AM Andrew Burgess <andrew.burgess@embecosm.com>
wrote:
> This commit adds support to RISC-V GDB for vector registers in the
> incoming target description.
>
It looks reasonable to me. Though I did notice that you have two comments
which mention f-register instead of v-register.
The vector spec isn't official yet, and hasn't been frozen yet, so there is
a chance that some things will still change, but very unlikely that this
patch would be affected. I can't imagine them changing the number of user
registers at this point.
Jim
next prev parent reply other threads:[~2021-05-05 21:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 9:46 Andrew Burgess
2021-05-05 21:05 ` Jim Wilson [this message]
2021-05-06 7:26 ` Palmer Dabbelt
2021-06-21 11:04 ` [PATCHv2] " Andrew Burgess
2021-06-21 11:41 ` Eli Zaretskii via Gdb-patches
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