From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id KsQIEjCak2BfGwAAWB0awg (envelope-from ) for ; Thu, 06 May 2021 03:26:40 -0400 Received: by simark.ca (Postfix, from userid 112) id E4D5C1F11C; Thu, 6 May 2021 03:26:39 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-0.5 required=5.0 tests=DKIM_SIGNED, MAILING_LIST_MULTI,RDNS_DYNAMIC,T_DKIM_INVALID,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id ACBE91E01F for ; Thu, 6 May 2021 03:26:38 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0A5613857801; Thu, 6 May 2021 07:26:38 +0000 (GMT) Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by sourceware.org (Postfix) with ESMTPS id B84213857801 for ; Thu, 6 May 2021 07:26:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org B84213857801 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=palmer@dabbelt.com Received: by mail-pg1-x532.google.com with SMTP id m190so4155626pga.2 for ; Thu, 06 May 2021 00:26:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20150623.gappssmtp.com; s=20150623; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=EOzMLl3Z2r9HUuZ1lFxvgs4eYdW9gJUt2IpBHeNLxUM=; b=F2gVOD9utwoys7Ha/4VBqyyIwGpXlH/cGvQvftpK52uvbSapWTfYKWa7lr7aI+oPj/ pznrkh1rc2crKVvbdssl2peLfJMDlhO0y0FtcZ0UZNh+mP944dOajw+siMiGVx/deVde 1JQyuIvR9B+gNPay+DtGnDFamSwijd75fHb1Wgk/dYCjTVEpWAMJOk6d7NZgXMG2iM25 9/FPITtr5ng5CI8rQ2l7d9fC54MlIAL5pU4jSMZrRggJwTGvcqoQJ9/6FjzPPRJFaVw1 H5cDxgIHxX2ITt3dKz3sBJUk4nb1SbkJqpUtS0ftS9uCX7m3NgNZOgLVqZCB6UW28EKU wOcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=EOzMLl3Z2r9HUuZ1lFxvgs4eYdW9gJUt2IpBHeNLxUM=; b=BldZ6OcqkTqqx5qDHz2o3PjV4fTeUYHewR0BlQ48zotb3YrS/6q0BksFEuKvnYTkDH /EjGXqtP745EsSZmZxsf8p1QDL4jHeYicgJfJM5RaFdDkcQDdONdOxG15dQrcca3/lK7 5z5fcFdKgwD8szt+I8tJ/Qq33ktQVCeSWgnexqlF+31fz+044aF09Alz36reuMiluWJa LKahqkjHQAzQ0mAPkq/aCrqjGjkGv/rlpA2TEa4QUG5k4P5Janp2hYu0KsrN8DGSATzM AOAKdn+A2/DwK3xZlcyvfhoqWY02meiSt8QlRVXaVY9JmJkzb3/DMt+vyTWdwlR2DSe0 bXEw== X-Gm-Message-State: AOAM533Q3ZoZCyO2udC0QfK2G5vCD7Q68cXSrnAC/zTPEOKht9V4gtgA m9+J4j58QC0Ne2FwELpa3kMfiA== X-Google-Smtp-Source: ABdhPJzHNEVZOQYTZFDMN+PkikjbHxIoAYKoaGT8UO1axdeUT+1C0Yeew3PxtC8m7dxlOAq64uR3vA== X-Received: by 2002:a63:184a:: with SMTP id 10mr2850755pgy.426.1620285994811; Thu, 06 May 2021 00:26:34 -0700 (PDT) Received: from localhost (76-210-143-223.lightspeed.sntcca.sbcglobal.net. [76.210.143.223]) by smtp.gmail.com with ESMTPSA id j12sm1230986pff.49.2021.05.06.00.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 00:26:34 -0700 (PDT) Date: Thu, 06 May 2021 00:26:34 -0700 (PDT) X-Google-Original-Date: Thu, 06 May 2021 00:26:32 PDT (-0700) Subject: Re: [PATCH] gdb/riscv: add support for vector registers in target descriptions In-Reply-To: From: Palmer Dabbelt To: Jim Wilson Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gdb-patches@sourceware.org Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" On Wed, 05 May 2021 14:05:52 PDT (-0700), Jim Wilson wrote: > On Wed, May 5, 2021 at 2:46 AM Andrew Burgess > wrote: > >> This commit adds support to RISC-V GDB for vector registers in the >> incoming target description. >> > > It looks reasonable to me. Though I did notice that you have two comments > which mention f-register instead of v-register. > > The vector spec isn't official yet, and hasn't been frozen yet, so there is > a chance that some things will still change, but very unlikely that this > patch would be affected. I can't imagine them changing the number of user > registers at this point. IMO that's fine: we can maintain a stable ABI for this, even in the unlikely event that the number of vector registers changes we'll just end up with some unused register indices. We're already relying on an external mechanism to determine the semantics of the CSRs, as we've allocated register numbers for all of those despite most not being in any spec.