Re: [RFA][3/5] New port: Cell BE SPU (the port itself)

[Jim Blandy <jimb@codesourcery.com>]

"Mark Kettenis" <mark.kettenis@xs4all.nl> writes:
>>  I have a set of patches that does appear to work so far; it is based
>>  primarily on switching current_gdbarch on thread switch.  However,
>>  there's still some work to be done before this is in a shape suitable
>>  for mainline inclusion.
>
> Andrew Cagney has talked a fair bit about this sort of things in the past.
> His idea was that each frame would have a gdbarch.  But a gdbarch per
> thread probably makes more sense.

Not to distract from discussion of Uli's patch, but:

I've worked on a processor that would switch between a normal ISA and
a special VLIW ISA on function calls.  The bottom bit of the return
address said which mode to return to on the way out.  And ARM allows
calls between Thumb and ARM code.

Making the architecture per-frame, though, raises a bunch of odd
questions.  If a register is callee-saves, finding its value in some
frame F entails asking F's callee G for the value.  But if G is a
different gdbarch from F, then what register numbering does F use to
make the request?

And that's just off the top of my head.  I'll bet there's lots more.