From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12383 invoked by alias); 13 Nov 2006 19:50:59 -0000 Received: (qmail 12373 invoked by uid 22791); 13 Nov 2006 19:50:58 -0000 X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (65.74.133.4) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 13 Nov 2006 19:50:51 +0000 Received: (qmail 17076 invoked from network); 13 Nov 2006 19:50:49 -0000 Received: from unknown (HELO localhost) (jimb@127.0.0.2) by mail.codesourcery.com with ESMTPA; 13 Nov 2006 19:50:49 -0000 To: "Mark Kettenis" Cc: "Ulrich Weigand" , "Daniel Jacobowitz" , gdb-patches@sourceware.org Subject: Re: [RFA][3/5] New port: Cell BE SPU (the port itself) References: <200611131227.kADCRe28032402@d12av02.megacenter.de.ibm.com> <22583.192.87.1.22.1163421727.squirrel@webmail.xs4all.nl> From: Jim Blandy Date: Mon, 13 Nov 2006 19:50:00 -0000 In-Reply-To: <22583.192.87.1.22.1163421727.squirrel@webmail.xs4all.nl> (Mark Kettenis's message of "Mon, 13 Nov 2006 13:42:07 +0100 (CET)") Message-ID: User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.0.50 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2006-11/txt/msg00104.txt.bz2 "Mark Kettenis" writes: >> I have a set of patches that does appear to work so far; it is based >> primarily on switching current_gdbarch on thread switch. However, >> there's still some work to be done before this is in a shape suitable >> for mainline inclusion. > > Andrew Cagney has talked a fair bit about this sort of things in the past. > His idea was that each frame would have a gdbarch. But a gdbarch per > thread probably makes more sense. Not to distract from discussion of Uli's patch, but: I've worked on a processor that would switch between a normal ISA and a special VLIW ISA on function calls. The bottom bit of the return address said which mode to return to on the way out. And ARM allows calls between Thumb and ARM code. Making the architecture per-frame, though, raises a bunch of odd questions. If a register is callee-saves, finding its value in some frame F entails asking F's callee G for the value. But if G is a different gdbarch from F, then what register numbering does F use to make the request? And that's just off the top of my head. I'll bet there's lots more.