Re: RFC: partially available registers

[Tom Tromey <tromey@redhat.com>]

>>>>> "Pedro" == Pedro Alves <pedro@codesourcery.com> writes:

CC'ing H.J.

Pedro> But before the <unavailable> stuff, it meant "supply the register
Pedro> as 0".  I seem to remember discussing this AVX stuff with H.J.,
Pedro> and coming to the conclusion that what want is really 0, but
Pedro> maybe not.

I am far from being an expert in this area, but from the Intel
Architecture manual, section 13.5.1:

    Saving the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 state using FXSAVE
    requires processor overhead. If the new task does not access x87 FPU,
    MMX, XMM, and MXCSR registers, avoid overhead by not automatically
    saving the state on a task switch.

    The TS flag in control register CR0 is provided to allow the operating
    system to delay saving the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 state
    until an instruction that actually accesses this state is encountered in
    a new task.

So I think what is going on here is that the upper bits of these
registers are truly unavailable, because the inferior has never executed
an instruction referencing them.

Pedro> Whatever the answer, we need to fix one of native
Pedro> gdb or gdbserver for consistency.

If you agree with what I have checked in, I will update gdbserver.
Otherwise, let me know what you think would be correct and I will
implement that, instead, for both.

thanks,
Tom