From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3370 invoked by alias); 22 Jul 2011 19:31:30 -0000 Received: (qmail 3353 invoked by uid 22791); 22 Jul 2011 19:31:30 -0000 X-SWARE-Spam-Status: No, hits=-7.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 22 Jul 2011 19:31:06 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p6MJUuc3017721 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 22 Jul 2011 15:30:56 -0400 Received: from ns3.rdu.redhat.com (ns3.rdu.redhat.com [10.11.255.199]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p6MJUtVF013431; Fri, 22 Jul 2011 15:30:56 -0400 Received: from barimba (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by ns3.rdu.redhat.com (8.13.8/8.13.8) with ESMTP id p6MJUrLK015563; Fri, 22 Jul 2011 15:30:54 -0400 From: Tom Tromey To: Pedro Alves Cc: gdb-patches@sourceware.org, Daniel Jacobowitz , hjl@gnu.org Subject: Re: RFC: partially available registers References: <201107221940.32070.pedro@codesourcery.com> <201107222010.23822.pedro@codesourcery.com> Date: Fri, 22 Jul 2011 22:20:00 -0000 In-Reply-To: <201107222010.23822.pedro@codesourcery.com> (Pedro Alves's message of "Fri, 22 Jul 2011 20:10:23 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.0.50 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2011-07/txt/msg00646.txt.bz2 >>>>> "Pedro" == Pedro Alves writes: CC'ing H.J. Pedro> But before the stuff, it meant "supply the register Pedro> as 0". I seem to remember discussing this AVX stuff with H.J., Pedro> and coming to the conclusion that what want is really 0, but Pedro> maybe not. I am far from being an expert in this area, but from the Intel Architecture manual, section 13.5.1: Saving the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 state using FXSAVE requires processor overhead. If the new task does not access x87 FPU, MMX, XMM, and MXCSR registers, avoid overhead by not automatically saving the state on a task switch. The TS flag in control register CR0 is provided to allow the operating system to delay saving the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 state until an instruction that actually accesses this state is encountered in a new task. So I think what is going on here is that the upper bits of these registers are truly unavailable, because the inferior has never executed an instruction referencing them. Pedro> Whatever the answer, we need to fix one of native Pedro> gdb or gdbserver for consistency. If you agree with what I have checked in, I will update gdbserver. Otherwise, let me know what you think would be correct and I will implement that, instead, for both. thanks, Tom