From: Tsukasa OI via Gdb-patches <gdb-patches@sourceware.org>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Liao Shihua <shihua@iscas.ac.cn>
Cc: binutils@sourceware.org, gdb-patches@sourceware.org
Subject: [PATCH v4 0/3] RISC-V: Add 'Zmmul' extension
Date: Tue, 9 Aug 2022 12:37:24 +0900 [thread overview]
Message-ID: <cover.1660016195.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1657793406.git.research_trasio@irq.a4lg.com>
Hi RISC-V folks,
This patch is PATCH v4 of the Zmmul support patchset primarily for Binutils
but also contains some GDB changes (simulator fix and new testcase).
***WARNING (BLOCKER)***
Although I already assigned the copyright for my Binutils contribution, I
haven't completed the copyright assignment for my GDB contribution (because
the simulator that need to be fixed is a part of GDB).
So don't merge this until my copyright assignment completes.
Once that's done, I will send a ping to the people concerned.
Note:
To test the simulator, it requires another patch:
<https://sourceware.org/pipermail/binutils/2022-July/121814.html>
that fixes a minor problem on the arch-specific simulator testing.
This is also a GDB change so once my copyright assignment is done, I will ping
*and* submit the same patch to gdb-patches@sourceware.org.
Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_zmmul>
PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-July/121685.html>
PATCH v2:
<https://sourceware.org/pipermail/binutils/2022-July/121791.html>
PATCH v3:
<https://sourceware.org/pipermail/binutils/2022-July/121810.html>
This is based on the ISA Manual, draft-20220707-f518c25:
<https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220707-f518c25>
<https://github.com/riscv/riscv-isa-manual/commit/f518c259c008f926eba4aba67804f62531b6e94b>
This patchset also contains generic 'M' extension testcases.
[Changes: v3 -> v4]
- Minor rebase
- Fixed the issue that caused the failure of the simulator test.
[Changes: v2 -> v3]
- Minor rebase
- Fixed an issue which caused the simulator to stop working.
[Changes: v1 -> v2]
- Minor rebase
- On testcases, use macro symbols with no leading underscores
(__64_bit__ -> rv64 and __zmmul__ -> zmmul)
Thanks to Shihua for feedback.
- Renamed some testcases
[BUG in PATCH v2: Simulator stopped working after PATCH v2]
The cause was simple. The simulator supports I, M and A extensions and
the instruction is identified by those instruction classes:
- INSN_CLASS_I (for 'I')
- INSN_CLASS_M (for 'M')
- INSN_CLASS_A (for 'A')
I forgot to add INSN_CLASS_ZMMUL (for 'M') and that caused multiply
instructions to cause failure.
PATCH v3 fixed that and I added a testcase (checks whether all RV32M
instructions run without any fault).
[RFC: Implied extension (same text as PATCH v2)]
Tsukasa OI's (my) patchset implies 'Zmmul' from 'M'.
LIAO Shihua's patch does not imply 'Zmmul' from 'M'.
c.f. <https://sourceware.org/pipermail/binutils/2022-July/121685.html> (OI)
c.f. <https://sourceware.org/pipermail/binutils/2022-July/121728.html> (LIAO)
My position is derived from existing implications: Zhinx -> Zhinxmin and
Zfh -> Zfhmin. Big problem is, those implications are implemented by ME.
I have no or a little preference here and I would like
to hear your thoughts.
Thanks,
Tsukasa
Tsukasa OI (3):
RISC-V: Add 'M' extension testcases
RISC-V: Add 'Zmmul' extension
RISC-V: Add 'Zmmul' failure testcases
bfd/elfxx-riscv.c | 6 +++++
gas/testsuite/gas/riscv/attribute-09.d | 2 +-
gas/testsuite/gas/riscv/m-ext-32.d | 18 +++++++++++++
gas/testsuite/gas/riscv/m-ext-64.d | 23 ++++++++++++++++
.../gas/riscv/m-ext-fail-noarch-64.d | 4 +++
.../gas/riscv/m-ext-fail-noarch-64.l | 14 ++++++++++
gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 +++
gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 +++++
gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 +++
gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l | 5 ++++
gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 +++
gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l | 9 +++++++
gas/testsuite/gas/riscv/m-ext.s | 21 +++++++++++++++
gas/testsuite/gas/riscv/option-arch-02.d | 2 +-
gas/testsuite/gas/riscv/zmmul-32.d | 14 ++++++++++
gas/testsuite/gas/riscv/zmmul-64.d | 15 +++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 26 +++++++++----------
sim/riscv/sim-main.c | 1 +
sim/testsuite/riscv/m-ext.s | 18 +++++++++++++
20 files changed, 182 insertions(+), 15 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
create mode 100644 gas/testsuite/gas/riscv/m-ext.s
create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
create mode 100644 sim/testsuite/riscv/m-ext.s
base-commit: 65c9841b6fee984714509acef6e52366363072b6
--
2.34.1
next parent reply other threads:[~2022-08-09 3:39 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1657793406.git.research_trasio@irq.a4lg.com>
2022-08-09 3:37 ` Tsukasa OI via Gdb-patches [this message]
2022-08-09 3:37 ` [PATCH v4 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI via Gdb-patches
2022-08-09 3:37 ` [PATCH v4 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI via Gdb-patches
2022-08-09 3:37 ` [PATCH v4 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI via Gdb-patches
2022-08-29 1:58 ` [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI via Gdb-patches
2022-08-29 1:58 ` [PATCH v5 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI via Gdb-patches
2022-08-29 1:58 ` [PATCH v5 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI via Gdb-patches
2022-08-29 1:58 ` [PATCH v5 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI via Gdb-patches
2022-08-30 9:55 ` [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Nelson Chu
2022-09-01 7:47 ` Tsukasa OI via Gdb-patches
2022-08-31 1:46 ` [PATCH 0/1] sim: Fix RISC-V multiply instructions on simulator Tsukasa OI via Gdb-patches
2022-08-31 1:46 ` [PATCH 1/1] " Tsukasa OI via Gdb-patches
2022-09-14 10:55 ` [PING^1 PATCH 0/1] " Tsukasa OI via Gdb-patches
2022-09-14 10:55 ` [PING^1 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator Tsukasa OI via Gdb-patches
2022-09-21 16:01 ` [PING^2 PATCH 0/1] sim/riscv: Fix broken RISC-V simulater after implementing 'Zmmul' Tsukasa OI via Gdb-patches
2022-09-21 16:01 ` [PING^2 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator Tsukasa OI via Gdb-patches
2022-10-06 10:32 ` [PING^3 PATCH 0/1] sim/riscv: PR29595, Fix broken RISC-V simulater after implementing 'Zmmul' Tsukasa OI via Gdb-patches
2022-10-06 10:33 ` [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions Tsukasa OI via Gdb-patches
2022-10-06 15:58 ` Palmer Dabbelt
2022-10-06 16:14 ` Tsukasa OI via Gdb-patches
2022-10-06 18:27 ` Palmer Dabbelt
2022-10-11 11:43 ` Andrew Burgess via Gdb-patches
2022-10-11 11:41 ` Andrew Burgess via Gdb-patches
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