From: Nelson Chu <nelson@rivosinc.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Liao Shihua <shihua@iscas.ac.cn>,
binutils@sourceware.org, Kito Cheng <kito.cheng@sifive.com>,
Nelson Chu <nelson.chu@rivosinc.com>,
gdb-patches@sourceware.org
Subject: Re: [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension
Date: Tue, 30 Aug 2022 17:55:18 +0800 [thread overview]
Message-ID: <CAPpQWtA_MUe7NS5FPSE-p_+oQPVSewBiRJ2gbA=k8AT5MwJx+w@mail.gmail.com> (raw)
In-Reply-To: <cover.1661738291.git.research_trasio@irq.a4lg.com>
Thanks, committed except the gdb-sim part, since I'm not the
maintainer of gdb and sim, so I cannot approve the related stuff.
Besides that, some minor failures of ld testcases which caused by m
adding implicit zmmul. However, I also fix that since it's minor.
Nelson
On Mon, Aug 29, 2022 at 9:59 AM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> Hi RISC-V folks,
>
> 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a
> subset of 'M'; multiply and divide instructions).
>
> This patch is PATCH v5 of the Zmmul support patchset primarily for Binutils
> but also contains some GDB changes (a simulator fix and a new testcase).
>
> I completed the copyright assignment for my GDB contribution so minor
> simulator changes are now safe enough to merge.
>
> Changed Project(s):
> PATCH 1/3: Binutils
> PATCH 2/3: Binutils and GDB (not to make "temporally broken" revision)
> PATCH 3/3: Binutils
>
>
> Note:
> To confirm that the simulator is fixed, it requires another patch.
> <https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
> Without the patch above, 'Zmmul' extension will still work perfectly
> (even the simulator). Still, testing whether the simulator works with this
> extension (with `make check-sim') requires it.
>
>
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_zmmul>
> PATCH v1:
> <https://sourceware.org/pipermail/binutils/2022-July/121685.html>
> PATCH v2:
> <https://sourceware.org/pipermail/binutils/2022-July/121791.html>
> PATCH v3:
> <https://sourceware.org/pipermail/binutils/2022-July/121810.html>
> PATCH v4:
> <https://sourceware.org/pipermail/binutils/2022-August/122300.html>
>
>
> This is based on the ISA Manual, draft-20220707-f518c25:
> <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220707-f518c25>
> <https://github.com/riscv/riscv-isa-manual/commit/f518c259c008f926eba4aba67804f62531b6e94b>
>
> This patchset also contains generic 'M' extension testcases as PATCH 1/3 (it
> also tests for existence of the symbol `zmmul' so that it can also be a
> base of 'Zmmul' testcases).
>
>
> [Changes: v4 -> v5]
>
> - Clarify that PATCH 1/3 (new 'M' extension testcases) contains
> preparation for the 'Zmmul' extension.
>
>
> [BUG in PATCH v2 (fixed in v3): Simulator stopped working]
>
> The cause was simple. The RISC-V simulator supports I, M and A extensions
> and the instruction is identified by those instruction classes:
>
> - INSN_CLASS_I (for 'I')
> - INSN_CLASS_M (for 'M')
> - INSN_CLASS_A (for 'A')
>
> I forgot to add INSN_CLASS_ZMMUL (also for 'M') to that list and that caused
> multiply instructions to cause failure.
>
> PATCH v3 fixed that and I added a testcase (checks whether all RV32M
> instructions run without any fault).
>
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (3):
> RISC-V: Add 'M' extension testcases
> RISC-V: Add 'Zmmul' extension
> RISC-V: Add 'Zmmul' failure testcases
>
> bfd/elfxx-riscv.c | 6 +++++
> gas/testsuite/gas/riscv/attribute-09.d | 2 +-
> gas/testsuite/gas/riscv/m-ext-32.d | 18 +++++++++++++
> gas/testsuite/gas/riscv/m-ext-64.d | 23 ++++++++++++++++
> .../gas/riscv/m-ext-fail-noarch-64.d | 4 +++
> .../gas/riscv/m-ext-fail-noarch-64.l | 14 ++++++++++
> gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 +++
> gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 +++++
> gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 +++
> gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l | 5 ++++
> gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 +++
> gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l | 9 +++++++
> gas/testsuite/gas/riscv/m-ext.s | 21 +++++++++++++++
> gas/testsuite/gas/riscv/option-arch-02.d | 2 +-
> gas/testsuite/gas/riscv/zmmul-32.d | 14 ++++++++++
> gas/testsuite/gas/riscv/zmmul-64.d | 15 +++++++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 26 +++++++++----------
> sim/riscv/sim-main.c | 1 +
> sim/testsuite/riscv/m-ext.s | 18 +++++++++++++
> 20 files changed, 182 insertions(+), 15 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
> create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
> create mode 100644 gas/testsuite/gas/riscv/m-ext.s
> create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
> create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
> create mode 100644 sim/testsuite/riscv/m-ext.s
>
>
> base-commit: 27d582267a1d06e94661979f8893799ac235a768
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-08-30 9:55 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1657793406.git.research_trasio@irq.a4lg.com>
2022-08-09 3:37 ` [PATCH v4 " Tsukasa OI via Gdb-patches
2022-08-09 3:37 ` [PATCH v4 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI via Gdb-patches
2022-08-09 3:37 ` [PATCH v4 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI via Gdb-patches
2022-08-09 3:37 ` [PATCH v4 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI via Gdb-patches
2022-08-29 1:58 ` [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI via Gdb-patches
2022-08-29 1:58 ` [PATCH v5 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI via Gdb-patches
2022-08-29 1:58 ` [PATCH v5 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI via Gdb-patches
2022-08-29 1:58 ` [PATCH v5 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI via Gdb-patches
2022-08-30 9:55 ` Nelson Chu [this message]
2022-09-01 7:47 ` [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI via Gdb-patches
2022-08-31 1:46 ` [PATCH 0/1] sim: Fix RISC-V multiply instructions on simulator Tsukasa OI via Gdb-patches
2022-08-31 1:46 ` [PATCH 1/1] " Tsukasa OI via Gdb-patches
2022-09-14 10:55 ` [PING^1 PATCH 0/1] " Tsukasa OI via Gdb-patches
2022-09-14 10:55 ` [PING^1 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator Tsukasa OI via Gdb-patches
2022-09-21 16:01 ` [PING^2 PATCH 0/1] sim/riscv: Fix broken RISC-V simulater after implementing 'Zmmul' Tsukasa OI via Gdb-patches
2022-09-21 16:01 ` [PING^2 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator Tsukasa OI via Gdb-patches
2022-10-06 10:32 ` [PING^3 PATCH 0/1] sim/riscv: PR29595, Fix broken RISC-V simulater after implementing 'Zmmul' Tsukasa OI via Gdb-patches
2022-10-06 10:33 ` [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions Tsukasa OI via Gdb-patches
2022-10-06 15:58 ` Palmer Dabbelt
2022-10-06 16:14 ` Tsukasa OI via Gdb-patches
2022-10-06 18:27 ` Palmer Dabbelt
2022-10-11 11:43 ` Andrew Burgess via Gdb-patches
2022-10-11 11:41 ` Andrew Burgess via Gdb-patches
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