[PATCH v2 00/12] MIPS+testsuite: BLEZL stepping fix and associated test infrastructure

["Maciej W. Rozycki" <macro@orcam.me.uk>]

Hi,

 In the course of further verification additional issues have been found 
leading to the expansion of this patch set.  Minor issues in the original 
changes have been addressed as well.  I have retained the original heading 
for the purpose of thread sorting in mailer software even though the scope 
has now expanded beyond just the BLEZL stepping fix.  The original cover 
letter follows, adjusted as appropriate.

 This patch series is based on a buried bug fix extracted from a change 
submitted to add MIPSr6 support, most recently posted at 
<https://inbox.sourceware.org/gdb-patches/20250604123838.501596-3-jovan.dmitrovic@htecgroup.com/>, 
that corrects the handling of single-stepping through the BLEZL MIPS II 
instruction.

 This fix begged for test coverage, as indeed does all the MIPS software 
single-stepping infrastructure, so I have created a bunch of test cases 
roughly based on the skeleton already provided with said MIPSr6 change, 
however with extra feature checks to correctly enable individual tests 
based on the target configuration chosen for the testsuite invocation and 
target board's compatibility with the ISA required for test execution.

 This in turn revealed a repeated pattern of feature check code across 
numerous procedures in testsuite/lib/gdb.exp.  Rather than adding a bunch 
more, I chose to factor out the repeated pattern and build the new feature 
checks around it.  For illustration purposes I have converted the existing 
`powerpc*-*-*' target feature checks I could verify with my POWER9 test 
system.

 Consequently this set of 12 changes has resulted, comprised of the new 
generic procedure in 01/12, followed by the `powerpc*-*-*' updates in 
02/12, and then the MIPS changes in 03/12 through 12/12.  At this point 
MIPS I, MIPS II, MIPS16 and microMIPS, as well as DSP ASE CPU branches are 
covered at this point for condition evaluation and then the same branches 
and jumps for stepping through to the delay slot (i.e. no CP1/FPU/MIPS3D 
branches nor R6 branches or jumps).

 See individual change descriptions for details.  Authorship attributions 
are on the best knowledge basis.

 This patch set has been regression-tested with a `powerpc64le-linux-gnu' 
native configuration using POWER9 hardware and with the `mips-linux-gnu' 
and `mipsel-linux-gnu' targets, using real MIPS I, MIPS III and MIPS32r2 
hardware, the latter with regular MIPS and MIPS16 test configurations.  
Additional verification was done with QEMU, especially for microMIPS code, 
on the best effort basis and triggering emulation issues with QEMU itself 
(and overall instability of the target).  Detailed logs were examined for 
correctness with respect to the tests affected as well.

 I request approval for the non-MIPS parts of the patch series; I can 
self-approve the MIPS bits, though obviously I'm happy to address any 
feedback.

 Company copyright assignment with FSF is currently still being sorted.

 Previous iterations:

- v1 at: <https://inbox.sourceware.org/gdb-patches/alpine.DEB.2.21.2607220148540.14485@angie.orcam.me.uk/>.

  Maciej