Re: [0/1] RISC-V: Update CSR to priv 1.11.

[Jim Wilson <jimw@sifive.com>]

On Mon, Jun 8, 2020 at 2:39 PM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> Unless I misunderstand here, you asking why we don't use the xml
> target descriptions?  We do.  Or we _should_ do.  Maybe it's not
> working?  Is your target definitely sending back a description?  And
> it definitely includes register "dscratch" ?

qemu does have xml support; I added it.  The xml register files were
copied straight from the gdb xml files at the time I wrote the
patches.  Unfortunately, no one is actively maintaining this code, or
actively testing it, unless maybe you count Tom who is apparently
testing it, so the xml files no longer match the gdb ones.  The old
qemu version of the files does have a dscratch register because gdb
had it at the time.  qemu does have a concept of priv spec version,
but I doubt anyone has given any thought about how to match the xml
files to the priv spec version.  Currently, there is a single set of
xml files, and that isn't going to work long term.  The list of csr
registers needs to depend on the priv spec version.  descratch was
added in priv spec 1.9, and was dropped in 1.11.  qemu 4.0 has 1.9.1
and 1.10 support, so dscratch is a valid register name for priv spec
versions supported by qemu (though qemu is dropping 1.9.1 from the
development tree).  Anyways, dscratch needs to work in gdb, adding an
alias sounds like a reasonable solution.  There is a DECLARE_CSR_ALIAS
in include/opcode/riscv-opc.h for dscratch and other affected csrs,
but I guess gdb isn't handling those at the moment

Jim