From: Andrew Burgess <andrew.burgess@embecosm.com>
To: Jim Wilson <jimw@sifive.com>
Cc: Tom Tromey <tom@tromey.com>, gdb-patches@sourceware.org
Subject: Re: [RFC] gdb/riscv: Improved register alias name creation
Date: Thu, 11 Jun 2020 09:28:41 +0100 [thread overview]
Message-ID: <20200611082841.GJ2737@embecosm.com> (raw)
In-Reply-To: <CAFyWVabKhLgQau4n4p3irYUK2A-sRtoB4_Qr6HYpTEhFZ3c-JQ@mail.gmail.com>
* Jim Wilson <jimw@sifive.com> [2020-06-10 13:37:03 -0700]:
> On Tue, Jun 9, 2020 at 3:31 PM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > > (gdb) call debug.trace (me, "You")
> > > Could not fetch register "mucounteren"; remote failure reply 'E14'
> >
> > That is so weird! Based on the dump you included in the other email I
> > would have expected that to work.
>
> Bu mucounteren is one of the registers that we chose not to make an
> alias for because of the compatibility break. Apparently we will have
> to make an alias for it anyways because qemu 4.0 wants it.
No.
QEMU provides a register list that _includes_ mucounteren so GDB
doesn't need to know anything about this register or its aliases. The
XML built into GDB is used only for targets that don't provide a
target description. If a target provides a description, as in this
case, then the builtin description is not touched.
> And
> someone should fix qemu to use the right register list depending on
> the priv spec version.
Yes, this. Change the register description that QEMU sends based on
the machine its emulating and then GDB will "just work". GDB doesn't
need to know about privilege specs at all[1].
Thanks,
Andrew
[1] Native debugging is a slightly different case, but lets leave that
discussion for another day.
next prev parent reply other threads:[~2020-06-11 8:28 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 10:00 [0/1] RISC-V: Update CSR to priv 1.11 Nelson Chu
2020-03-12 10:00 ` [PATCH] RISC-V: Update CSR to privileged spec 1.11 Nelson Chu
2020-03-24 5:05 ` [PING] " Nelson Chu
2020-03-24 8:51 ` Andrew Burgess
2020-03-24 9:11 ` Nelson Chu
2020-06-08 15:37 ` [0/1] RISC-V: Update CSR to priv 1.11 Tom Tromey
2020-06-08 21:39 ` Andrew Burgess
2020-06-09 1:19 ` Jim Wilson
2020-06-09 10:27 ` Andrew Burgess
2020-06-09 20:12 ` Tom Tromey
2020-06-09 17:30 ` [RFC] gdb/riscv: Improved register alias name creation Andrew Burgess
2020-06-09 20:14 ` Jim Wilson
2020-06-09 22:47 ` Andrew Burgess
2020-06-10 9:31 ` Nelson Chu
2020-06-10 10:55 ` Andrew Burgess
2020-06-10 13:26 ` Nelson Chu
2020-06-09 20:54 ` Tom Tromey
2020-06-09 22:30 ` Andrew Burgess
[not found] ` <8736735bjx.fsf@tromey.com>
2020-06-10 13:01 ` Tom Tromey
2020-06-10 20:37 ` Jim Wilson
2020-06-11 8:28 ` Andrew Burgess [this message]
2020-06-09 22:58 ` Andrew Burgess
2020-06-10 12:53 ` Tom Tromey
[not found] ` <87mu5b3vm3.fsf@tromey.com>
2020-06-10 14:46 ` Tom Tromey
2020-06-11 13:16 ` [PATCH 0/2] [PATCHv2] " Andrew Burgess
2020-06-11 13:16 ` [PATCH 1/2] " Andrew Burgess
2020-06-11 13:16 ` [PATCH 2/2] gdb/riscv: Take CSR names from target description Andrew Burgess
2020-06-11 14:06 ` [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation Tom Tromey
2020-06-12 22:34 ` Andrew Burgess
2020-06-15 20:27 ` Tom Tromey
2020-06-16 7:56 ` Andrew Burgess
2020-06-16 12:03 ` Tom Tromey
2020-06-16 20:39 ` Andrew Burgess
2020-06-10 20:34 ` [RFC] " Jim Wilson
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