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From: Tom Tromey <tom@tromey.com>
To: Tom Tromey <tom@tromey.com>
Cc: Andrew Burgess <andrew.burgess@embecosm.com>,
	 Nelson Chu <nelson.chu@sifive.com>,
	 gdb-patches@sourceware.org
Subject: Re: [RFC] gdb/riscv: Improved register alias name creation
Date: Wed, 10 Jun 2020 08:46:46 -0600	[thread overview]
Message-ID: <87d0673rmx.fsf@tromey.com> (raw)
In-Reply-To: <87mu5b3vm3.fsf@tromey.com> (Tom Tromey's message of "Wed, 10 Jun 2020 07:20:52 -0600")

[-- Attachment #1: Type: text/plain, Size: 777 bytes --]

Tom> The first attachment is the log from git master.
Tom> Here's what I did:

Tom> (gdb) tar rem :7960
Tom> Remote debugging using :7960
Tom> 0x0000000000001000 in ?? ()
Tom> (gdb) print $dscratch
Tom> Could not fetch register "dscratch"; remote failure reply 'E14'
Tom> (gdb) print $dscratch0
Tom> $1 = void
Tom> (gdb) print $mucounteren
Tom> Could not fetch register "mucounteren"; remote failure reply 'E14'

I didn't apply your patch before that run.

Here's with your patch:

(gdb) tar rem :7960
Remote debugging using :7960
0x0000000000001000 in ?? ()
(gdb) print $dscratch
$1 = void
(gdb) print $dscratch0
Could not fetch register "dscratch0"; remote failure reply 'E14'
(gdb) print $mucounteren
Could not fetch register "mucounteren"; remote failure reply 'E14'

Tom


[-- Attachment #2: log with patch --]
[-- Type: text/plain, Size: 16957 bytes --]


w +$qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+;xmlRegisters=i386#6a
r +$PacketSize=1000;qXfer:features:read+;multiprocess+#5c
w +$vMustReplyEmpty#3a
r +$#00
w +$Hgp0.0#ad
r +$OK#9a
w +$qXfer:features:read:target.xml:0,ffb#79
r +$l<?xml version="1.0"?><!DOCTYPE target SYSTEM "gdb-target.dtd"><target><xi:include href="riscv-64bit-cpu.xml"/><xi:include href="riscv-64bit-fpu.xml"/><xi:include href="riscv-64bit-csr.xml"/></target>#ca
w +$qXfer:features:read:riscv-64bit-cpu.xml:0,ffb#64
r +$l<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n     Copying and distribution of this file, with or without modification,\n     are permitted in any medium without royalty provided the copyright\n     notice and this notice are preserved.  -->\n\n<!-- Register numbers are hard-coded in order to maintain backward\n     compatibility with older versions of tools that didn't use xml\n     register descriptions.  -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.cpu">\n  <reg name="zero" bitsize="64" type="int" regnum="0"/>\n  <reg name="ra" bitsize="64" type="code_ptr"/>\n  <reg name="sp" bitsize="64" type="data_ptr"/>\n  <reg name="gp" bitsize="64" type="data_ptr"/>\n  <reg name="tp" bitsize="64" type="data_ptr"/>\n  <reg name="t0" bitsize="64" type="int"/>\n  <reg name="t1" bitsize="64" type="int"/>\n  <reg name="t2" bitsize="64" type="int"/>\n  <reg name="fp" bitsize="64" type="data_ptr"/>\n  <reg name="s1" bitsize="64" type="int"/>\n  <reg name="a0" bitsize="64" type="int"/>\n  <reg name="a1" bitsize="64" type="int"/>\n  <reg name="a2" bitsize="64" type="int"/>\n  <reg name="a3" bitsize="64" type="int"/>\n  <reg name="a4" bitsize="64" type="int"/>\n  <reg name="a5" bitsize="64" type="int"/>\n  <reg name="a6" bitsize="64" type="int"/>\n  <reg name="a7" bitsize="64" type="int"/>\n  <reg name="s2" bitsize="64" type="int"/>\n  <reg name="s3" bitsize="64" type="int"/>\n  <reg name="s4" bitsize="64" type="int"/>\n  <reg name="s5" bitsize="64" type="int"/>\n  <reg name="s6" bitsize="64" type="int"/>\n  <reg name="s7" bitsize="64" type="int"/>\n  <reg name="s8" bitsize="64" type="int"/>\n  <reg name="s9" bitsize="64" type="int"/>\n  <reg name="s10" bitsize="64" type="int"/>\n  <reg name="s11" bitsize="64" type="int"/>\n  <reg name="t3" bitsize="64" type="int"/>\n  <reg name="t4" bitsize="64" type="int"/>\n  <reg name="t5" bitsize="64" type="int"/>\n  <reg name="t6" bitsize="64" type="int"/>\n  <reg name="pc" bitsize="64" type="code_ptr"/>\n</feature>\n#3d
w +$qXfer:features:read:riscv-64bit-fpu.xml:0,ffb#67
r +$m<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n     Copying and distribution of this file, with or without modification,\n     are permitted in any medium without royalty provided the copyright\n     notice and this notice are preserved.  -->\n\n<!-- Register numbers are hard-coded in order to maintain backward\n     compatibility with older versions of tools that didn't use xml\n     register descriptions.  -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.fpu">\n\n  <union id="riscv_double">\n    <field name="float" type="ieee_single"/>\n    <field name="double" type="ieee_double"/>\n  </union>\n\n  <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>\n  <reg name="ft1" bitsize="64" type="riscv_double"/>\n  <reg name="ft2" bitsize="64" type="riscv_double"/>\n  <reg name="ft3" bitsize="64" type="riscv_double"/>\n  <reg name="ft4" bitsize="64" type="riscv_double"/>\n  <reg name="ft5" bitsize="64" type="riscv_double"/>\n  <reg name="ft6" bitsize="64" type="riscv_double"/>\n  <reg name="ft7" bitsize="64" type="riscv_double"/>\n  <reg name="fs0" bitsize="64" type="riscv_double"/>\n  <reg name="fs1" bitsize="64" type="riscv_double"/>\n  <reg name="fa0" bitsize="64" type="riscv_double"/>\n  <reg name="fa1" bitsize="64" type="riscv_double"/>\n  <reg name="fa2" bitsize="64" type="riscv_double"/>\n  <reg name="fa3" bitsize="64" type="riscv_double"/>\n  <reg name="fa4" bitsize="64" type="riscv_double"/>\n  <reg name="fa5" bitsize="64" type="riscv_double"/>\n  <reg name="fa6" bitsize="64" type="riscv_double"/>\n  <reg name="fa7" bitsize="64" type="riscv_double"/>\n  <reg name="fs2" bitsize="64" type="riscv_double"/>\n  <reg name="fs3" bitsize="64" type="riscv_double"/>\n  <reg name="fs4" bitsize="64" type="riscv_double"/>\n  <reg name="fs5" bitsize="64" type="riscv_double"/>\n  <reg name="fs6" bitsize="64" type="riscv_double"/>\n  <reg name="fs7" bitsize="64" type="riscv_double"/>\n  <reg name="fs8" bitsize="64" type="riscv_double"/>\n  <reg name="fs9" bitsize="64" type="riscv_doub#ad
w +$qXfer:features:read:riscv-64bit-fpu.xml:7fd,ffb#38
r +$lle"/>\n  <reg name="fs10" bitsize="64" type="riscv_double"/>\n  <reg name="fs11" bitsize="64" type="riscv_double"/>\n  <reg name="ft8" bitsize="64" type="riscv_double"/>\n  <reg name="ft9" bitsize="64" type="riscv_double"/>\n  <reg name="ft10" bitsize="64" type="riscv_double"/>\n  <reg name="ft11" bitsize="64" type="riscv_double"/>\n\n  <reg name="fflags" bitsize="32" type="int" regnum="66"/>\n  <reg name="frm" bitsize="32" type="int" regnum="67"/>\n  <reg name="fcsr" bitsize="32" type="int" regnum="68"/>\n</feature>\n#55
w +$qXfer:features:read:riscv-64bit-csr.xml:0,ffb#64
r +$m<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n     Copying and distribution of this file, with or without modification,\n     are permitted in any medium without royalty provided the copyright\n     notice and this notice are preserved.  -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.csr">\n  <reg name="ustatus" bitsize="64"/>\n  <reg name="uie" bitsize="64"/>\n  <reg name="utvec" bitsize="64"/>\n  <reg name="uscratch" bitsize="64"/>\n  <reg name="uepc" bitsize="64"/>\n  <reg name="ucause" bitsize="64"/>\n  <reg name="utval" bitsize="64"/>\n  <reg name="uip" bitsize="64"/>\n  <reg name="fflags" bitsize="64"/>\n  <reg name="frm" bitsize="64"/>\n  <reg name="fcsr" bitsize="64"/>\n  <reg name="cycle" bitsize="64"/>\n  <reg name="time" bitsize="64"/>\n  <reg name="instret" bitsize="64"/>\n  <reg name="hpmcounter3" bitsize="64"/>\n  <reg name="hpmcounter4" bitsize="64"/>\n  <reg name="hpmcounter5" bitsize="64"/>\n  <reg name="hpmcounter6" bitsize="64"/>\n  <reg name="hpmcounter7" bitsize="64"/>\n  <reg name="hpmcounter8" bitsize="64"/>\n  <reg name="hpmcounter9" bitsize="64"/>\n  <reg name="hpmcounter10" bitsize="64"/>\n  <reg name="hpmcounter11" bitsize="64"/>\n  <reg name="hpmcounter12" bitsize="64"/>\n  <reg name="hpmcounter13" bitsize="64"/>\n  <reg name="hpmcounter14" bitsize="64"/>\n  <reg name="hpmcounter15" bitsize="64"/>\n  <reg name="hpmcounter16" bitsize="64"/>\n  <reg name="hpmcounter17" bitsize="64"/>\n  <reg name="hpmcounter18" bitsize="64"/>\n  <reg name="hpmcounter19" bitsize="64"/>\n  <reg name="hpmcounter20" bitsize="64"/>\n  <reg name="hpmcounter21" bitsize="64"/>\n  <reg name="hpmcounter22" bitsize="64"/>\n  <reg name="hpmcounter23" bitsize="64"/>\n  <reg name="hpmcounter24" bitsize="64"/>\n  <reg name="hpmcounter25" bitsize="64"/>\n  <reg name="hpmcounter26" bitsize="64"/>\n  <reg name="hpmcounter27" bitsize="64"/>\n  <reg name="hpmcounter28" bitsize="64"/>\n  <reg name="hpmcounter29" bitsize="64"/>\n  <reg name="hpmcounter30" bitsize="64"/>\n  <reg name="hpmcounter31"#12
w +$qXfer:features:read:riscv-64bit-csr.xml:7fd,ffb#35
r +$m bitsize="64"/>\n  <reg name="cycleh" bitsize="64"/>\n  <reg name="timeh" bitsize="64"/>\n  <reg name="instreth" bitsize="64"/>\n  <reg name="hpmcounter3h" bitsize="64"/>\n  <reg name="hpmcounter4h" bitsize="64"/>\n  <reg name="hpmcounter5h" bitsize="64"/>\n  <reg name="hpmcounter6h" bitsize="64"/>\n  <reg name="hpmcounter7h" bitsize="64"/>\n  <reg name="hpmcounter8h" bitsize="64"/>\n  <reg name="hpmcounter9h" bitsize="64"/>\n  <reg name="hpmcounter10h" bitsize="64"/>\n  <reg name="hpmcounter11h" bitsize="64"/>\n  <reg name="hpmcounter12h" bitsize="64"/>\n  <reg name="hpmcounter13h" bitsize="64"/>\n  <reg name="hpmcounter14h" bitsize="64"/>\n  <reg name="hpmcounter15h" bitsize="64"/>\n  <reg name="hpmcounter16h" bitsize="64"/>\n  <reg name="hpmcounter17h" bitsize="64"/>\n  <reg name="hpmcounter18h" bitsize="64"/>\n  <reg name="hpmcounter19h" bitsize="64"/>\n  <reg name="hpmcounter20h" bitsize="64"/>\n  <reg name="hpmcounter21h" bitsize="64"/>\n  <reg name="hpmcounter22h" bitsize="64"/>\n  <reg name="hpmcounter23h" bitsize="64"/>\n  <reg name="hpmcounter24h" bitsize="64"/>\n  <reg name="hpmcounter25h" bitsize="64"/>\n  <reg name="hpmcounter26h" bitsize="64"/>\n  <reg name="hpmcounter27h" bitsize="64"/>\n  <reg name="hpmcounter28h" bitsize="64"/>\n  <reg name="hpmcounter29h" bitsize="64"/>\n  <reg name="hpmcounter30h" bitsize="64"/>\n  <reg name="hpmcounter31h" bitsize="64"/>\n  <reg name="sstatus" bitsize="64"/>\n  <reg name="sedeleg" bitsize="64"/>\n  <reg name="sideleg" bitsize="64"/>\n  <reg name="sie" bitsize="64"/>\n  <reg name="stvec" bitsize="64"/>\n  <reg name="scounteren" bitsize="64"/>\n  <reg name="sscratch" bitsize="64"/>\n  <reg name="sepc" bitsize="64"/>\n  <reg name="scause" bitsize="64"/>\n  <reg name="stval" bitsize="64"/>\n  <reg name="sip" bitsize="64"/>\n  <reg name="satp" bitsize="64"/>\n  <reg name="mvendorid" bitsize="64"/>\n  <reg name="marchid" bitsize="64"/>\n  <reg name="mimpid" bitsize="64"/>\n  <reg name="mhartid" bitsize="64"/>\n  <reg name="mstatus" bitsize="64"/>\n  <reg name="misa" bitsize="64"/>\n  <reg name="medeleg" bitsize="#68
w +$qXfer:features:read:riscv-64bit-csr.xml:ffa,ffb#61
r +$m64"/>\n  <reg name="mideleg" bitsize="64"/>\n  <reg name="mie" bitsize="64"/>\n  <reg name="mtvec" bitsize="64"/>\n  <reg name="mcounteren" bitsize="64"/>\n  <reg name="mscratch" bitsize="64"/>\n  <reg name="mepc" bitsize="64"/>\n  <reg name="mcause" bitsize="64"/>\n  <reg name="mtval" bitsize="64"/>\n  <reg name="mip" bitsize="64"/>\n  <reg name="pmpcfg0" bitsize="64"/>\n  <reg name="pmpcfg1" bitsize="64"/>\n  <reg name="pmpcfg2" bitsize="64"/>\n  <reg name="pmpcfg3" bitsize="64"/>\n  <reg name="pmpaddr0" bitsize="64"/>\n  <reg name="pmpaddr1" bitsize="64"/>\n  <reg name="pmpaddr2" bitsize="64"/>\n  <reg name="pmpaddr3" bitsize="64"/>\n  <reg name="pmpaddr4" bitsize="64"/>\n  <reg name="pmpaddr5" bitsize="64"/>\n  <reg name="pmpaddr6" bitsize="64"/>\n  <reg name="pmpaddr7" bitsize="64"/>\n  <reg name="pmpaddr8" bitsize="64"/>\n  <reg name="pmpaddr9" bitsize="64"/>\n  <reg name="pmpaddr10" bitsize="64"/>\n  <reg name="pmpaddr11" bitsize="64"/>\n  <reg name="pmpaddr12" bitsize="64"/>\n  <reg name="pmpaddr13" bitsize="64"/>\n  <reg name="pmpaddr14" bitsize="64"/>\n  <reg name="pmpaddr15" bitsize="64"/>\n  <reg name="mcycle" bitsize="64"/>\n  <reg name="minstret" bitsize="64"/>\n  <reg name="mhpmcounter3" bitsize="64"/>\n  <reg name="mhpmcounter4" bitsize="64"/>\n  <reg name="mhpmcounter5" bitsize="64"/>\n  <reg name="mhpmcounter6" bitsize="64"/>\n  <reg name="mhpmcounter7" bitsize="64"/>\n  <reg name="mhpmcounter8" bitsize="64"/>\n  <reg name="mhpmcounter9" bitsize="64"/>\n  <reg name="mhpmcounter10" bitsize="64"/>\n  <reg name="mhpmcounter11" bitsize="64"/>\n  <reg name="mhpmcounter12" bitsize="64"/>\n  <reg name="mhpmcounter13" bitsize="64"/>\n  <reg name="mhpmcounter14" bitsize="64"/>\n  <reg name="mhpmcounter15" bitsize="64"/>\n  <reg name="mhpmcounter16" bitsize="64"/>\n  <reg name="mhpmcounter17" bitsize="64"/>\n  <reg name="mhpmcounter18" bitsize="64"/>\n  <reg name="mhpmcounter19" bitsize="64"/>\n  <reg name="mhpmcounter20" bitsize="64"/>\n  <reg name="mhpmcounter21" bitsize="64"/>\n  <reg name="mhpmcounter22" bitsize="64"/>\n  <reg name="mhpmcounter23" b#51
w +$qXfer:features:read:riscv-64bit-csr.xml:17f7,ffb#39
r +$mitsize="64"/>\n  <reg name="mhpmcounter24" bitsize="64"/>\n  <reg name="mhpmcounter25" bitsize="64"/>\n  <reg name="mhpmcounter26" bitsize="64"/>\n  <reg name="mhpmcounter27" bitsize="64"/>\n  <reg name="mhpmcounter28" bitsize="64"/>\n  <reg name="mhpmcounter29" bitsize="64"/>\n  <reg name="mhpmcounter30" bitsize="64"/>\n  <reg name="mhpmcounter31" bitsize="64"/>\n  <reg name="mcycleh" bitsize="64"/>\n  <reg name="minstreth" bitsize="64"/>\n  <reg name="mhpmcounter3h" bitsize="64"/>\n  <reg name="mhpmcounter4h" bitsize="64"/>\n  <reg name="mhpmcounter5h" bitsize="64"/>\n  <reg name="mhpmcounter6h" bitsize="64"/>\n  <reg name="mhpmcounter7h" bitsize="64"/>\n  <reg name="mhpmcounter8h" bitsize="64"/>\n  <reg name="mhpmcounter9h" bitsize="64"/>\n  <reg name="mhpmcounter10h" bitsize="64"/>\n  <reg name="mhpmcounter11h" bitsize="64"/>\n  <reg name="mhpmcounter12h" bitsize="64"/>\n  <reg name="mhpmcounter13h" bitsize="64"/>\n  <reg name="mhpmcounter14h" bitsize="64"/>\n  <reg name="mhpmcounter15h" bitsize="64"/>\n  <reg name="mhpmcounter16h" bitsize="64"/>\n  <reg name="mhpmcounter17h" bitsize="64"/>\n  <reg name="mhpmcounter18h" bitsize="64"/>\n  <reg name="mhpmcounter19h" bitsize="64"/>\n  <reg name="mhpmcounter20h" bitsize="64"/>\n  <reg name="mhpmcounter21h" bitsize="64"/>\n  <reg name="mhpmcounter22h" bitsize="64"/>\n  <reg name="mhpmcounter23h" bitsize="64"/>\n  <reg name="mhpmcounter24h" bitsize="64"/>\n  <reg name="mhpmcounter25h" bitsize="64"/>\n  <reg name="mhpmcounter26h" bitsize="64"/>\n  <reg name="mhpmcounter27h" bitsize="64"/>\n  <reg name="mhpmcounter28h" bitsize="64"/>\n  <reg name="mhpmcounter29h" bitsize="64"/>\n  <reg name="mhpmcounter30h" bitsize="64"/>\n  <reg name="mhpmcounter31h" bitsize="64"/>\n  <reg name="mhpmevent3" bitsize="64"/>\n  <reg name="mhpmevent4" bitsize="64"/>\n  <reg name="mhpmevent5" bitsize="64"/>\n  <reg name="mhpmevent6" bitsize="64"/>\n  <reg name="mhpmevent7" bitsize="64"/>\n  <reg name="mhpmevent8" bitsize="64"/>\n  <reg name="mhpmevent9" bitsize="64"/>\n  <reg name="mhpmevent10" bitsize="64"/>\n  <reg name="mhpmeven#dc
w +$qXfer:features:read:riscv-64bit-csr.xml:1ff4,ffb#65
r +$lt11" bitsize="64"/>\n  <reg name="mhpmevent12" bitsize="64"/>\n  <reg name="mhpmevent13" bitsize="64"/>\n  <reg name="mhpmevent14" bitsize="64"/>\n  <reg name="mhpmevent15" bitsize="64"/>\n  <reg name="mhpmevent16" bitsize="64"/>\n  <reg name="mhpmevent17" bitsize="64"/>\n  <reg name="mhpmevent18" bitsize="64"/>\n  <reg name="mhpmevent19" bitsize="64"/>\n  <reg name="mhpmevent20" bitsize="64"/>\n  <reg name="mhpmevent21" bitsize="64"/>\n  <reg name="mhpmevent22" bitsize="64"/>\n  <reg name="mhpmevent23" bitsize="64"/>\n  <reg name="mhpmevent24" bitsize="64"/>\n  <reg name="mhpmevent25" bitsize="64"/>\n  <reg name="mhpmevent26" bitsize="64"/>\n  <reg name="mhpmevent27" bitsize="64"/>\n  <reg name="mhpmevent28" bitsize="64"/>\n  <reg name="mhpmevent29" bitsize="64"/>\n  <reg name="mhpmevent30" bitsize="64"/>\n  <reg name="mhpmevent31" bitsize="64"/>\n  <reg name="tselect" bitsize="64"/>\n  <reg name="tdata1" bitsize="64"/>\n  <reg name="tdata2" bitsize="64"/>\n  <reg name="tdata3" bitsize="64"/>\n  <reg name="dcsr" bitsize="64"/>\n  <reg name="dpc" bitsize="64"/>\n  <reg name="dscratch" bitsize="64"/>\n  <reg name="hstatus" bitsize="64"/>\n  <reg name="hedeleg" bitsize="64"/>\n  <reg name="hideleg" bitsize="64"/>\n  <reg name="hie" bitsize="64"/>\n  <reg name="htvec" bitsize="64"/>\n  <reg name="hscratch" bitsize="64"/>\n  <reg name="hepc" bitsize="64"/>\n  <reg name="hcause" bitsize="64"/>\n  <reg name="hbadaddr" bitsize="64"/>\n  <reg name="hip" bitsize="64"/>\n  <reg name="mbase" bitsize="64"/>\n  <reg name="mbound" bitsize="64"/>\n  <reg name="mibase" bitsize="64"/>\n  <reg name="mibound" bitsize="64"/>\n  <reg name="mdbase" bitsize="64"/>\n  <reg name="mdbound" bitsize="64"/>\n  <reg name="mucounteren" bitsize="64"/>\n  <reg name="mscounteren" bitsize="64"/>\n  <reg name="mhcounteren" bitsize="64"/>\n</feature>\n#9f
w +$qTStatus#49
r +$#00
w +$?#3f
r +$T05thread:p01.01;#06
w +$qfThreadInfo#bb
r +$mp01.01#cd
w +$qsThreadInfo#c8
r +$l#6c
w +$qAttached:1#fa
r +$0#30
w +$Hc-1#09
r +$OK#9a
w +$qOffsets#4b
r +$#00
w +$g#67
r +$000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000#01
w +$qfThreadInfo#bb
r +$mp01.01#cd
w +$qsThreadInfo#c8
r +$l#6c
w +$m1000,4#8e
r +$97020000#92
w +$mffc,4#fc
r +$00000000#80
w +$qSymbol::#5b
r +$#00
w +
c print $dscratch
c print $dscratch0
w $p121#04
r +$E14#aa
w +
End of log

  parent reply	other threads:[~2020-06-10 14:46 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-12 10:00 [0/1] RISC-V: Update CSR to priv 1.11 Nelson Chu
2020-03-12 10:00 ` [PATCH] RISC-V: Update CSR to privileged spec 1.11 Nelson Chu
2020-03-24  5:05   ` [PING] " Nelson Chu
2020-03-24  8:51   ` Andrew Burgess
2020-03-24  9:11     ` Nelson Chu
2020-06-08 15:37 ` [0/1] RISC-V: Update CSR to priv 1.11 Tom Tromey
2020-06-08 21:39   ` Andrew Burgess
2020-06-09  1:19     ` Jim Wilson
2020-06-09 10:27       ` Andrew Burgess
2020-06-09 20:12     ` Tom Tromey
2020-06-09 17:30   ` [RFC] gdb/riscv: Improved register alias name creation Andrew Burgess
2020-06-09 20:14     ` Jim Wilson
2020-06-09 22:47       ` Andrew Burgess
2020-06-10  9:31         ` Nelson Chu
2020-06-10 10:55           ` Andrew Burgess
2020-06-10 13:26             ` Nelson Chu
2020-06-09 20:54     ` Tom Tromey
2020-06-09 22:30       ` Andrew Burgess
     [not found]         ` <8736735bjx.fsf@tromey.com>
2020-06-10 13:01           ` Tom Tromey
2020-06-10 20:37         ` Jim Wilson
2020-06-11  8:28           ` Andrew Burgess
2020-06-09 22:58       ` Andrew Burgess
2020-06-10 12:53         ` Tom Tromey
     [not found]           ` <87mu5b3vm3.fsf@tromey.com>
2020-06-10 14:46             ` Tom Tromey [this message]
2020-06-11 13:16               ` [PATCH 0/2] [PATCHv2] " Andrew Burgess
2020-06-11 13:16                 ` [PATCH 1/2] " Andrew Burgess
2020-06-11 13:16                 ` [PATCH 2/2] gdb/riscv: Take CSR names from target description Andrew Burgess
2020-06-11 14:06                 ` [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation Tom Tromey
2020-06-12 22:34                   ` Andrew Burgess
2020-06-15 20:27                     ` Tom Tromey
2020-06-16  7:56                       ` Andrew Burgess
2020-06-16 12:03                         ` Tom Tromey
2020-06-16 20:39                           ` Andrew Burgess
2020-06-10 20:34       ` [RFC] " Jim Wilson

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