[PATCH] aarch64 sim xtn2 bug fix

[Jim Wilson <jim.wilson@linaro.org>]

[-- Attachment #1: Type: text/plain, Size: 349 bytes --]

The code is applying a bias (shift) to inputs which is wrong.  The
index in case 2 should be i + 2 not i + 4.  We can simplify the code a
little and remove the if statement, reducing 7 lines to 3 in each of
the 3 cases.

The testcase works with the patch, and fails without.  The patch
reduces GCC C testsuite failures from 2174 to 2108 (-66).

Jim

[-- Attachment #2: aarch64-sim-xtn2.patch --]
[-- Type: text/x-patch, Size: 3119 bytes --]

	sim/aarch64/
	* simulator.c (do_vec_XTN): Delete shifts.  In case 2, change index
	from i + 4 to i + 2.  Delete if on bias, change index to i + bias * X.

	sim/testsuite/sim/aarch64/
	* xtn.s: New.

diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 36129e5..c8e65c5 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -4206,33 +4203,21 @@ do_vec_XTN (sim_cpu *cpu)
   switch (INSTR (23, 22))
     {
     case 0:
-      if (bias)
-	for (i = 0; i < 8; i++)
-	  aarch64_set_vec_u8 (cpu, vd, i + 8,
-			      aarch64_get_vec_u16 (cpu, vs, i) >> 8);
-      else
-	for (i = 0; i < 8; i++)
-	  aarch64_set_vec_u8 (cpu, vd, i, aarch64_get_vec_u16 (cpu, vs, i));
+      for (i = 0; i < 8; i++)
+	aarch64_set_vec_u8 (cpu, vd, i + (bias * 8),
+			    aarch64_get_vec_u16 (cpu, vs, i));
       return;
 
     case 1:
-      if (bias)
-	for (i = 0; i < 4; i++)
-	  aarch64_set_vec_u16 (cpu, vd, i + 4,
-			       aarch64_get_vec_u32 (cpu, vs, i) >> 16);
-      else
-	for (i = 0; i < 4; i++)
-	  aarch64_set_vec_u16 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vs, i));
+      for (i = 0; i < 4; i++)
+	aarch64_set_vec_u16 (cpu, vd, i + (bias * 4),
+			     aarch64_get_vec_u32 (cpu, vs, i));
       return;
 
     case 2:
-      if (bias)
-	for (i = 0; i < 2; i++)
-	  aarch64_set_vec_u32 (cpu, vd, i + 4,
-			       aarch64_get_vec_u64 (cpu, vs, i) >> 32);
-      else
-	for (i = 0; i < 2; i++)
-	  aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u64 (cpu, vs, i));
+      for (i = 0; i < 2; i++)
+	aarch64_set_vec_u32 (cpu, vd, i + (bias * 2),
+			     aarch64_get_vec_u64 (cpu, vs, i));
       return;
     }
 }
diff --git a/sim/testsuite/sim/aarch64/xtn.s b/sim/testsuite/sim/aarch64/xtn.s
new file mode 100644
index 0000000..de369f7
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/xtn.s
@@ -0,0 +1,79 @@
+# mach: aarch64
+
+# Check the extract narrow instructions: xtn, xtn2.
+
+.include "testutils.inc"
+
+	.data
+	.align 4
+input:
+	.word 0x04030201
+	.word 0x08070605
+	.word 0x0c0b0a09
+	.word 0x100f0e0d
+input2:
+	.word 0x14131211
+	.word 0x18171615
+	.word 0x1c1b1a19
+	.word 0x201f1e1d
+x16b:
+	.word 0x07050301
+	.word 0x0f0d0b09
+	.word 0x17151311
+	.word 0x1f1d1b19
+x8h:
+	.word 0x06050201
+	.word 0x0e0d0a09
+	.word 0x16151211
+	.word 0x1e1d1a19
+x4s:
+	.word 0x04030201
+	.word 0x0c0b0a09
+	.word 0x14131211
+	.word 0x1c1b1a19
+
+	start
+	adrp x0, input
+	ldr q0, [x0, #:lo12:input]
+	adrp x0, input2
+	ldr q1, [x0, #:lo12:input2]
+
+	xtn v2.8b, v0.8h
+	xtn2 v2.16b, v1.8h
+	mov x1, v2.d[0]
+	mov x2, v2.d[1]
+	adrp x3, x16b
+	ldr x4, [x3, #:lo12:x16b]
+	cmp x1, x4
+	bne .Lfailure
+	ldr x5, [x3, #:lo12:x16b+8]
+	cmp x2, x5
+	bne .Lfailure
+
+	xtn v2.4h, v0.4s
+	xtn2 v2.8h, v1.4s
+	mov x1, v2.d[0]
+	mov x2, v2.d[1]
+	adrp x3, x8h
+	ldr x4, [x3, #:lo12:x8h]
+	cmp x1, x4
+	bne .Lfailure
+	ldr x5, [x3, #:lo12:x8h+8]
+	cmp x2, x5
+	bne .Lfailure
+
+	xtn v2.2s, v0.2d
+	xtn2 v2.4s, v1.2d
+	mov x1, v2.d[0]
+	mov x2, v2.d[1]
+	adrp x3, x4s
+	ldr x4, [x3, #:lo12:x4s]
+	cmp x1, x4
+	bne .Lfailure
+	ldr x5, [x3, #:lo12:x4s+8]
+	cmp x2, x5
+	bne .Lfailure
+
+	pass
+.Lfailure:
+	fail