[PATCH ARM] Fixing problem of 32bit multiplication instruction 'smull'

["Jayant R. Sonar" <Jayant.Sonar@kpitcummins.com>]

Hi,

While testing a 32bit x 32bit multiplication instruction 'smull' 
using GDB, I faced a problem for Cortex-A9 target.

Consider the following sample assembly code.
Compilation command I used: arm-eabi-gcc -march=armv7-a test.s
==============================================================
        .global main
main:
        movw    r2, 0x5432
        movt    r2, 0x7698
        movw    r3, 0x5678
        movt    r3, 0x1234
        smull   r1, r3, r3, r2
        bx      lr
==============================================================

The "smull" instruction syntax is: 
	 SMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>.
Here, the signed 32bit operands from Rm and Rn are multiplied and the
64 bit result is stored in the register pair RdHi, RdLo.

The GDB debugger throws the following error on executing 'smull':
     sim: MULTIPLY64 - INVALID ARGUMENTS

This was because the "Multiply64()" routine from ARM simulator source
file 'armemu.c' checks for a condition:
	 nRdHi != nRm &&  nRdLo != nRm
 
However, as per the "ARM Architecture Reference Manual ARMv7-A and 
ARMv7-R edition, ARM DDI 0406C.b, ID072512", section "A8.8.189 SMULL",
this condition is required only if "ArchVersion() < 6". 

Therefore, in case of Cortex-A9 target this condition should not be 
tested. However, this is not happening resulting in condition failure
and ultimately instruction execution failure.

Following change in the "Multiply64()" makes this check conditional 
and resolves the problem.

--- gdb-a/sim/arm/armemu.c      2013-05-14 15:20:47.000000000 +0530
+++ gdb-b/sim/arm/armemu.c      2013-05-14 15:23:20.000000000 +0530
@@ -5077,8 +5077,9 @@ Multiply64 (ARMul_State * state, ARMword
       && nRs   != 15
       && nRm   != 15
       && nRdHi != nRdLo
-      && nRdHi != nRm
-      && nRdLo != nRm)
+      && (state->is_v6
+          || (   nRdHi != nRm
+              && nRdLo != nRm)))
     {
       /* Intermediate results.  */
       ARMword lo, mid1, mid2, hi;

It alters the condition check for targets ARMv6 and above only.
Can someone please review this change?

Regression tested successfully for gdb and simulator with cortex-a9 
target. 

To add more here, for Cortex-A9 target, without this change I was
getting 14302 unexpected failures during GCC regression testing. Most
of them were execution failures, failing with same error message as I
was getting with above mentioned sample code. With this change 
the unexpected failure count has got reduced to just 1363.

Regards
Jayant