From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8719 invoked by alias); 14 May 2013 13:16:06 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 8698 invoked by uid 89); 14 May 2013 13:16:04 -0000 X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,RCVD_IN_DNSWL_MED,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_YE,TW_OV autolearn=ham version=3.3.1 Received: from tx2ehsobe003.messaging.microsoft.com (HELO tx2outboundpool.messaging.microsoft.com) (65.55.88.13) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 14 May 2013 13:16:03 +0000 Received: from mail42-tx2-R.bigfish.com (10.9.14.253) by TX2EHSOBE015.bigfish.com (10.9.40.35) with Microsoft SMTP Server id 14.1.225.23; Tue, 14 May 2013 13:16:01 +0000 Received: from mail42-tx2 (localhost [127.0.0.1]) by mail42-tx2-R.bigfish.com (Postfix) with ESMTP id BF5A1440272 for ; Tue, 14 May 2013 13:16:01 +0000 (UTC) X-Forefront-Antispam-Report: CIP:59.163.77.45;KIP:(null);UIP:(null);IPV:NLI;H:KCHJEXHC01.kpit.com;RD:59.163.77.45.static.vsnl.net.in;EFVD:NLI X-SpamScore: -1 X-BigFish: VPS-1(zz936eIzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6hzzz2dh2a8h668h839h944hd25hf0ah1220h1288h12a5h12a9h12bdh137ah13b6h1441h14ddh1504h1537h153bh15d0h162dh1631h1758h18e1h1946h19b5h1b0ah1d0ch1d2eh1d3fh1155h) Received: from mail42-tx2 (localhost.localdomain [127.0.0.1]) by mail42-tx2 (MessageSwitch) id 136853735949602_17177; Tue, 14 May 2013 13:15:59 +0000 (UTC) Received: from TX2EHSMHS015.bigfish.com (unknown [10.9.14.240]) by mail42-tx2.bigfish.com (Postfix) with ESMTP id F31A824008D for ; Tue, 14 May 2013 13:15:58 +0000 (UTC) Received: from KCHJEXHC01.kpit.com (59.163.77.45) by TX2EHSMHS015.bigfish.com (10.9.99.115) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 14 May 2013 13:15:57 +0000 Received: from KCHJEXMB03.kpit.com ([169.254.4.30]) by KCHJEXHC01.kpit.com ([172.10.15.73]) with mapi id 14.03.0123.003; Tue, 14 May 2013 18:45:54 +0530 From: "Jayant R. Sonar" To: "gdb-patches@sourceware.org" CC: Kaushik Phatak Subject: [PATCH ARM] Fixing problem of 32bit multiplication instruction 'smull' Date: Tue, 14 May 2013 13:16:00 -0000 Message-ID: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: kpitcummins.com X-SW-Source: 2013-05/txt/msg00463.txt.bz2 Hi, While testing a 32bit x 32bit multiplication instruction 'smull'=20 using GDB, I faced a problem for Cortex-A9 target. Consider the following sample assembly code. Compilation command I used: arm-eabi-gcc -march=3Darmv7-a test.s =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D .global main main: movw r2, 0x5432 movt r2, 0x7698 movw r3, 0x5678 movt r3, 0x1234 smull r1, r3, r3, r2 bx lr =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The "smull" instruction syntax is:=20 SMULL{S} , , , . Here, the signed 32bit operands from Rm and Rn are multiplied and the 64 bit result is stored in the register pair RdHi, RdLo. The GDB debugger throws the following error on executing 'smull': sim: MULTIPLY64 - INVALID ARGUMENTS This was because the "Multiply64()" routine from ARM simulator source file 'armemu.c' checks for a condition: nRdHi !=3D nRm && nRdLo !=3D nRm =20 However, as per the "ARM Architecture Reference Manual ARMv7-A and=20 ARMv7-R edition, ARM DDI 0406C.b, ID072512", section "A8.8.189 SMULL", this condition is required only if "ArchVersion() < 6".=20 Therefore, in case of Cortex-A9 target this condition should not be=20 tested. However, this is not happening resulting in condition failure and ultimately instruction execution failure. Following change in the "Multiply64()" makes this check conditional=20 and resolves the problem. --- gdb-a/sim/arm/armemu.c 2013-05-14 15:20:47.000000000 +0530 +++ gdb-b/sim/arm/armemu.c 2013-05-14 15:23:20.000000000 +0530 @@ -5077,8 +5077,9 @@ Multiply64 (ARMul_State * state, ARMword && nRs !=3D 15 && nRm !=3D 15 && nRdHi !=3D nRdLo - && nRdHi !=3D nRm - && nRdLo !=3D nRm) + && (state->is_v6 + || ( nRdHi !=3D nRm + && nRdLo !=3D nRm))) { /* Intermediate results. */ ARMword lo, mid1, mid2, hi; It alters the condition check for targets ARMv6 and above only. Can someone please review this change? Regression tested successfully for gdb and simulator with cortex-a9=20 target.=20 To add more here, for Cortex-A9 target, without this change I was getting 14302 unexpected failures during GCC regression testing. Most of them were execution failures, failing with same error message as I was getting with above mentioned sample code. With this change=20 the unexpected failure count has got reduced to just 1363. Regards Jayant