From: Pedro Alves <palves@redhat.com>
To: Jiong Wang <jiwang@tilera.com>
Cc: Yao Qi <yao@codesourcery.com>,
Joel Brobecker <brobecker@adacore.com>,
gdb-patches@sourceware.org, Walter Lee <walt@tilera.com>
Subject: Re: [RFC/TileGX 2/6] simplify the handling of skip prologue for plt stub
Date: Fri, 01 Mar 2013 15:59:00 -0000 [thread overview]
Message-ID: <5130D06A.9000701@redhat.com> (raw)
In-Reply-To: <5130B63A.1060304@tilera.com>
On 03/01/2013 02:07 PM, Jiong Wang wrote:
>
> * tilegx-tdep.c (tilegx_analyze_prologue): Improve the evaluation
> of "instbuf_size".
> (tilegx_skip_prologue): Improve the evaluation of the end address
> for prologue analyze.
"improve" is a "Why?", and subjective. ChangeLogs are objective, and document
the "What" changed. I suggest:
* tilegx-tdep.c (tilegx_analyze_prologue): Limit bundle reading to END_ADDR.
(tilegx_skip_prologue): Limit prologue analysis to section end.
> tilegx_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
> {
> - CORE_ADDR func_start;
> + CORE_ADDR func_start, end_pc;
> + struct obj_section *s = NULL;
No need to initialize 's' here, it's unconditionally initialized below.
> + s = find_pc_section (start_pc);
OK with these changes.
Thanks.
--
Pedro Alves
next prev parent reply other threads:[~2013-03-01 15:59 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-18 9:25 Jiong Wang
2013-01-18 13:15 ` Joel Brobecker
2013-01-18 15:12 ` Jiong Wang
2013-01-18 17:30 ` Pedro Alves
2013-02-15 3:22 ` Jiong Wang
2013-02-16 4:50 ` Yao Qi
2013-02-20 2:49 ` Jiong Wang
2013-02-20 4:11 ` Yao Qi
2013-02-21 13:40 ` Jiong Wang
2013-03-01 10:35 ` Jiong Wang
2013-03-01 11:31 ` Pedro Alves
2013-03-01 14:08 ` Jiong Wang
2013-03-01 15:59 ` Pedro Alves [this message]
2013-03-02 1:40 ` [COMMITTED][RFC/TileGX " Jiong Wang
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