Re: [patch V2, testsuite] gdb.base/savedregs.exp: SIGSEGV -> SIGALRM

[Yao Qi <yao@codesourcery.com>]

On 06/20/2011 07:10 PM, Mark Kettenis wrote:
> My concern with using SIGILL (apart from generating an instruction
> that forces SIGALL on all architectures we support) is that you're
> going to end up testing a different unwinder as well.  Typically in
> the SIGSEGV case you'll end up at the faulting instruction, which is
> defenitely in the function body, where we should be using the DWARF
> CFI unwinder.  But for SIGILL you could end up at the instruction
> after the trapping instruction, which is likely to be in the function
> epilogue which may be handled by an epilogue unwinder.

Oh, I don't know PC could be the next instruction of that illegal
instruction.  At least, some years ago, when I was working on PowerPC,
PC still points to the illegal instruction when SIGILL is triggered.

> 
>> > Maybe, another option is to define invalid instruction for each targets
>> > in test case.
> Perhaps a reasonable compromise is to do something like:
> 
> static void
> thrower (void)
> {
>   *(char *)0 = 0;
> #ifdef __arm__
>   asm(".word 0xffff");
> #endif
> }
> 
> and then handle both SIGSEGV and SIGILL.

Yes, that looks good to me in general.  It can be like this,

#ifdef __UCLIBC__
#if !(defined(__UCLIBC_HAS_MMU__) || defined(__ARCH_HAS_MMU__))
#define HAS_NOMMU
#endif
#endif

static void
thrower (void)
{
#if defined(HAS_NOMMU)

#if defined(__arm__)
  asm(".word 0xffff");
#elif defined(__foo__)
  asm(".word 0xeeeee"); // invalid instruction for port foo.
#else
#error Please write an invalid instruction here for your target
#endif

#else
  *(char *)0 = 0;
#endif
}


I'll write a new patch later.

-- 
Yao (齐尧)