* [PATCH] [AArch64] Expose the BTI BTYPE more explicitly in the registers
@ 2021-11-17 13:05 Luis Machado via Gdb-patches
2021-11-17 13:50 ` Alan Hayward via Gdb-patches
0 siblings, 1 reply; 3+ messages in thread
From: Luis Machado via Gdb-patches @ 2021-11-17 13:05 UTC (permalink / raw)
To: gdb-patches
Augment the register description XML to expose the BTI BTYPE field contained
in the CPSR register. It will be displayed like so:
cpsr 0x60001000 [ EL=0 BTYPE=0 SSBS C Z ]
---
gdb/features/aarch64-core.c | 1 +
gdb/features/aarch64-core.xml | 3 +++
2 files changed, 4 insertions(+)
diff --git a/gdb/features/aarch64-core.c b/gdb/features/aarch64-core.c
index a080a641c45..bb707173be6 100644
--- a/gdb/features/aarch64-core.c
+++ b/gdb/features/aarch64-core.c
@@ -18,6 +18,7 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
tdesc_add_flag (type_with_fields, 7, "I");
tdesc_add_flag (type_with_fields, 8, "A");
tdesc_add_flag (type_with_fields, 9, "D");
+ tdesc_add_bitfield (type_with_fields, "BTYPE", 10, 11);
tdesc_add_flag (type_with_fields, 12, "SSBS");
tdesc_add_flag (type_with_fields, 20, "IL");
tdesc_add_flag (type_with_fields, 21, "SS");
diff --git a/gdb/features/aarch64-core.xml b/gdb/features/aarch64-core.xml
index d63456956fd..a328ede508c 100644
--- a/gdb/features/aarch64-core.xml
+++ b/gdb/features/aarch64-core.xml
@@ -61,6 +61,9 @@
<!-- Debug exception mask. -->
<field name="D" start="9" end="9"/>
+ <!-- ARMv8.5-A: Branch Target Identification BTYPE. -->
+ <field name="BTYPE" start="10" end="11"/>
+
<!-- ARMv8.0-A: Speculative Store Bypass. -->
<field name="SSBS" start="12" end="12"/>
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] [AArch64] Expose the BTI BTYPE more explicitly in the registers
2021-11-17 13:05 [PATCH] [AArch64] Expose the BTI BTYPE more explicitly in the registers Luis Machado via Gdb-patches
@ 2021-11-17 13:50 ` Alan Hayward via Gdb-patches
2021-11-17 13:57 ` Luis Machado via Gdb-patches
0 siblings, 1 reply; 3+ messages in thread
From: Alan Hayward via Gdb-patches @ 2021-11-17 13:50 UTC (permalink / raw)
To: Luis Machado; +Cc: nd, gdb-patches\@sourceware.org
> On 17 Nov 2021, at 13:05, Luis Machado <luis.machado@linaro.org> wrote:
>
> Augment the register description XML to expose the BTI BTYPE field contained
> in the CPSR register. It will be displayed like so:
>
> cpsr 0x60001000 [ EL=0 BTYPE=0 SSBS C Z ]
Good spot. Did a quick check, and couldn't see any other flags missing.
Code is obvious and looks fine to me.
Alan.
> ---
> gdb/features/aarch64-core.c | 1 +
> gdb/features/aarch64-core.xml | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/gdb/features/aarch64-core.c b/gdb/features/aarch64-core.c
> index a080a641c45..bb707173be6 100644
> --- a/gdb/features/aarch64-core.c
> +++ b/gdb/features/aarch64-core.c
> @@ -18,6 +18,7 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
> tdesc_add_flag (type_with_fields, 7, "I");
> tdesc_add_flag (type_with_fields, 8, "A");
> tdesc_add_flag (type_with_fields, 9, "D");
> + tdesc_add_bitfield (type_with_fields, "BTYPE", 10, 11);
> tdesc_add_flag (type_with_fields, 12, "SSBS");
> tdesc_add_flag (type_with_fields, 20, "IL");
> tdesc_add_flag (type_with_fields, 21, "SS");
> diff --git a/gdb/features/aarch64-core.xml b/gdb/features/aarch64-core.xml
> index d63456956fd..a328ede508c 100644
> --- a/gdb/features/aarch64-core.xml
> +++ b/gdb/features/aarch64-core.xml
> @@ -61,6 +61,9 @@
> <!-- Debug exception mask. -->
> <field name="D" start="9" end="9"/>
>
> + <!-- ARMv8.5-A: Branch Target Identification BTYPE. -->
> + <field name="BTYPE" start="10" end="11"/>
> +
> <!-- ARMv8.0-A: Speculative Store Bypass. -->
> <field name="SSBS" start="12" end="12"/>
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] [AArch64] Expose the BTI BTYPE more explicitly in the registers
2021-11-17 13:50 ` Alan Hayward via Gdb-patches
@ 2021-11-17 13:57 ` Luis Machado via Gdb-patches
0 siblings, 0 replies; 3+ messages in thread
From: Luis Machado via Gdb-patches @ 2021-11-17 13:57 UTC (permalink / raw)
To: Alan Hayward; +Cc: nd, gdb-patches\@sourceware.org
On 11/17/21 10:50 AM, Alan Hayward wrote:
>
>
>> On 17 Nov 2021, at 13:05, Luis Machado <luis.machado@linaro.org> wrote:
>>
>> Augment the register description XML to expose the BTI BTYPE field contained
>> in the CPSR register. It will be displayed like so:
>>
>> cpsr 0x60001000 [ EL=0 BTYPE=0 SSBS C Z ]
>
> Good spot. Did a quick check, and couldn't see any other flags missing.
> Code is obvious and looks fine to me.
Thanks. Pushed now.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-11-17 13:50 ` Alan Hayward via Gdb-patches
2021-11-17 13:57 ` Luis Machado via Gdb-patches
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