[PATCH] [AArch64] Expose the BTI BTYPE more explicitly in the registers

[Luis Machado via Gdb-patches <gdb-patches@sourceware.org>]

Augment the register description XML to expose the BTI BTYPE field contained
in the CPSR register. It will be displayed like so:

cpsr           0x60001000          [ EL=0 BTYPE=0 SSBS C Z ]
---
 gdb/features/aarch64-core.c   | 1 +
 gdb/features/aarch64-core.xml | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/gdb/features/aarch64-core.c b/gdb/features/aarch64-core.c
index a080a641c45..bb707173be6 100644
--- a/gdb/features/aarch64-core.c
+++ b/gdb/features/aarch64-core.c
@@ -18,6 +18,7 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
   tdesc_add_flag (type_with_fields, 7, "I");
   tdesc_add_flag (type_with_fields, 8, "A");
   tdesc_add_flag (type_with_fields, 9, "D");
+  tdesc_add_bitfield (type_with_fields, "BTYPE", 10, 11);
   tdesc_add_flag (type_with_fields, 12, "SSBS");
   tdesc_add_flag (type_with_fields, 20, "IL");
   tdesc_add_flag (type_with_fields, 21, "SS");
diff --git a/gdb/features/aarch64-core.xml b/gdb/features/aarch64-core.xml
index d63456956fd..a328ede508c 100644
--- a/gdb/features/aarch64-core.xml
+++ b/gdb/features/aarch64-core.xml
@@ -61,6 +61,9 @@
     <!-- Debug exception mask.  -->
     <field name="D" start="9" end="9"/>
 
+    <!-- ARMv8.5-A: Branch Target Identification BTYPE.  -->
+    <field name="BTYPE" start="10" end="11"/>
+
     <!-- ARMv8.0-A: Speculative Store Bypass.  -->
     <field name="SSBS" start="12" end="12"/>
 
-- 
2.25.1