* [patch] New Target - Fujitsu FRV
@ 2002-06-12 12:31 Dave Brolley
0 siblings, 0 replies; 7+ messages in thread
From: Dave Brolley @ 2002-06-12 12:31 UTC (permalink / raw)
To: gdb-patches
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Hi,
Attached is a patch which adds sim support for Fujitsu's FRV
architecture targeting frv-elf, including models for the FR400 and
FR500. This patch is part of a larger submission of bfd, gas, ld,
binutils, sim, gdb and newlib for the FRV by Red Hat.
The generated files will be included in a separate patch due to their size.
Seeking approval to commit.
Dave
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sim/ChangeLog:
2002-06-11 Dave Brolley <brolley@redhat.com>
* configure.in: Support frv-*-*.
* frv: New sim.
sim/common/ChangeLog:
2002-06-11 Dave Brolley <brolley@redhat.com>
* nltvals.def: Add frv syscalls.
* gennltvals.sh: Handle frv.
* cgen-par.h (CGEN_WRITE_QUEUE_ELEMENT): New members: flags, word1.
(CGEN_WRITE_QUEUE_ELEMENT_FLAGS): New macro.
(CGEN_WRITE_QUEUE_ELEMENT_WORD1): New macro.
sim/frv/ChangeLog:
2001-10-11 Dave Brolley <brolley@redhat.com>
* cpu.h,decode.c,decode.h,sem.c: Regenerate.
2001-10-09 Dave Brolley <brolley@redhat.com>
* traps.c (frv_rett): Hallt if PSR.S and PSR.ET are both set or both
not set.
* reset.c (frv_hardware_reset): Invalidate both caches.
* registers.c: Update init, reset and read-only masks for all registers
on all machines.
* profile.h (cur_gr_complex): New field of FRV_PROFILE_STATE
(prev_gr_complex): New field of FRV_PROFILE_STATE
(set_use_is_gr_complex): New function.
(set_use_not_gr_complex): New function.
(use_is_gr_complex): New function.
(decrease_GR_busy): New function.
* profile.c (reset_gr_flags): New function.
(reset_cc_flags): New function.
(set_use_is_gr_complex): New function.
(set_use_not_gr_complex): New function.
(use_is_gr_complex): New function.
(update_latencies): Reset gr and cc flags when latency reaches 0.
(decrease_GR_busy): New function.
* profile-fr400.h (fr500_reset_acc_flags): Removed.
(fr500_reset_cc_flags): New function.
* profile-fr500.c (frvbf_model_fr400_u_*): Reflect latencies from fr500
LSI version 1.41.
* profile-fr400.h (fr400_reset_gr_flags): New function.
(fr400_reset_fr_flags): New function.
(fr400_reset_acc_flags): New function.
* profile-fr400.c (set_use_not_media_p4): New function.
(set_use_not_media_p6): New function.
(set_acc_use_not_media_p2): New function.
(set_acc_use_not_media_p4): New function.
(fr400_reset_gr_flags): New function.
(fr400_reset_fr_flags): New function.
(fr400_reset_acc_flags): New function.
(frvbf_model_fr400_u_*): Reflect latencies from fr400 LSI version 1.1.
(frvbf_model_fr400_u_media_hilo): New function.
* pipeline.c (frv_vliw_setup_insn): Don't clear MSR0.MTT.
* memory.c (fr400_check_data_read_address): Check address range only
for double word loads. Don't check alignment here.
(fr400_check_readwrite_address): New function.
(fr500_check_readwrite_address): New function.
(check_readwrite_address): New function.
(fr500_check_insn_read_address): Correct address ranges.
(frvbf_read_mem_*): Check address range here.
(frv_address_forbidden): Removed.
(fr400_check_write_address): New function.
(check_write_address): New function.
(frvbf_write_mem_*): Don't check address range here.
(frvbf_mem_set_*): Check address range here.
* interrupts.c (frv_queue_data_access_error_interrupt): Now takes an
address as second argument.
(frv_queue_data_access_exception_interrupt): New function.
(frv_queue_illegal_instruction_interrupt): Generate fp_exception for
media insns on fr400.
(frv_queue_non_implemented_instruction_interrupt): Generate mp_exception
for media insns on fr400.
(frv_detect_insn_access_interrupts): Don't check for illegal addresses
of insns here. Check for MTRAP insn if PSR.EM is not set.
(frv_set_mp_exception_registers): Only set MSR0.MTT if it is not already
set.
(set_exception_status_registers): Do not always set EPCR. Set EAR for
data_acess_error only if not fr400.
* frv.c (do_media_average): New function.
(frvbf_media_average): New function.
(frvbf_insn_cache_invalidate): Check for illegal invocation.
(frvbf_data_cache_invalidate): Ditto.
(frvbf_data_cache_flush): Ditto.
* frv-sim.h (GET_FSR_QNE): New macro.
(frv_msr_mtt): Remove MTT_SEQUENCE_ERROR.
(GET_MSR_SRDAV): New macro.
(GET_MSR_RDAV): New macro.
(GET_MSR_RD): New macro.
(frv_queue_data_access_error_interrupt): Now takes an address as second
argument.
(frv_address_forbidden): Removed.
* cache.c (non_cache_access): Correct address ranges. Now takes cache
as first argument.
* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
2001-08-20 Dave Brolley <brolley@redhat.com>
* sim-main.h (_sim_cpu): New field 'elf_flags'.
* sim-if.c (sim_open): Extract the elf_flags from the input file and
save them with each cpu.
* mloop.in (main loop): Pass elf flags to frv_vliw_reset. Set
last_insn_p before executing the insn.
* cache.c (frv_cache_invalidate): Flush scache if this is the cpu's
insn cache.
(frv_cache_invalidate_all): Ditto.
2001-08-20 Richard Sandiford <rsandifo@redhat.com>
* traps.c (syscall_read_mem): Flush the data cache before reading.
(syscall_write_mem): Flush the data cache before writing.
Invalidate both caches.
2001-07-05 Ben Elliston <bje@redhat.com>
* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
(stamp-cpu): Likewise.
2001-05-23 Dave Brolley <brolley@redhat.com>
* profile-fr400.c (acc_use_is_media_p2): New function.
(frvbf_model_fr400_u_media_2): Account for latency of output
accumulators.
(frvbf_model_fr400_u_media_2_quad): Ditto.
(frvbf_model_fr400_u_media_2_acc): New function.
(frvbf_model_fr400_u_media_2_acc_dual): New function.
(frvbf_model_fr400_u_media_2_add_sub): New function.
(frvbf_model_fr400_u_media_2_add_sub_dual): New function.
(frvbf_model_fr400_u_media_3_dual): New function.
(frvbf_model_fr400_u_media_4_acc_dual): New function.
* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
2001-05-15 Dave Brolley <brolley@redhat.com>
* registers.c (fr400_spr): Enable write access to HSR0.CBM.
* profile.h (FRV_PROFILE_STATE): New field 'all_cache_entries'.
* profile.c (CACHE_QUEUE_ELEMENT): New 'all' field.
(request_cache_flush): Save 'all' argument.
(request_cache_invalidate): Save all_cache_entries from profile state
to 'all' field of the request.
(submit_cache_request): Pass the 'all' field of the request to
frv_cache_request_invalidate.
* frv.c (frv_insn_cache_invalidate): Add new 'all' parameter. Perform
operation even if HSR0.ICE is not set.
(frv_data_cache_invalidate): Add new 'all' parameter. Perform
operation even if HSR0.DCE is not set.
(frv_data_cache_flush): Ditto.
* frv-sim.h (frv_insn_cache_invalidate): Add new 'all' parameter.
(frv_data_cache_invalidate): Add new 'all' parameter.
(frv_data_cache_flush): Add new 'all' parameter.
* cache.h (FRV_CACHE_INVALIDATE_REQUEST): Add new 'all' field.
(frv_cache_request_invalidate): Add new 'all' parameter.
* cache.c (frv_cache_request_invalidate): Add new 'all' parameter. Save
its value in the invalidate request.
(address_interference): Accept the value '-1' for the address argument
to mean 'any address'.
(handle_req_invalidate): Handle request to invalidate all cache lines.
* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
2001-05-14 Dave Brolley <brolley@redhat.com>
* profile.h (past_first_p): New field of profiling state.
(branch_penalty): Ditto.
(branch_hint): Ditto.
(update_branch_penalty): New function.
* profile.c (frvbf_model_insn_after): Reset past_first_p and
branch_address fields of the profiling state.
(frvbf_model_branch): New function.
(update_branch_penalty): New function.
* profile-fr500.c (frvbf_model_fr500_u_branch): Remove ICCi_3 and
FCCi_3 inputs.
(frvbf_model_fr500_u_trap): New function.
(frvbf_model_fr500_u_check): New function.
(frvbf_model_fr500_u_media_dual_htob): post-processing latency is 3
cycles.
* profile-fr400.c (frvbf_model_fr400_u_branch): Set branch penalties
as documented in the fr400 LSI. Remove ICCi_3 and FCCi_3 inputs.
(frvbf_model_fr400_u_media_dual_expand): Check resource usage as
documented in teh fr400 LSI.
(frvbf_model_fr400_u_media_dual_htob): Ditto.
(frvbf_model_fr400_u_media_dual_unpack): Removed.
(frvbf_model_fr500_u_trap): New function.
(frvbf_model_fr500_u_check): New function.
* mloop.in (simulate_dual_insn_prefetch): New function.
(@cpu@_simulate_insn_prefetch): Call simulate_dual_insn_prefetch with
arguments for each machine type.
* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
2001-05-09 Dave Brolley <brolley@redhat.com>
* Makefile.in (profile.o): Add profile-fr400.h as a dependency.
(profile-fr400.o): New target.
* profile.c: New file.
* profile.h: New file.
* profile-fr400.c: New file.
* profile-fr400.h: New file.
* profile-fr500.c: New file.
* profile-fr500.h: New file.
* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
2001-05-02 Dave Brolley <brolley@redhat.com>
* sim-main.h (profile.h): #include it.
(CPU_PROFILE_STATE): New macro.
(profile_state): New frv specific cpu field.
* reset.c (frv_initialize): insn_fetch_address and branch_address now
part of global profiling state.
* Makefile.in (SIM_OBJS): Add profile.o and profile-fr500.o.
(SIM_EXTRA_DEPS): Add profile.h.
(registers.o): Correct name of source file.
(profile.o): New target.
(profile-fr500.o): New target.
* frv-sim.h: Move profile related data structures to profile.h.
* frv.c: Move fr500 specific functions to profile-fr500.c.
* cpu.h: Regenerated.
2001-04-27 Dave Brolley <brolley@redhat.com>
* sim-main.h (CPU_PIPELINE): Renamed to CPU_VLIW.
* interrupts.c: Rename FRV_PIPELINE to FRV_VLIW.
Rename pipeline to vliw. Rename CPU_PIPELINE to CPU_VLIW.
Rename PIPE_* to UNIT_*.
(frv_queue_illegal_instruction_interrupt): Use
frv_is_float_insn and frv_is_media_insn.
(frv_queue_non_implemented_instruction_interrupt): Ditto.
(frv_detect_insn_access_interrupts): Ditto.
* frv.c: Rename FRV_PIPELINE to FRV_VLIW. Rename pipeline to vliw.
Rename CPU_PIPELINE to CPU_VLIW. Rename PIPE_* to UNIT_*.
* memory.c: Ditto.
* pipeline.c: Ditto.
* mloop.in: Ditto.
* frv-sim.h (frv_pipeline_setup_insn): Renamed to frv_vliw_setup_insn.
* cache.c: Rename PIPE_* to UNIT_*.
2001-04-24 Dave Brolley <brolley@redhat.com>
* frv.c (frvbf_load_quad_GR): Delete have_data and hsr0.
(frvbf_load_quad_FRint): Ditto.
(frvbf_load_quad_CPR): Ditto.
* cache.c (frv_cache_init): Initialize cache for fr400 vs other
machines.
(bfd.h): #include it.
(non_cache_access): Update for revised fr500 and for fr400.
* registers.c (frv_spr): Don't reset PSR.PS.
(fr500_spr): Ditto.
(frv_reset_spr): Set PSR.PS to the former value of PSR.S.
2001-04-23 Dave Brolley <brolley@redhat.com>
* traps.c (frv_core_signal): On fr400, generate data_access_error.
(frvbf_media_cr_not_aligned): On fr400, generate illegal_instruction.
(frvbf_media_acc_not_aligned): Ditto.
(frvbf_media_register_not_aligned): Ditto.
(frvbf_division_exception): Use GET_ISR_EDE.
* registers.c (frv_check_spr_read_access): New function.
(frv_check_spr_write_access): New function.
(frv_check_spr_access): Deleted.
(frv_check_register_access): On fr400, generate illegal_instruction.
* memory.c (fr400_check_data_read_address): New function.
(fr500_check_data_read_address): Ditto.
(check_data_read_address): Ditto.
(fr400_check_insn_read_address): Ditto.
(fr500_check_insn_read_address): Ditto.
(check_insn_read_address): Ditto.
(frvbf_read_mem_QI): Call check_data_read_access.
(frvbf_read_mem_UQI): Ditto.
(frvbf_read_mem_HI): Ditto.
(frvbf_read_mem_UHI): Ditto.
(frvbf_read_mem_SI): Ditto.
(frvbf_read_mem_DI): Ditto.
(frvbf_read_mem_DF): Ditto.
(frvbf_read_imem_USI): Call check_insn_read_access.
(frv_address_forbidden): Now takes cpu as first argument. Check based
on machine type.
(fr400_mem_address_unaligned): New function.
(fr500_mem_address_unaligned): Ditto.
(check_write_address): Ditto.
(frvbf_mem_set_QI): Call check_write_address.
(frvbf_mem_set_HI): Ditto.
(frvbf_mem_set_SI): Ditto.
(frvbf_mem_set_DI): Ditto.
(frvbf_mem_set_DF): Ditto.
(frvbf_mem_set_XI): Ditto.
* interrupts.c (bfd.h): #include it.
(frv_queue_data_access_error_interrupt): New function.
(frv_queue_instruction_access_error_interrupt): New function.
(frv_queue_instruction_access_exception_interrupt): New function.
(frv_queue_illegal_instruction_interrupt): No fp_exception on fr400.
(frv_queue_non_implemented_instruction_interrupt): Ditto.
(frv_detect_insn_access_interrupts): Reorder tests to match priority
from the LSI manual.
(set_isr_exception_fields): Accumulate dtt bits.
* frv.c (check_register_alignment): New function.
(check_fr_register_alignment): New function.
(check_memory_alignment): New function.
(frvbf_h_gr_double_get_handler): Call check_register_alignment.
(frvbf_h_gr_double_set_handler): Ditto.
(frvbf_h_cpr_double_get_handler): Ditto.
(frvbf_h_cpr_double_set_handler): Ditto.
(frvbf_h_gr_quad_set_handler): Ditto.
(frvbf_h_cpr_quad_set_handler): Ditto.
(frvbf_h_fr_double_get_handler): Call check_fr_register_alignment.
(frvbf_h_fr_double_set_handler): Ditto.
(frvbf_h_fr_quad_set_handler): Ditto.
(frvbf_h_spr_get_handler): Call frv_check_spr_read_access.
(frvbf_h_spr_set_handler): Call frv_check_spr_write_access.
(frvbf_load_quad_GR): Call check_memory_aligment.
(frvbf_load_quad_FRint): Ditto.
(frvbf_load_quad_CPR): Ditto.
(frvbf_store_quad_GR): Call check_memory_aligment and
check_register_alignment.
(frvbf_store_quad_FRint): Ditto.
(frvbf_store_quad_CPR): Ditto.
(frvbf_signed_integer_divide: Use GET_ISR_EDEM.
* frv-sim.h (H_SPR_ACC0): New macro.
(H_SPR_ACC63): New macro.
(H_SPR_ACCG0): New macro.
(H_SPR_ACCG63): New macro.
(frv_dtt): New enumerator.
(GET_ISR_EDE): Renamed from GET_ISR_EDEM.
(GET_ISR_DTT): New macro.
(frv_queue_data_access_error_interrupt): New function.
(frv_queue_instruction_access_error_interrupt): New function.
(frv_queue_instruction_access_exception_interrupt): New function.
(frv_address_forbidden): Now takes cpu as first argument.
* cpu.h: Regenerate.
2001-04-10 Dave Brolley <brolley@redhat.com>
* registers.c (fr500_spr): Add new fields to fr500 PSR register.
(fr500_spr): Add STBAR and MMCR unimplemented registers for fr500.
(fr400_spr): Implement SPR registers for fr400.
(frv_register_control_init): Handle bfd_mach_fr400 properly.
* frv.c (spr_bpsr_get_handler): Mask field before shifting.
(spr_psr_get_handler): Ditto.
(spr_ccr_get_handler): Ditto.
(spr_cccr_get_handler): Ditto.
(frvbf_clear_accumulators): Only 4 accumulators on fr400.
* frv-sim.h: Update comment about MCCR_* macros.
* cpu.c,cpu.h: Regenerate.
2001-04-05 Dave Brolley <brolley@redhat.com>
* cpu.h,decode.c,model.c,sem.c: Regenerate.
2001-04-05 Dave Brolley <brolley@redhat.com>
* reset.c: Update copyright.
* registers.c (frv_register_control_init): Handle bfd_mach_fr400.
* frv.c (frvbf_model_fr400_u_exec): New function.
* Makefile.in (stamp-cpu): Add fr400 to list of machines.
* arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
Regenerate.
2000-11-22 Dave Brolley <brolley@redhat.com>
* arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
Regenerate.
2000-11-10 Dave Brolley <brolley@redhat.com>
* decode.c: Regenerate.
2000-09-12 Dave Brolley <brolley@redhat.com>
* traps.c (frv_sim_engine_halt_hook): New function.
(frv_itrap): Caches now invalidated in sim_engine_halt via
SIM_ENGINE_HALT_HOOK.
(frv_break): Ditto.
* sim-main.h (frv_sim_engine_halt_hook): New function.
(SIM_ENGINE_HALT_HOOK): New macro.
(SIM_ENGINE_RESTART_HOOK): New macro.
* interrupts.c: Call to frv_term now done within sim_engine_halt via
SIM_ENGINE_HALT_HOOK.
2000-09-08 Dave Brolley <brolley@redhat.com>
* traps.c (frv_itrap): Invalidate and flush the data and insn caches
respectively when stopping for a breakpoint.
(frv_break): Ditto.
* cache.h (frv_cache_invalidate_all): New function.
* cache.c (frv_cache_invalidate_all): New function.
2000-09-05 Dave Brolley <brolley@redhat.com>
* traps.c (frv_break): If SIM_HAVE_BREAKPOINTS, call
sim_handle_breakpoint. Otherwise if environment != operating call
sim_engine_halt. Otherwise handle normally.
* interrupts.c (frv_queue_break_interrupt): Don't handle debugger
breakpoints here. Moved to frv_break in traps.c.
* sem.c: Regenerate.
2000-09-01 Dave Brolley <brolley@redhat.com>
* interrupts.c (frv_queue_break_interrupt): Call sim_handle_breakpoint
before queuing an interrupt in order to allow 'break' to be used as
the breakpoint insn.
2000-08-29 Dave Brolley <brolley@redhat.com>
* traps.c (frv_itrap): Invalidate the insn cache at a breakpoint.
2000-07-27 Dave Brolley <brolley@redhat.com>
* cpu.h,decode.c: Rebuild.
2000-07-26 Dave Brolley <brolley@redhat.com>
* frv.c (spr_cccr_get_handler): Change CRx to CCx.
(spr_cccr_set_handler): Change CRx to CCx.
* cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
2000-07-24 Dave Brolley <brolley@redhat.com>
* sem.c: Regenerate.
* frv.c (frvbf_unsigned_integer_divide): Queue a write for the result.
Don't write it directly.
Thu Jul 6 13:51:12 2000 Dave Brolley <brolley@topaz>
* configure: Regenerated to track ../common/aclocal.m4 changes.
2000-07-05 Ben Elliston <bje@redhat.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
2000-06-28 Dave Brolley <brolley@redhat.com>
* cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
2000-06-21 Dave Brolley <brolley@redhat.com>
* pipeline.c: All code except frv_pipeline_setup_insn moved to
frv.opc.
* mloop.in (main loop): frv_pipeline_add_insn broken up into
frv_pipeline_add_insn and frv_pipeline_setup_insn.
* frv-sim.h: Move pipeline status code to frv.opc.
* model.c: Regenerate.
2000-06-12 Dave Brolley <brolley@redhat.com>
* options.c (frv_option_handler): --profile-parallel implies
--profile-model.
* mloop.in (fetch_buffer): Removed.
(@cpu@_simulate_insn_prefetch): Monitoring of fetch buffer moved to
run_caches. Use cache directly if not counting cycles. Don't use
cache at all if not counting cycles and cache not enabled.
* frv.c (frv_insn_fetch_buffer): New global variable.
(run_caches): Monitor the status of insn prefetch requests.
* frv-sim.h (FRV_INSN_FETCH_BUFFER): New struct type.
(frv_insn_fetch_buffer): New global variable.
2000-06-12 Dave Brolley <brolley@redhat.com>
* mloop.in (fetch_buffer): New static struct.
(@cpu@_simulate_insn_prefetch): Rewritten.
* cache.c (frv_cache_request_invalidate): Don't invalidate return
buffer.
(address_interference): Defer to any WAR request in either pipeline.
2000-06-09 Dave Brolley <brolley@redhat.com>
* pipeline.c (insns_in_slot): New Array.
(frv_pipeline_add_insn): Call COUNT_INSNS_IN_SLOT.
* options.c (frv_options): Remove 'NONBLOCK' argument from data-cache
option.
(parse_cache_option): New function.
(frv_option_handler): Call parse_cache_option.
* frv.c (vliw_branch_taken): New variable.
(vliw_load_stall): New variable.
(handle_resource_wait): Update vliw_load_stall.
(frvbf_model_insn_before): Initialize vliw_branch_taken and
vliw_load_stall.
(frvbf_model_insn_after): Increment PROFILE_MODEL_LOAD_STALL_CYCLES.
(load_wait_for_FR): Update vliw_load_stall.
(load_wait_for_GR): Update vliw_load_stall.
(load_wait_for_FRdouble): Update vliw_load_stall.
(load_wait_for_GRdouble): Update vliw_load_stall.
(frvbf_model_fr500_u_branch): Count branches taken and not taken.
(slot_names): New static array.
(print_parallel): Now takes second argument 'verbose'. Print cycles per
VLIW insn and instructions per cycle. Also tabulate the number of insns
in each type of VLIW slot.
(frv_profile_info): Call print_parallel with new second argument.
* frv-sim.h (insn_in_slot): New array.
(COUNT_INSNS_IN_SLOT): New macro.
(INSNS_IN_SLOT): New macro.
* cache.c: Remove references to non_blocking_count. Remove references to
last_was_hit. Remove references to req_none.
(handle_req_store): Adjust statistics before requeuing the store
request.
(handle_req_WAR): Don't let the WAR request affect the cache statistics.
* cache.h: Remove references to non_blocking_count. Remove references to
last_was_hit. Remove references to req_none.
* model.c: Regenerate.
2000-06-08 Dave Brolley <brolley@redhat.com>
* frv.c (request_complete): Copy load data from the correct return
buffer.
2000-06-07 Dave Brolley <brolley@redhat.com>
* traps.c (frv_core_signal): Call frv_term before exiting.
(frv_itrap): Call frv_term before exiting.
(next_available_nesr): Make sure NECR is implemented before reading it.
(next_valid_nesr): Ditto.
(frvbf_check_non_excepting_load): Ditto.
(frvbf_clear_ne_flags): Ditto.
(frvbf_commit): Ditto.
(frvbf_check_recovering_store): Delay cache operation if 'model_insn'.
* sim-main.h (_sim_cpu): Add load_address, load_length, load_flag and
store_flag members.
(CPU_LOAD_ADDRESS): New macro.
(CPU_LOAD_LENGTH): New macro.
(CPU_LOAD_SIGNED): New macro.
(CPU_LOAD_LOCK): New macro.
* reset.c (frv_term): New function.
(frv_power_on_reset): Use SETMEMSI if the cache is not enabled.
(frv_hardware_reset): Use SETMEMSI if the cache is not enabled.
(frv_software_reset): Use SETMEMSI if the cache is not enabled.
* mloop.in (execute): Call FRV_COUNT_CYCLES to decide whether to model
the insn. Model the insn in two passes. One before and one after
execution.
(cache_reqno): new static variable.
(@cpu@_simulate_insn_prefetch): Model fetch latency by waiting for the
cache rather than assuming a fixed latency.
(xinit): Turn on PROFILE_MODEL_P before each vliw insn if the timer is
enabled so that modeling data is collected by cgen during execution.
(full-exec): Restore PROFILE_MODEL_P after each vliw insn.
* memory.c (data_non_cache_access): Removed.
(insn_non_cache_access): Removed.
(frvbf_read_mem_QI): Delay read operation if 'model_insn'.
(frvbf_read_mem_UQI): Delay read operation if 'model_insn'.
(frvbf_read_mem_HI): Delay read operation if 'model_insn'.
(frvbf_read_mem_UHI): Delay read operation if 'model_insn'.
(frvbf_read_mem_SI): Delay read operation if 'model_insn'.
(frvbf_read_mem_DI): Delay read operation if 'model_insn'.
(frvbf_read_mem_DF): Delay read operation if 'model_insn'.
(frvbf_read_imem_USI): Read the cache or ememory passively.
(frvbf_write_mem_QI): Don't check for non-cache access here.
(frvbf_write_mem_UQI): Call frvbf_write_mem_QI.
(frvbf_write_mem_HI): Don't check for non-cache access here.
(frvbf_write_mem_UHI): Call frvbf_write_mem_QI.
(frvbf_write_mem_SI): Don't check for non-cache access here.
(frvbf_write_mem_DI): Don't check for non-cache access here.
(frvbf_write_mem_DF): Don't check for non-cache access here.
(frvbf_mem_set_QI): Use cycle-accurate cache write if 'model_insn'.
(frvbf_mem_set_HI): Use cycle-accurate cache write if 'model_insn'.
(frvbf_mem_set_SI): Use cycle-accurate cache write if 'model_insn'.
(frvbf_mem_set_DI): Use cycle-accurate cache write if 'model_insn'.
(frvbf_mem_set_DF): Use cycle-accurate cache write if 'model_insn'.
(frvbf_mem_set_XI): Use cycle-accurate cache write if 'model_insn'.
* interrupts.c (check_reset): Read the cache and memory passively.
(frv_program_or_software_interrupt): Call frv_term before calling
sim_engine_halt.
* frv.c (all modeling functions): Break into two passes. One before
execuetion and one after. call load_wait_for_* for all GR and FR
registers.
(frvbf_load_quad_GR): Delay performing the load if 'model_insn'.
(frvbf_load_quad_FRint): Delay performing the load if 'model_insn'.
(frvbf_load_quad_CPR): Delay performing the load if 'model_insn'.
(frvbf_insn_cache_preload): Delay cache operation if 'model_insn'.
(frvbf_data_cache_preload): Delay cache operation if 'model_insn'.
(frvbf_insn_cache_unlock): Delay cache operation if 'model_insn'.
(frvbf_data_cache_unlock): Delay cache operation if 'model_insn'.
(frvbf_insn_cache_invalidate): Delay cache operation if 'model_insn'.
(frvbf_data_cache_invalidate): Delay cache operation if 'model_insn'.
(frvbf_data_cache_flush): Delay cache operation if 'model_insn'.
(model_insn): New global variable.
(fr_ptime): New array.
(cache_request): New enumeration.
(CACHE_QUEUE_ELEMENT): New struct type.
(CACHE_QUEUE_SIZE): New macro.
(cache_queue): New static struct.
(request_cache_load): New function.
(request_cache_flush): New function.
(request_cache_invalidate): New function.
(request_cache_preload): New function.
(request_cache_unlock): New function.
(submit_cache_request): New function.
(activate_cache_requests): New function.
(load_pending_for_register): New function.
(flush_pending_for_address): New function.
(remove_cache_queue_element): New function.
(copy_load_data): New function.
(request_complete): New function.
(run_caches): New function.
(frv_model_trace_wait_cycles): New function.
(wait_for_flush): New function.
(frvbf_model_insn_before): Insn prefect wait now modeled in
frvbf_simulate_insn_prefetch. Incremement vliw_insns here. Call
wait_for_flush.
(frvbf_model_insn_after): Call activate_cache_requests. Don't increment
vliw_insns here anymore.
(update_FR_latency_for_load): New function.
(update_FRdouble_latency_for_load): New function.
(update_FR_ptime): New function.
(update_FRdouble_ptime): New function.
(update_GR_latency_for_swap): New function.
(load_wait_for_GR): New function.
(load_wait_for_FR): New function.
(load_wait_for_GRdouble): New function.
(load_wait_for_FRdouble): New function.
(frvbf_model_fr500_u_ici): New function.
(frvbf_model_fr500_u_dci): New function.
(frvbf_model_fr500_u_dcf): New function.
(frvbf_model_fr500_u_icpl): New function.
(frvbf_model_fr500_u_dcpl): New function.
(frvbf_model_fr500_u_icul): New function.
(frvbf_model_fr500_u_dcul): New function.
* frv-sim.h (frv_term): New function.
(insn_non_cache_access): Removed.
(FRV_COUNT_CYCLES): New macro.
(frv_save_peofile_model_p): New global variable.
(model_insn): New enumerated global variable.
(frv_model_advance_cycles): New function.
(frv_model_trace_wait_cycles): New function.
* cache.h (FRV_CACHE_REQUEST_KIND): New enumeration.
(FRV_CACHE_WAR_REQUEST): New struct type.
(FRV_CACHE_STORE_REQUEST): New struct type.
(FRV_CACHE_INVALIDATE_REQUEST): New struct type.
(FRV_CACHE_PRELOAD_REQUEST): New struct type.
(FRV_CACHE_REQUEST): New struct type.
(FRV_CACHE_RETURN_BUFFER): New struct type.
(FRV_CACHE_FLUSH_STATUS): New struct type.
(FRV_CACHE_STATUS): New struct type.
(FRV_CACHE_STAGE): New struct type.
(FRV_CACHE_STAGES): New enumeration.
(FRV_CACHE_WAR): New struct type.
(FRV_CACHE_PIPELINE): New struct type.
(FRV_CACHE_ARS): New struct type.
(FRV_CACHE_STATISTICS): New struct type.
(FRV_CACHE): Add pipeline, statistics, BARS and NARS.
(CACHE_RETURN_DATA): 'return_buffer' is now within 'status'.
(CACHE_RETURN_DATA_ADDRESS): New macro.
(frv_cache_read): Now takes pipe index as second argument.
(frv_cache_enabled): New function.
(frv_cache_request_load): New function.
(frv_cache_request_store): New function.
(frv_cache_request_invalidate): New function.
(frv_cache_request_preload): New function.
(frv_cache_request_unlock): New function.
(frv_cache_run): New function.
(frv_cache_read_passive_SI): New function.
(frv_cache_data_in_buffer): New function.
(frv_cache_data_flushed): New function.
* cache.c (frv_cache_init): Initialize pipelines and xARS registers.
(frv_cache_enabled): New function.
(non_cache_access): New function.
(write_data_to_memory): Count write accesses for each mode. Write to
memory using sim_core_write_unaligned_1;
(read_data_from_memory): New function.
(fill_line_from_memory): Use read_data_from_memory.
(copy_line_to_return_buffer): New function.
(copy_memory_to_return_buffer): New function.
(set_return_buffer_reqno): New function.
(frv_cache_read): Now takes pipe index as second argument. Check for
non-cache access.
(frv_cache_preload): Check for non-cache access.
(frv_cache_unlock): Check for non-cache access.
(invalidate_return_buffer): New function.
(frv_cache_invalidate): Check for non-cache access.
(convert_slot_to_index): New function.
(FREE_CHAIN_SIZE): New macro.
(frv_cache_request_free_chain): New static variable.
(frv_store_request_free_chain): New static variable.
(allocate_new_cache_requests): New function.
(new_cache_request): New function.
(free_cache_request): New function.
(new_store_request): New function.
(pipeline_remove_request): New function.
(pipeline_add_request): New function.
(pipeline_requeue_request): New function.
(next_priority): New function.
(add_WAR_request): New function.
(pipeline_next_request): New function.
(pipeline_stage_request): New function.
(advance_pipelines): New function.
(frv_cache_request_load): New function.
(frv_cache_request_store): New function.
(frv_cache_request_invalidate): New function.
(frv_cache_request_preload): New function.
(frv_cache_request_unlock): New function.
(address_interference): New function.
(wait_for_WAR): New function.
(wait_in_WAR): New function.
(handle_req_load): New function.
(handle_req_preload): New function.
(handle_req_store): New function.
(handle_req_invalidate): New function.
(handle_req_unlock): New function.
(handle_req_WAR): New function.
(arbitrate_requests): New function.
(move_ARS_to_WAR): New function.
(decrease_latencies): New function.
(frv_cache_run): New function.
(frv_cache_read_passive_SI): New function.
(frv_cache_data_in_buffer): New function.
(frv_cache_data_flushed): New function.
* arch.h,decode.c,decode.h,model.c,sem.c: Rebuild.
Wed May 24 14:40:34 2000 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
2000-05-19 Dave Brolley <brolley@redhat.com>
* traps.c (frv_rett): Check for exceptions in the order specified in the
architecture spec. Allow privileged_instruction interrrupt to be handled
normally.
* registers.c (frv_register_control_init): Handle bfd_mach_frvtomcat.
* frv.c (frvbf_signed_integer_divide): Use updated dtt to decide whether
to clear the NE flag.
(frvbf_model_tomcat_u_exec): New function.
* frv-sim.h (frvbf_division_exception): Now returns updated dtt.
* Makefile.in (stamp-cpu): Add 'tomcat' to 'mach' value.
* arch.c,arch.h,cpu.h,cpuall.h,model.h,decode.c,sem.c: Regenerate.
2000-05-18 Dave Brolley <brolley@redhat.com>
* sim-if.c (elf-bfd.h): #include it.
(sim_open): Set machine amd architecture based on elf flags.
2000-04-04 Dave Brolley <brolley@redhat.com>
* frv-sim.h (frv_h_psr_esr_set_handler): Removed.
Delete '#if 0' blocks.
* frv.c: Delete '#if 0' blocks.
(spr_psr_set_handler): Remove special handling for circular referencing of handlers for
PSR.S and PSR.ESR.
(frv_h_psr_esr_set_handler): Removed.
* interrupts.c: Delete '#if 0' blocks.
* memory.c: Delete '#if 0' blocks.
* cpu.c,cpu.h: Regenerate.
2000-04-03 Dave Brolley <brolley@redhat.com>
* traps.c (frvbf_check_recovering_store): Invalidate data cache line
containing the target address.
(clear_nesr_neear): No longer takes hi_available and lo_available.
Remove bogus check for available GR registers.
(frvbf_clear_ne_flags): Update call to clear_nesr_neear.
(frvbf_commit): Update call to clear_nesr_neear.
* interrupts.c (next_available_esr): Removed.
(next_available_edr): Removed.
(next_available_fq): Removed.
* frv.c (frvbf_fetch_register): Remove "FIXME" comment.
(frvbf_store_register): Remove "FIXME" comment.
* frv-sim.h (UART_INCHAR_ADDR): Removed.
(UART_OUTCHAR_ADDR): Removed.
(UART_STATUS_ADDR): Removed.
(UART_INPUT_READY): Removed.
(UART_OUTPUT_READY): Removed.
(FRV_DEVICE_ADDR): Removed.
(FRV_DEVICE_LEN): Removed.
(SET_NESR): Call frvbf_force_update.
(SET_NEEAR): Call frvbf_force_update.
(SET_NE_FLAGS): Call frvbf_force_update.
2000-03-30 Dave Brolley <brolley@redhat.com>
* configure: Regenerated.
2000-03-30 Dave Brolley <brolley@redhat.com>
* registers.c (fr500_spr): Define ESR14-15 and EPCSR14-15 for fr500.
* memory.c (frvbf_write_mem_*): Save slot containing the insn
performing the write.
(frvbf_mem_set_*): Overwrite the slot information of the interrupt
queue element with the information in the interrupt state.
* interrupts.c (frv_queue_interrupt): Call frv_set_interrupt_queue_slot.
(frv_queue_fp_exception_interrupt): Initialize 'new_element'.
(frv_set_interrupt_queue_slot): New function.
(esr_for_data_access_exception): New function.
(set_edr_register): edr_index is now passed in.
(fq_for_exception): New function.
(set_fp_exception_registers): Call fq_for_exception. Interrupt queue
element now passed in.
(set_exception_status_registers): Obtain slot from interrupt queue
element. Call esr_for_data_access_exception. Use ESR14
for data_store_error. Use ESR15 for data_access_error. Use EDR0.
(frv_save_data_written_for_interrupts): Save slot containing the insn
performing the write.
* frv-sim.h (struct frv_fp_exception_info): Use frv_fsr_traps and
frv_fsr_ftt.
(struct frv_interrupt_state): Add 'slot' field.
(frv_set_interrupt_queue_slot): New function.
(frv_set_write_queue_slot): New function.
2000-03-24 Dave Brolley <brolley@redhat.com>
* mloop.in (_parallel_write_init): Initialize
frv_interrupt_state.imprecise_interrupt.
(_parallel_write_queued): After an imprecise interrupt, only perform
forced writes and floating point writes (for certain exceptions).
* interrupts.c (handle_interrupt): Set
frv_interrupt_state.imprecise_interrupt for writeback after an imprecise
interrupt.
(frv_process_interrupts): No need to clear f_ne_flags.
* frv.c (frvbf_signed_integer_divide): Queue writes to GR registers and
force them to happen even if there is an overflow exception.
(frvbf_force_update): New function.
* frv-sim.h (frvbf_force_update): New function.
(struct frv_interrupt_state): Add imprecise_interrupt.
(FRV_WRITE_QUEUE_FORCE_WRITE): New macro.
* sem.c: Regenerate.
2000-03-23 Dave Brolley <brolley@redhat.com>
* traps.c (frv_rett): Queue FRV_ILLEGAL_INSTRUCTION directly.
* registers.c (frv_spr): MCIRL -> MCILR.
* interrupts.c (frv_queue_non_implemented_instruction_interrupt):
New function.
(frv_detect_insn_access_interrupts):
Call frv_queue_non_implemented_instruction_interrupt.
(frv_process_interrupts): Clear accumulated NE flags.
* frv.c (frvbf_media_cop): New function.
(frvbf_set_ne_index): Now takes (SIM_CPU *) as first argument. Clear
the NE flag of the given target register.
(frvbf_model_fr500_u_float_arith): Account for FRdouble registers.
(frvbf_model_fr500_u_float_dual_arith): Account for FRdouble registers.
(frvbf_model_fr500_u_float_dual_sqrt): New function.
(frvbf_model_fr500_u_float_convert): Account for FRdouble registers.
(frvbf_model_fr500_u_float_dual_convert): New function.
* frv-sim.h (frvbf_media_cop): New function.
(GET_FQ): Use H_SPR_FQST0.
(SET_FQ): Use H_SPR_FQST0.
(SET_FQ_OPC): Use J_SPR_FQOP0.
(GET_MSR_EMCI): New macro.
(frv_queue_non_implemented_instruction_interrupt): New function.
* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
2000-03-08 Dave Brolley <brolley@redhat.com>
* traps.c (frv_rett): Align new_pc.
* memory.c (frvbf_read_mem_HI): Align address.
(frvbf_read_mem_UHI): Align address.
(frvbf_read_mem_SI): Align address.
(frvbf_read_mem_DI): Align address.
(frvbf_read_mem_DF): Align address.
(frvbf_read_imem_USI): Align address.
(frvbf_mem_set_HI): Align address.
(frvbf_mem_set_SI): Align address.
(frvbf_mem_set_DI): Align address.
(frvbf_mem_set_DF): Align address.
(frvbf_mem_set_XI): Align address.
* registers.c (frv_spr): Initialize FSR0.NS to 1.
(fr500_spr): Initialize FSR0.NS to 1.
* interrupts.c (frv_queue_mem_address_not_aligned_interrupt): Check
whether the exception is masked.
* frv.c (frvbf_load_quad_GR): Align address.
(frvbf_store_quad_GR): Align address.
(frvbf_load_quad_FRint): Align address.
(frvbf_store_quad_FRint): Align address.
(frvbf_load_quad_CPR): Align address.
(frvbf_store_quad_CPR): Align address.
* frv-sim.h (GET_ISR_EMAM): New macro.
2000-03-08 Dave Brolley <brolley@redhat.com>
* traps.c (frvbf_division_exception): Check for masked overflow and
set NE flags, if necessary.
(frvbf_check_recovering_store): Queue writes to the hardware.
(check_registers_available): Removed.
(which_registers_available): Call frv_{fr,gr}_registers_available.
(frvbf_clear_ne_flags): Call check_register_access.
(frvbf_commit): Call check_register_access.
* registers.h (frv_fr_registers_available): New function.
(frv_gr_registers_available): New function.
(frv_check_register_access): New function.
(frv_check_gr_access): New function.
(frv_check_fr_access): New function.
* registers.c (frv_spr): Correct initial value of ISR.
(fr500_spr): Correct initial value of ISR.
(frv_fr_registers_available): New function.
(frv_gr_registers_available): New function.
(frv_check_register_access): New function.
(frv_check_gr_access): New function.
(frv_check_fr_access): New function.
* interrupts.c (frv_queue_division_exception_interrupt): New function.
(set_isr_exception_fields): New function.
(set_exception_status_registers): Set ISR fields for division exception.
(frv_save_data_written_for_interrupts): Handle CGEN_FN_SF_WRITE.
* frv.c (frvbf_h_gr_get_handler): New function.
(frvbf_h_gr_set_handler): New function.
(frvbf_h_fr_get_handler): New function.
(frvbf_h_fr_set_handler): New function.
(frvbf_h_spr_get_handler): Remove special handling for ISR.
(frvbf_h_spr_set_handler): Remove special handling for ISR.
(spr_isr_get_handler): Removed.
(spr_isr_set_handler): Removed.
(frvbf_signed_integer_divide): New funciton.
(frvbf_unsigned_integer_divide): New funciton.
* frv-sim.h (frvbf_h_gr_get_handler): New function.
(frvbf_h_gr_set_handler): New function.
(frvbf_h_fr_get_handler): New function.
(frvbf_h_fr_set_handler): New function.
(frvbf_signed_integer_divide): New funciton.
(frvbf_unsigned_integer_divide): New funciton.
(frv_dtt): New enumeration.
(struct frv_interrupt_queue_element): Add dtt member.
(GET_ISR): New macro.
(SET_ISR): New macro.
(GET_ISR_EDEM): New macro.
(SET_ISR_DTT): New macro.
(SET_ISR_AEXC): New macro.
(frvbf_division_exception): Add 2 'int' arguments.
(frvbf_check_non_excepting_divide): Removed.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
2000-02-29 Dave Brolley <brolley@redhat.com>
* traps.c (frv_itrap): Use GET_H_GR, SET_H_GR, GET_H_FR.
(frv_rett): Use hardware access macros. Write PSR as a whole.
(next_available_nesr): Check that NECR is valid.
(next_valid_nesr): Check that NECR is valid.
(frvbf_check_non_excepting_load): User new NECR access macros. Don't
call hardware access functions. Use cover macros.
(check_registers_available): New function.
(clear_nesr_near): Check register availability.
(clear_ne_flags): Check register availability.
(frvbf_clear_ne_flags): Check register availability.
(frvbf_commit): Check register availability.
(which_registers_available): New function.
* sim-main.h (registers.h): #include it.
(register_control): New cpu field.
(CPU_REGISTER_CONTROL): New macro.
* reset.c (frv_initialize): Set HSR0 fields for cache here.
(frv_power_on_reset): Initialize SPR registers and RSTR.
(frv_hardware_reset): Initialize SPR registers and RSTR.
(frv_software_reset): Reset SPR registers and RSTR.
* options.c (frv_option_handler): Don't set HSR0 fields for cache here.
Call frv_cache_init.
* mloop.in (main loop): Check for insn access interrupts before
executing the insn.
* interrupts.c (frv_queue_external_interrupt): Use GET_H_PSR_ET.
(frv_detect_insn_access_interrupts): Don't call hardware access
functions directly. Use cover macros.
(check_reset): Don't reset RSTR here.
(next_available_esr): ESFR -> ESFR_FLAG.
(next_available_edr): ESFR -> ESFR_FLAG.
(clear_exception_status_registers): Use GET_ESFR and SET_ESFR.
ESFR -> ESFR_FLAG.
(frv_break_interrupt): Don't call hardware access functions directly.
Use cover macros.
(frv_program_or_software_interrupt): Ditto.
(frv_external_interrupt): Ditto.
* frv.c (frvbf_fetch_register): Don't call 'get' functions directly.
(frvbf_store_register): Don't call 'set' functions directly.
(frvbf_h_gr_double_get_handler): Use GET_H_GR.
(frvbf_h_gr_double_set_handler): Use SET_H_GR.
(frvbf_h_fr_double_get_handler): Use GET_H_FR.
(frvbf_h_fr_double_set_handler): Use SET_H_FR.
(frvbf_h_fr_int_get_handler): Use GET_H_FR.
(frvbf_h_fr_int_set_handler): Use SET_H_FR.
(frvbf_h_cpr_double_get_handler): Use GET_H_CPR.
(frvbf_h_cpr_double_set_handler): Use SET_H_CPR.
(frvbf_h_gr_quad_set_handler): Use SET_H_GR.
(frvbf_h_fr_quad_set_handler): Use SET_H_FR.
(frvbf_h_spr_get_handler): Check SPR access. Call renamed functions.
Support shadow registers.
(frvbf_h_spr_set_handler): Check SPR access. Call renamed functions.
Support shadow registers.
(spr_psr_get_handler): Renamed from frvbf_h_psr_get_handler.
(spr_psr_set_handler): Renamed from frvbf_h_psr_set_handler.
(spr_tbr_get_handler): Renamed from frvbf_h_tbr_get_handler.
(spr_tbr_set_handler): Renamed from frvbf_h_tbr_set_handler.
(spr_bpsr_get_handler): Renamed from frvbf_h_bpsr_get_handler.
(spr_bpsr_set_handler): Renamed from frvbf_h_bpsr_set_handler.
(spr_ccr_get_handler): Renamed from frvbf_h_ccr_get_handler.
(spr_ccr_set_handler): Renamed from frvbf_h_ccr_set_handler.
(spr_lr_get_handler): Renamed from frvbf_h_lr_get_handler.
(spr_lr_set_handler): Renamed from frvbf_h_lr_set_handler.
(spr_cccr_get_handler): Renamed from frvbf_h_cccr_get_handler.
(spr_cccr_set_handler): Renamed from frvbf_h_cccr_set_handler.
(spr_isr_get_handler): Renamed from frvbf_h_isr_get_handler.
(spr_isr_set_handler): Renamed from frvbf_h_isr_set_handler.
(spr_sr_get_handler): Renamed from frvbf_h_sr_get_handler.
(spr_sr_set_handler): Renamed from frvbf_h_sr_set_handler.
(frvbf_h_psr_esr_set_handler): Update to conform to FRV architecture
version 1.3a.
(spr_ccr_get_handler): Don't reference the hardware directly.
(spr_ccr_set_handler): Don't reference the hardware directly.
(spr_cccr_get_handler): Don't reference the hardware directly.
(spr_cccr_set_handler): Don't reference the hardware directly.
(spr_sr_get_handler): New function.
(spr_sr_set_handler): New function.
(frvbf_switch_supervisor_user_context): Temporarily switch to
supervisor mode.
(frvbf_store_quad_GR): Don't call handler directly.
(frvbf_store_quad_FRint): Don't call handler directly.
(frvbf_store_quad_CPR): Don't call handler directly.
(frvbf_clear_all_accumulators): Removed.
(frvbf_clear_accumulators): New function.
(frvbf_model_fr500_u_media): Expand busy_adjustment to 8 members.
Account for in_ACCGi and out_ACCGk.
* frv-sim.h (RSTR_HARDWARE_RESET): New macro.
(RSTR_SOFTWARE_RESET): New macro.
(spr_psr_get_handler): Renamed from frvbf_h_psr_get_handler.
(spr_psr_set_handler): Renamed from frvbf_h_psr_set_handler.
(spr_tbr_get_handler): Renamed from frvbf_h_tbr_get_handler.
(spr_tbr_set_handler): Renamed from frvbf_h_tbr_set_handler.
(spr_bpsr_get_handler): Renamed from frvbf_h_bpsr_get_handler.
(spr_bpsr_set_handler): Renamed from frvbf_h_bpsr_set_handler.
(spr_ccr_get_handler): Renamed from frvbf_h_ccr_get_handler.
(spr_ccr_set_handler): Renamed from frvbf_h_ccr_set_handler.
(spr_lr_get_handler): Renamed from frvbf_h_lr_get_handler.
(spr_lr_set_handler): Renamed from frvbf_h_lr_set_handler.
(spr_cccr_get_handler): Renamed from frvbf_h_cccr_get_handler.
(spr_cccr_set_handler): Renamed from frvbf_h_cccr_set_handler.
(spr_isr_get_handler): Renamed from frvbf_h_isr_get_handler.
(spr_isr_set_handler): Renamed from frvbf_h_isr_set_handler.
(spr_sr_get_handler): Renamed from frvbf_h_sr_get_handler.
(spr_sr_set_handler): Renamed from frvbf_h_sr_set_handler.
(frvbf_clear_all_accumulators): Removed.
(frvbf_clear_accumulators): New function.
(GET_HSR0): Use GET_H_SPR.
(SET_HSR0): Use SET_H_SPR.
(CLEAR_HSR0_ICE): New macro.
(CLEAR_HSR0_DCE): New macro.
(GET_IHSR8): Use GET_H_SPR.
(GET_PSR): New macro.
(SET_PSR_ET): New macro.
(GET_PSR_PS): New macro.
(SET_PSR_S): New macro.
(GET_ESFR): Changed to reference entire register.
(SET_ESFR): Changed to reference entire register.
(GET_ESFR_FLAG): New macro.
(SET_ESFR_FLAG): New macro.
(NECR_ELOS): Removed.
(NECR_NEN): Removed.
(NECR_VALID): Removed.
(GET_NECR): New macro.
(GET_NECR_ELOS): New macro.
(GET_NECR_NEN): New macro.
(GET_NECR_VALID): New macro.
(NESR_RANGE): Removed.
(GET_NESR): Use GET_H_SPR.
(GET_NE_FLAGS): Use GET_H_SPR.
* cache.h (CACHE_INITIALIZED): New macro.
* Makefile.in (SIM_OBJS): Add registers.o.
(SIM_EXTRA_DEPS): Add registers.h.
(registers.o): New target.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
2000-02-17 Dave Brolley <brolley@redhat.com>
* interrupts.c (frv_interrupt_table): Update priority order and handler
offsets to conform to the architecture version 1.3a.
* frv-sim.h (frv_interrupt_kind): Update priority order to conform
to the architecture version 1.3a.
2000-02-17 Dave Brolley <brolley@redhat.com>
* interrupts.c (frv_interrupt_table): Update priority order and handler
offsets to conform to the latest specifications.
(frv_queue_interrupt): Correct comment. Identical interrupts can be
queued. New variable 'iclass' used to test for external interrupts.
* frv-sim.h (frv_interrupt_kind): Update priority order to conform
to the latest specifications.
2000-01-20 Dave Brolley <brolley@redhat.com>
* sim-if.c (sim_open): Move frv-specific initialization to
frv_initialize in reset.c.
* interrupts.c (check_reset): Use RSTR_ADDRESS. Check and reset RSTR
status bits for hardware vs software reset.
* reset.c: New file.
* frv-sim.h (frv_initialize): New function.
(frv_power_on_reset): New function.
(frv_hardware_reset): New function.
(frv_software_reset): New function.
(RSTR_ADDRESS): New macro.
(RSTR_INITIAL_VALUE): New macro.
(GET_RSTR_HR): New macro.
(GET_RSTR_SR): New macro.
(SET_RSTR_H): New macro.
(SET_RSTR_S): New macro.
(CLEAR_RSTR_P): New macro.
(CLEAR_RSTR_H): New macro.
(CLEAR_RSTR_S): New macro.
(CLEAR_RSTR_HR): New macro.
(CLEAR_RSTR_SR): New macro.
2000-01-03 Dave Brolley <brolley@cygnus.com>
* mloop.in (execute): Only call modeling function if the pointer is not
NULL.
* frv.c (frvbf_model_insn_after): Only access FR500_MODEL_DATA for
fr500.
2000-01-03 Dave Brolley <brolley@cygnus.com>
* options.c (OPTION_FRV_MEMORY_LATENCY): New enumerator.
(frv_options): Add --memory-latency.
(frv_option_handler): Handle FRV_OPTION_MEMORY_LATENCY.
* mloop.in (@cpu@_simulate_insn_prefetch): Use cache memory_latency.
* frv.c (SET_ACC_USE_IS_MEDIA_P1): operate on d->curr_acc_p1
(SET_ACC_USE_NOT_MEDIA_P1): operate on d->curr_acc_p1
(SET_ACC_USE_IS_MEDIA_P2): operate on d->curr_acc_p1
(SET_ACC_USE_NOT_MEDIA_P2): operate on d->curr_acc_p1
(update_latencies): Only clear usage flags if the register has no
target latency.
(frvbf_model_insn_before): Update cur_acc_p1 and cur_acc_p2. Use | (or)
not |= (or assgnment).
(frvbf_model_insn_after): Print post processing wait for all insns.
Update prev_acc_p1 and prev_acc_p2.
(frvbf_model_fr500_u_gr_load_store): Use cache memory_latency.
(frvbf_model_fr500_u_fr_load_store): Use cache memory_latency.
(frvbf_model_fr500_u_swap): Use cache memory_latency.
(frvbf_model_fr500_u_media): Use busy_adjustment[4] for out_ACC40Sk.
(frvbf_model_fr500_u_media): Use busy_adjustment[5] for out_ACC40Uk.
(frvbf_model_fr500_u_media_quad_arith): New function.
(frvbf_model_fr500_u_media_dual_mul): New function.
(frvbf_model_fr500_u_media_quad_mul): New function.
(frvbf_model_fr500_u_media_quad_complex): New function.
(frvbf_model_fr500_u_media_dual_expand): New function.
(frvbf_model_fr500_u_media_dual_unpack): New function.
(frvbf_model_fr500_u_media_dual_btoh): New function.
(frvbf_model_fr500_u_media_dual_htob): New function.
(frvbf_model_fr500_u_media_dual_btohe): New function.
(frv_ref_SI): New function.
* cache.h (FRV_CACHE): Add memory_latency field.
* cache.c (frv_cache_init): Initialize memory_latency.
* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-12-17 Dave Brolley <brolley@cygnus.com>
* sim-if.c (sim_open): Initialize insn prefetch and reset register.
* options.c (OPTIONS_FRV_PROFILE_CACHE): New enumeration.
(OPTIONS_FRV_PROFILE_PARALLEL): New enumeration.
(OPTIONS_FRV_TIMER): New enumeration.
(frv_options): Add --profile-cache, --profile-parallel, --timer.
(frv_option_handler): Override common implementation of -p. Handle
--profile-cache, --profile-parallel, --timer.
* mloop.in (execute): Call profiling functions if the timer interrupt
is enabled.
(@cpu@_simulate_insn_prefetch): New function.
(main loop): Call @cpu@_simulate_insn_prefetch.
* interrupts.c (frv_queue_interrupt): Don't queue two external
interrupts of the same priority.
(frv_queue_external_interrupt): New function.
(frv_external_interrupt): New function.
(handle_interrupt): Handle external interrupts.
(check_reset): New function.
(frv_process_interrupts): Call check_reset.
* frv.c: Include "bfd.h"
(frvbf_h_psr_get_handler): Set the PIL field.
(frvbf_h_psr_set_handler): Get the PIL field.
(DUAL_REG): New macro.
(DUAL_DOUBLE): New macro.
(SET_USE_IS_FPOP): New macro.
(SET_USE_NOT_FPOP): New macro.
(USE_IS_FPOP): New macro.
(SET_USE_IS_MEDIA): New macro.
(SET_USE_NOT_MEDIA): New macro.
(USE_IS_MEDIA_P1): New macro.
(SET_USE_IS_MEDIA_P1): New macro.
(SET_USE_NOT_MEDIA_P1): New macro.
(SET_USE_IS_MEDIA_P2): New macro.
(SET_USE_NOT_MEDIA_P2): New macro.
(USE_IS_MEDIA_P2): New macro.
(SET_ACC_USE_IS_MEDIA_P1): New macro.
(SET_ACC_USE_NOT_MEDIA_P1): New macro.
(ACC_USE_IS_MEDIA_P1): New macro.
(SET_ACC_USE_IS_MEDIA_P2): New macro.
(SET_ACC_USE_NOT_MEDIA_P2): New macro.
(ACC_USE_IS_MEDIA_P2): New macro.
(RESOURCE_IDIV): New macro.
(RESOURCE_FDIV): New macro.
(RESOURCE_SQRT): New macro.
(fr_busy_adjust): New array.
(acc_busy_adjust): New array.
(apply_latency_adjustments): New function.
(update_latencies): New function.
(handle_wait_cycles): New function.
(handle_resource_wait): New function.
(update_target_latencies): New function.
(frvbf_model_insn_before): Add resource latency to cycle counts.
(frvbf_model_insn_after): Add resource latency to cycle counts.
(update_GR_latency): New function.
(update_GRdouble_latency): New function.
(update_FR_latency): New function.
(update_FRdouble_latency): New function.
(decrease_ACC_busy): New function.
(decrease_FR_busy): New function.
(increase_FR_busy): New function.
(update_ACC_latency): New function.
(update_CCR_latency): New function.
(update_idiv_resource_latency): New function.
(update_fdiv_resource_latency): New function.
(update_fsqrt_resource_latency): New function.
(vliw_wait_for_GR): New function.
(vliw_wait_for_GRdouble): New function.
(vliw_wait_for_FR): New function.
(vliw_wait_for_FRdouble): New function.
(vliw_wait_for_CCR): New function.
(vliw_wait_for_ACC): New function.
(vliw_wait_for_idiv_resource): New function.
(vliw_wait_for_fdiv_resource): New function.
(vliw_wait_for_fsqrt_resource): New function.
(enforce_full_fr_latency): New function.
(frvbf_model_fr500_u_exec): New function.
(frvbf_model_fr500_u_integer): New function.
(frvbf_model_fr500_u_imul): New function.
(frvbf_model_fr500_u_idiv): New function.
(frvbf_model_fr500_u_branch): New function.
(frvbf_model_fr500_u_set_hilo): New function.
(frvbf_model_fr500_u_gr_load_store): New function.
(frvbf_model_fr500_u_fr_load_store): New function.
(frvbf_model_fr500_u_swap): New function.
(frvbf_model_fr500_u_fr2fr): New function.
(frvbf_model_fr500_u_fr2gr): New function.
(frvbf_model_fr500_u_spr2gr): New function.
(frvbf_model_fr500_u_gr2fr): New function.
(frvbf_model_fr500_u_gr2spr): New function.
(post_wait_for_FR): New function.
(post_wait_for_FRdouble): New function.
(post_wait_for_ACC): New function.
(post_wait_for_CCR): New function.
(post_wait_for_fdiv): New function.
(post_wait_for_fsqrt): New function.
(adjust_float_register_busy): New function.
(adjust_double_register_busy): New function.
(restore_float_register_busy): New function.
(restore_double_register_busy): New function.
(frvbf_model_fr500_u_float_arith): New function.
(frvbf_model_fr500_u_float_dual_arith): New function.
(frvbf_model_fr500_u_float_div): New function.
(frvbf_model_fr500_u_float_sqrt): New function.
(frvbf_model_fr500_u_float_compare): New function.
(frvbf_model_fr500_u_float_dual_compare): New function.
(frvbf_model_fr500_u_float_convert): New function.
(frvbf_model_fr500_u_media): New function.
(frvbf_model_fr500_u_barrier): New function.
(frvbf_model_fr500_u_membar): New function.
* frv-sim.h (LEUINT): New macro.
(GET_HSR0_SA): New macro.
(struct frv_interrupt_timer): New struct.
(struct frv_interrupt_state): Add timer fiield.
(frv_queue_external_interrupt): New function.
(frv_external_interrupt): New function.
(frv_profile_info): New function.
(PROFILE_CACHE_IDX): New enumerator.
(PROFILE_PARALLEL_IDX): New enumerator.
(PROFILE_cache): New macro.
(PROFILE_parallel): New macro.
(WITH_PROFILE_CACHE_P): New macro.
(WITH_PROFILE_PARALLEL_P): New macro.
* cache.h (FRV_CACHE): Add last_was_hit field.
* cache.c (get_tag): Use new last_was_hit field.
(frv_cache_read): Ditto.
(frv_cache_write): Ditto.
* arch.h,cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-12-13 Dave Brolley <brolley@cygnus.com>
* frv.c (frvbf_h_spr_set_handler): Handle accumulator guards.
(frvbf_clear_all_accumulators): Pass frvbf_h_acc40S_set to
sim_queue_fn_di_write.
(frvbf_media_cut_ss): New function.
* frv-sim.h (frvbf_media_cut_ss): New function.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-12-13 Dave Brolley <brolley@cygnus.com>
* pipeline.c (check_insn_major_constraints): F-4, F-8 and M-8 have
no constraints.
* interrupts.c (frv_queue_illegal_instruction_interrupt): Use
FRV_IS_FLOAT_INSN and FRV_IS_MEDIA_INSN.
(frv_detect_insn_access_interrupts): Use FRV_IS_FLOAT_INSN and
FRV_IS_MEDIA_INSN.
* frv.c (frvbf_model_simple_u_exec): New function.
* frv-sim.h (FRV_IS_FLOAT_INSN): Range includes F-8.
(FRV_IS_MEDIA_INSN): Range includes M-8.
* Makefile.in (stamp-cpu): add 'simple' to the list of machines.
* arch.c,arch.h,cpu.h,cpuall.h,decode.c,decode.h,model.c,sem.c:
Regenerate.
1999-12-10 Dave Brolley <brolley@cygnus.com>
* traps.c (check_registers_available): New function.
(clear_ne_flags): Generate register_exception if register(s) not
available.
(frvbf_commit): Generate register_exception if register(s) not
available.
* interrupts.c (frv_program_or_software_interrupt): No need to copy
GR4-GR7 to SR0-SR4.
* frv.c (frvbf_h_psr_set_handler): Special handling for PSR.S and
PSR.ESR.
(frvbf_h_psr_s_set_handler): New function.
(frvbf_h_psr_esr_set_handler): New function.
(frvbf_switch_supervisor_user_context): New function.
(frvbf_scan_result): Reflect latest ISA.
* frv-sim.h (frvbf_h_psr_s_set_handler): New function.
(frvbf_h_psr_esr_set_handler): New function.
(frvbf_switch_supervisor_user_context): New function.
(GET_HSR0_FRN): New Macro.
(GET_HSR0_GRN): New Macro.
(GET_HSR0_FRHE): New Macro.
(GET_HSR0_FRLE): New Macro.
(GET_HSR0_GRHE): New Macro.
(GET_HSR0_GRLE): New Macro.
(frv_ec): New value for FRV_EC_COMMIT_EXCEPTION.
(GET_ESFR): New bit ordering.
(SET_ESFR): New bit ordering.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-12-10 Michael Meissner <meissner@cygnus.com>
* Makefile.in (sim-if.o): Add eng.h dependency.
1999-12-09 Dave Brolley <brolley@cygnus.com>
* mloop.in (execute): Pass sc->first_insn_p to @cpu@_model_insn_before.
Pass sc->last_insn_p to @cpu@_model_insn_before.
(main loop): Compute sc->first_insn_p.
* frv.c (frvbf_model_insn_before): Set state variables.
(frvbf_model_insn_after): Count basic cycles. Set state variables.
(frvbf_model_fr500_u_integer): Remove.
* arch.h,cpu.h,decode.h,model.c: Regenerate.
1999-12-07 Dave Brolley <brolley@cygnus.com>
* sim-main.h (cache.h): Include it.
(insn_cache): New member.
(data_cache): New member.
(CPU_INSN_CACHE): New macro.
(CPU_DATA_CACHE): New macro.
* sim-if.c (WANT_CPU): New macro.
(WANT_CPU_FRVBF): New macro.
(sim_open): Call sim_add_option_table. Call frv_cache_init for the
data and insn caches for each cpu.
(sim_close): Call frv_cache_term for the insn and data caches of each
cpu.
* mloop.in (extract): Read insn from the cache.
(main loop): Access the insn cache in order to maintain stats.
* memory.c (data_non_cache_access): New function.
(insn_non_cache_access): New function.
(frvbf_read_mem_QI): Attempt to read from the cache first.
(frvbf_read_mem_UQI): Ditto.
(frvbf_read_mem_HI): Ditto.
(frvbf_read_mem_UHI): Ditto.
(frvbf_read_mem_SI): Ditto.
(frvbf_read_mem_DI): Ditto.
(frvbf_read_mem_DF): Ditto.
(frvbf_read_imem_USI): New function.
(frvbf_write_mem_QI): Write through the cache is it is enabled.
(frvbf_write_mem_UQI): Ditto.
(frvbf_write_mem_HI): Ditto.
(frvbf_write_mem_UHI): Ditto.
(frvbf_write_mem_SI): Ditto.
(frvbf_write_mem_DI): Ditto.
(frvbf_write_mem_DF): Ditto.
(frvbf_mem_set_QI): New function.
(frvbf_mem_set_HI): New function.
(frvbf_mem_set_SI): New function.
(frvbf_mem_set_DI): New function.
(frvbf_mem_set_DF): New function.
(frvbf_mem_set_XI): New function.
* interrupts.c (frv_save_data_written_for_interrupts): Handle
CGEN_FN_MEM_QI_WRITE,
CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE, CGEN_FN_MEM_DI_WRITE,
CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE.
* frv.c (frvbf_load_quad_GR): Call frvbf_read_mem_SI.
Call sim_queue_fn_mem_xi_write.
(frvbf_load_quad_FRint): Call frvbf_read_mem_SI.
Call sim_queue_fn_mem_xi_write.
(frvbf_load_quad_CPR): Call frvbf_read_mem_SI.
Call sim_queue_fn_mem_xi_write.
(frvbf_insn_cache_preload): New function.
(frvbf_data_cache_preload): New function.
(frvbf_insn_cache_unlock): New function.
(frvbf_data_cache_unlock): New function.
(frvbf_insn_cache_invalidate): New function.
(frvbf_data_cache_invalidate): New function.
(frvbf_data_cache_flush): New function.
* frv-sim.h (sim-options.h): Include it.
(GET_HSR0): New macro.
(SET_HSR0): New macro.
(GET_HSR0_ICE): New macro.
(SET_HSR0_ICE): New macro.
(GET_HSR0_DCE): New macro.
(SET_HSR0_DCE): New macro.
(GET_HSR0_CBM): New macro.
(GET_HSR0_RME): New macro.
(GET_IHSR8): New macro.
(GET_IHSR8_NBC): New macro.
(frvbf_insn_cache_preload): New function.
(frvbf_data_cache_preload): New function.
(frvbf_insn_cache_unlock): New function.
(frvbf_data_cache_unlock): New function.
(frvbf_insn_cache_invalidate): New function.
(frvbf_data_cache_invalidate): New function.
(frvbf_data_cache_flush): New function.
(insn_non_cache_access): New function.
(frvbf_read_imem_USI): New function.
(frvbf_mem_set_QI): New function.
(frvbf_mem_set_HI): New function.
(frvbf_mem_set_SI): New function.
(frvbf_mem_set_DI): New function.
(frvbf_mem_set_DF): New function.
(frvbf_mem_set_XI): New function.
(frv_options): FRV specific command line options.
* Makefile.in (SIM_OBJS): Add options.o and cache.o.
(SIM_EXTRA_DEPS): Add $(sim-options_h).
(cache.o): New target.
(options.o): New target.
* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
* cache.h: New file.
* cache.c: New file.
* options.c: New file.
1999-11-29 Dave Brolley <brolley@cygnus.com>
* traps.c (frvbf_check_non_excepting_load): Use new NE_FLAG macros.
(frvbf_check_non_excepting_divide): Ditto.
(clear_ne_flags): Ditto
(frvbf_commit): Ditto.
* pipeline.c (frv_pipeline_add_insn): Clear the NE index for all insns.
* mloop.in (_parallel_write_init): Clear NE flags here.
* interrupts.c (frv_queue_fp_exception_interrupt): Set NE flags here
for non excepting insns. Also check for masked interrupts here.
(frv_process_interrupts): Write NE flags here.
(set_fp_exception_registers): No longer check for masked interrupts
here.
(check_for_compound_interrupt): No need to worry about masked
interrupts.
* frv-sim.h (frv_interrupt_state): Add f_ne_flags member.
(GET_NE_FLAGS): New macro.
(SET_NE_FLAGS): New macro.
(GET_NE_FLAG): Operate on accumulated argument.
(SET_NE_FLAG): Operate on accumulated argument.
(CLEAR_NE_FLAG): Operate on accumulated argument.
* Makefile.in (FRVBF_INCLUDE_DEPS): Add $(SIM_EXTRA_DEPS)
(frv.o): Correct dependencies.
(traps.o): Ditto.
(pipeline.o): Ditto.
(interrupts.o): Ditto.
(memory.o): Ditto.
* sem.c: Regenerate.
1999-11-26 Dave Brolley <brolley@cygnus.com>
* traps.c (frvbf_fpu_error): Only call frv_queue_fp_exception if
there is an exception indicated in the mask.
* pipeline.c (frv_pipeline_add_insn): Clear ne_index in the interrupt
state when adding a floating point insn to the pipeline.
* interrupts.c (set_fp_exception_registers): Set NE flag for
non-excepting insns.
* frv-sim.h (frvbf_h_fr_double_get_handler): Mode of data is DF.
(frvbf_h_fr_double_set_handler): Mode of data is DF.
(frvbf_h_fr_int_get_handler): New function.
(frvbf_h_fr_int_set_handler): New function.
(frvbf_set_ne_index): New function.
(NE_NOFLAG): New macro.
(frv_interrupt_state): Add ne_index member.
* frv.c (frvbf_h_fr_double_get_handler): Mode of data is DF.
(frvbf_h_fr_double_set_handler): Mode of data is DF.
(frvbf_h_fr_int_get_handler): New function.
(frvbf_h_fr_int_set_handler): New function.
(frvbf_set_ne_index): New function.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-11-24 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-11-23 Dave Brolley <brolley@cygnus.com>
* frv-sim.h (frvbf_media_cut): New function.
* frv.c (frvbf_media_cut): New function.
* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-11-22 Dave Brolley <brolley@cygnus.com>
* frv-sim.h (frvbf_clear_all_accumulators): New function.
* frv.c.h (frvbf_clear_all_accumulators): New function.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-11-18 Dave Brolley <brolley@cygnus.com>
* pipeline.c (frv_pipeline_add_insn): Only clear MSR0 and FSR0 fields
if this is the first insn of its class in the pipeline.
* frv-sim.h (frvbf_media_register_not_aligned): New function.
* traps.c (frvbf_media_register_not_aligned): New function.
* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-11-17 Dave Brolley <brolley@cygnus.com>
* pipeline.c (frv_pipeline_add_insn): Clear MSRx.SIE fields.
* frv-sim.h (OR_MSR_SIE): New macro.
(CLEAR_MSR_SIE): New macro.
(frvbf_media_overflow): Now takes sie argument.
(frv_set_mp_exception_registers): Now takes sie argument.
* interrupts.c (frv_set_mp_exception_registers): Now takes sie argument.
Set MSRx.SIE field.
* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-11-15 Dave Brolley <brolley@cygnus.com>
* traps.c (frv_mtrap): New function.
(frvbf_media_cr_not_aligned): New function.
(frvbf_media_acc_not_aligned): New function.
(frvbf_media_overflow): New function.
* pipeline.c (frv_pipeline_add_insn): Clear MSR fields.
* interrupts.c: Call frv_set_mp_exception_registers.
(frv_set_mp_exception_registers): New function.
* frv-sim.h (frv_msr_mtt): New enumeration.
(GET_MSR): New macro.
(SET_MSR): New macro.
(GET_MSR_AOVF): New macro.
(SET_MSR_AOVF): New macro.
(GET_MSR_OVF): New macro.
(SET_MSR_OVF): New macro.
(CLEAR_MSR_OVF): New macro.
(GET_MSR_MTT): New macro.
(SET_MSR_MTT): New macro.
(frv_set_mp_exception_registers): New function.
(frv_mtrap): New function.
(FRV_IS_MEDIA_INSN): New macro.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-11-10 Dave Brolley <brolley@cygnus.com>
* sim-main.h (_sim_cpu): Add debug_state member.
* mloop.in (_parallel_write_queued): Clear data_written.length.
* interrupts.c (frv_interrupt_table): Offset of BREAK_EXCEPTION
handler is 0xff.
(frv_queue_break_interrupt): New function.
(frv_break_interrupt): New function.
(handle_interrupt): Handle break_interrupt.
(frv_non_operating_interrupt): Now takes interrupt_kind.
* frv-sim.h (frv_queue_break_interrupt): New function.
(frv_break_interrupt): New function.
(frv_break): New function.
(frv_non_operating_interrupt): Now takes interrupt_kind.
* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-11-09 Dave Brolley <brolley@cygnus.com>
* pipeline.c (frv_pipeline_add_insn): Clear FSR0.FTT when adding
a floating point insn.
* traps.c (frvbf_fpu_error): Map fpu status to frv interrupts.
* interrupts.c (frv_queue_illegal_instruction_interrupt): Call
frv_queue_fp_exception_interrupt.
(frv_queue_fp_exception_interrupt): New function.
(next_available_fq): New function.
(set_fp_exception_registers): New function.
(set_exception_status_registers): Now returns 1 if interrupt not masked.
(check_for_compound_interrupt): Now returns NULL if interrupt masked.
(frv_program_interrupt): Don't process interrupt if it is masked.
* frv.c (frvbf_h_fr_double_get_handler): Call
frv_queue_fp_exception_interrupt.
(frvbf_h_fr_double_set_handler): Call frv_queue_fp_exception_interrupt.
(frvbf_h_fr_quad_set_handler): Call frv_queue_fp_exception_interrupt.
(frvbf_store_quad_FRint): Call frv_queue_fp_exception_interrupt.
* frv-sim.h: Get/set hardware directly in GET/SET macros.
(frv_fp_exception_info): New struct type.
(frv_interrupt_queue_element): Add fp_info member.
(frv_fsr_traps): New enumeration.
(frv_fsr_ftt): New enumeration.
(frv_sie): New enumeration.
(frv_miv): New enumeration.
(GET_FSR): New macro.
(SET_FSR): New macro.
(GET_FSR_TEM): New macro.
(SET_FSR_QNE): New macro.
(SET_FSR_FTT): New macro.
(GET_FSR_AEXC): New macro.
(SET_FSR_AEXC): New macro.
(GET_FQ): New macro.
(SET_FQ): New macro.
(SET_FQ_OPC): New macro.
(SET_FQ_MIV): New macro.
(SET_FQ_SIE): New macro.
(SET_FQ_FTT): New macro.
(SET_FQ_CEXC): New macro.
(GET_FQ_VALID): New macro.
(SET_FQ_VALID): New macro.
(frv_queue_fp_exception_interrupt): New function.
(FRV_IS_FLOAT_INSN): New macro.
1999-11-04 Dave Brolley <brolley@cygnus.com>
* traps.c (frvbf_fpu_error): No floating point errors need to be
detected.
* interrupts.c (clear_exception_status_registers): Clear 'valid' fields
of the ESR registers too.
(set_exception_status_registers): Don't set EAR for any precise
interrupts. Register index should be 1 for insns in PIPE_I1. Clear
ESR.EAV and ESR.EDV if not setting them. Set ESR.VALID.
(non_operating_interrupt): No need for return code.
(frv_program_or_software_interrupt): Process interrupt regardless
of operating mode. If PSR.ET was not set at the start of processing,
then stop the simulation with a message.
(frv_save_data_written_for_interrupts): Handle CGEN_FN_XI_WRITE and
CGEN_MEM_XI_WRITE.
* frv.c (frvbf_h_gr_quad_set_handler): New function.
(frvbf_h_fr_quad_set_handler): New function.
(frvbf_h_cpr_quad_set_handler): New function.
(frvbf_load_quad_GR): Renamed from frvbf_load_multiple_GR. Use new
sim_queue_fn_xi_write.
(frvbf_load_quad_FRint): Renamed from frvbf_load_multiple_GR. Use new
sim_queue_fn_xi_write.
(frvbf_load_quad_CPR): Renamed from frvbf_load_multiple_GR. Use new
sim_queue_fn_xi_write.
(frvbf_store_quad_GR): Renamed from frvbf_store_multiple_GR. Use new
sim_queue_mem_xi_write.
(frvbf_store_quad_FRint): Renamed from frvbf_store_multiple_GR. Use new
sim_queue_mem_xi_write.
(frvbf_store_quad_CPR): Renamed from frvbf_store_multiple_GR. Use new
sim_queue_mem_xi_write.
* frv-sim.h (frvbf_h_gr_quad_set_handler): New function.
(frvbf_h_fr_quad_set_handler): New function.
(frvbf_h_cpr_quad_set_handler): New function.
(SET_ESR_VALID): New macro.
(CLEAR_ESR_VALID): New macro.
(CLEAR_ESR_EAV): New macro.
(CLEAR_ESR_EDV): New macro.
* sem.c: Regenerate.
1999-11-02 Dave Brolley <brolley@cygnus.com>
* traps.c (frv_core_signal): Call
frv_queue_mem_address_not_aligned_interrupt.
* mloop.in (_parallel_write_queued): Call
frv_save_data_written_for_interrupts.
* frv.c (frvbf_h_gr_double_get_handler): Call
frv_queue_register_exception_interrupt.
(frvbf_h_cpr_double_get_handler): Call
frv_queue_register_exception_interrupt.
(frvbf_h_cpr_double_set_handler): Call
frv_queue_register_exception_interrupt.
(frvbf_load_multiple_GR): Call
frv_queue_register_exception_interrupt.
(frvbf_store_multiple_GR): Call
frv_queue_register_exception_interrupt.
(frvbf_load_multiple_CPR): Call
frv_queue_register_exception_interrupt.
(frvbf_store_multiple_CPR): Call
frv_queue_register_exception_interrupt.
(frvbf_h_tbr_get_handler): Fix TBR.TBA mask.
* interrupts.c (frv_queue_software_interrupt): Now returns interrupt
queue element.
(frv_queue_program_interrupt): Now returns interrupt queue element.
(frv_queue_illegal_instruction_interrupt): Now returns interrupt queue
element.
(frv_queue_interrupt): Now returns interrupt queue element.
(frv_queue_register_exception_interrupt): New function.
(frv_queue_mem_address_not_aligned_interrupt): New function.
(frv_save_data_written_for_interrupts): New function.
(next_available_edr): EDR registers available in blocks of 4.
(clear_exception_status_registers): New function.
(set_exception_status_registers): Pass esr to SET_ESR* macros.
* frv-sim.h (struct frv_data_written): New struct type.
(frv_interrupt_queue_element): Add data_written member.
(frv_queue_software_interrupt): Now returns interrupt queue element.
(frv_queue_program_interrupt): Now returns interrupt queue element.
(frv_queue_illegal_instruction_interrupt): Now returns interrupt queue
element.
(frv_queue_interrupt): Now returns interrupt queue element.
(frv_queue_register_exception_interrupt): New function.
(frv_queue_mem_address_not_aligned_interrupt): New function.
(frv_save_data_written_for_interrupts): New function.
1999-10-27 Dave Brolley <brolley@cygnus.com>
* interrupts.c (ITABLE_ENTRY): New macro.
(frv_interrupt_table): Add exception codes.
(next_available_esr): New function.
(next_available_edr): New function.
(set_edr_register): New function.
(set_exception_status_registers): New function.
(check_for_compound_interrupt): Record information on all interrupts
found.
(frv_program_interrupt): Always call check_for_compound_interrupt.
* frv.c (frvbf_h_pc_set_handler): Removed.
(frvbf_h_spr_get_handler): Handle LR register.
(frvbf_h_spr_set_handler): Handle LR register.
(frvbf_h_lr_get_handler): New function.
(frvbf_h_lr_set_handler): New function.
* frv-sim.h (frvbf_h_lr_get_handler): New function.
(frvbf_h_lr_set_handler): New function.
(frv_ec): New enumeration.
(frv_interrupt): Add frv_ec field.
(frv_rec): New enumeration.
(frv_daec): New enumeration.
(frv_interrupt_queue_element): Add eaddress, rec, iaec, daec fields.
(SET_ESR_EC): New macro.
(SET_ESR_REC): New macro.
(SET_ESR_IAEC): New macro.
(SET_ESR_DAEC): New macro.
(SET_ESR_EAV): New macro.
(GET_ESR_EDV): New macro.
(SET_ESR_EDV): New macro.
(GET_ESR_EDN): New macro.
(SET_ESR_EDN): New macro.
(GET_ESR): New macro.
(SET_ESR): New macro.
(SET_EPCR): New macro.
(SET_EAR): New macro.
(SET_EDR): New macro.
(GET_ESFR): New macro.
(SET_ESFR): New macro.
* cpu.c,cpu.h,sem.c: Rebuild.
1999-10-26 Dave Brolley <brolley@cygnus.com>
* traps.c (frvbf_check_non_excepting_load): Only set NESR, NECR, NEEAR
if mach is frv.
(clear_nesr_neear): Only execute if mach is frv.
1999-10-22 Dave Brolley <brolley@cygnus.com>
* sim-main.h (sim_cpu): Add pipeline.
(CPU_PIPELINE): New macro.
* mloop.in (_parallel_write_queued): Maintain pc in cpu during writes.
(main loop): Maintain pc in cpu.
* frv-sim.h (frv_queue_software_interrupt): New interface.
(frv_queue_program_interrupt): New interface.
(frv_queue_illegal_instruction_interrupt: New interface.
(frv_queue_interrupt): New interface.
(frv_detect_insn_access_interrupts): New interface.
(frv_process_interrupts): New interface.
(frv_program_interrupt): New interface.
(frv_software_interrupt): New interface.
(frv_program_or_software_interrupt): New interface.
(FRV_PIPELINE): Moved from pipline.c.
(frv_pipeline_reset): New interface.
(frv_pipeline_add_insn): New interface.
* interrupts.c (frv_queue_software_interrupt): New interface.
(frv_queue_program_interrupt): New interface.
(frv_queue_illegal_instruction_interrupt: New interface.
(frv_queue_interrupt): New interface.
(frv_detect_insn_access_interrupts): New interface.
(frv_process_interrupts): New interface.
(frv_program_interrupt): New interface.
(frv_software_interrupt): New interface.
(frv_program_or_software_interrupt): New interface.
* frv.c: Use new interfaces.
* pipeline.c: Use new interfaces.
* traps.c: Use new interfaces.
* memory.c: Use new interfaces.
(frv_address_forbidden): No longer static.
1999-10-19 Dave Brolley <brolley@cygnus.com>
* traps.c (frvbf_check_non_excepting_load): Set NESR.DAEC, NESR.REC and
NESR.EC.
* mloop.in (_parallel_write_queued): Handle CGEN_FN_PC_WRITE.
* frv.c (frvbf_h_pc_set_handler): New function.
* interrupts.c (frv_detect_data_interrupt): Removed.
(address_forbidden): Removed.
* frv-sim.h (frv_detect_data_interrupt): Removed.
(NESR_MEM_ADDRESS_NOT_ALIGNED): New macro.
(NESR_REGISTER_NOT_ALIGNED): New macro.
(NESR_UQI_SIZE): New macro.
(NESR_QI_SIZE): New macro.
(NESR_UHI_SIZE): New macro.
(NESR_HI_SIZE): New macro.
(NESR_SI_SIZE): New macro.
(NESR_DI_SIZE): New macro.
(NESR_XI_SIZE): New macro.
(GET_NESR_DAEC): New macro.
(SET_NESR_DAEC): New macro.
(GET_NESR_REC): New macro.
(SET_NESR_REC): New macro.
(GET_NESR_EC): New macro.
(SET_NESR_EC): New macro.
(frvbf_read_mem_QI): New function.
(frvbf_read_mem_UQI): New function.
(frvbf_read_mem_HI): New function.
(frvbf_read_mem_UHI): New function.
(frvbf_read_mem_SI): New function.
(frvbf_read_mem_WI): New function.
(frvbf_read_mem_DI): New function.
(frvbf_read_mem_DF): New function.
(frvbf_write_mem_QI): New function.
(frvbf_write_mem_UQI): New function.
(frvbf_write_mem_HI): New function.
(frvbf_write_mem_UHI): New function.
(frvbf_write_mem_SI): New function.
(frvbf_write_mem_WI): New function.
(frvbf_write_mem_DI): New function.
(frvbf_write_mem_DF): New function.
* Makefile.in (SIM_OBJS): Add memory.o.
* cpu.c,cpu.h,sem.c: Rebuild.
1999-10-18 Dave Brolley <brolley@cygnus.com>
* sim-if.c (sim_open): Use a real fpu error function.
* pipeline.c (frv_pipeline_add_insn): Don't add invalid insns.
* mloop.in (_parallel_write_queued): Clear queue after writing.
* interrupts.c (check_for_compound_interrupt): New function.
(non_operating_interrupt): New function.
* frv-sim.h (frvbf_h_gr_double_get_handler): New function.
(frvbf_h_gr_double_set_handler): New function.
(frvbf_h_fr_double_get_handler): New function.
(frvbf_h_fr_double_set_handler): New function.
(frvbf_h_cpr_double_get_handler): New function.
(frvbf_h_cpr_double_set_handler): New function.
(frv_interrupt_queue_element): New struct type.
(frv_queue_program_interrupt): Now takes pc.
(frv_queue_illegal_instruction_interrupt): Now takes pc.
(frv_queue_interrupt): Now takes pc.
(frv_program_interrupt): Now takes frv_interrupt_queue_element.
(frv_software_interrupt): Now takes frv_interrupt_queue_element.
(frvbf_division_exception): New function.
(frvbf_fpu_error): New function.
(frvbf_load_multiple_GR): New function.
(frvbf_load_multiple_FR): New function.
(frvbf_load_multiple_CPR): New function.
* frv.c (frvbf_h_gr_double_get_handler): New function.
(frvbf_h_gr_double_set_handler): New function.
(frvbf_h_fr_double_get_handler): New function.
(frvbf_h_fr_double_set_handler): New function.
(frvbf_h_cpr_double_get_handler): New function.
(frvbf_h_cpr_double_set_handler): New function.
(frv_interrupt_queue_element): New struct type.
(frv_queue_program_interrupt): Now takes pc.
(frv_queue_illegal_instruction_interrupt): Now takes pc.
(frv_queue_interrupt): Now takes pc.
(frv_program_interrupt): Now takes frv_interrupt_queue_element.
(frv_software_interrupt): Now takes frv_interrupt_queue_element.
(frvbf_fpu_error): New function.
(frvbf_load_multiple_GR): New function.
(frvbf_load_multiple_FR): New function.
(frvbf_load_multiple_CPR): New function.
* traps.c (frvbf_division_exception): New function.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
1999-10-12 Dave Brolley <brolley@cygnus.com>
* mloop.in (new_vpc): New variable.
(main loop): Call frv_detect_insn_access_interrupts. Call
frv_detect_data_interrupts.
* interrupts.c (access_queued_to): New function.
(frv_detect_data_interrupts): New function.
(frv_detect_insn_access_interrupts): New function.
(frv_program_or_software_interrupt): Set PSR.S.
* frv-sim.h (frv_detect_data_interrupts): New function.
(frv_detect_insn_interrupts): New function.
1999-10-07 Dave Brolley <brolley@cygnus.com>
* frv-sim.h (frvbf_h_gr_hi_get_handler): New function.
(frvbf_h_gr_hi_set_handler): New function.
(frvbf_h_gr_lo_get_handler): New function.
(frvbf_h_gr_lo.set_handler): New function.
* frv.c (frvbf_h_gr_hi_get_handler): New function.
(frvbf_h_gr_hi_set_handler): New function.
(frvbf_h_gr_lo_get_handler): New function.
(frvbf_h_gr_lo.set_handler): New function.
(frvbf_model_fr500_u_integer): New function.
* arch.h,cpu.h,cpu.c,decode.h,decode.c,model.c,sem.c: Rebuild.
1999-10-04 Dave Brolley <brolley@cygnus.com>
* traps.c: Use sim_engine_abort.
* pipeline.c (frv_pipeline): Add field for insn major.
(add_next_to_pipe): Return address of matching pipeline.
(find_major_in_pipeline): New function.
(check_insn_major_constraints: New function.
(frv_pipeline_add_insn): Add checks for insn major constraints.
* interrupts.c (frv_process_interrupts): Use sim_engine_abort.
* frv.c (frvbf_h_spr_get_handler): No need to abort.
Thu Sep 30 18:10:25 1999 Dave Brolley <brolley@cygnus.com>
* pipeline.c: New file.
* mloop.in (main loop): Call frv_pipeline_reset.
Call frv_pipeline_add_insn.
* frv-sim.h (frv_pipeline_reset): New function.
(frv_pipeline_add_insn): New function.
* Makefile.in (SIM_OBJS): Add pipeline.o
1999-09-29 Doug Evans <devans@casey.cygnus.com>
* sem.c: Rebuild.
* traps.c (sim_engine_invalid_insn): New arg `vpc'. Change type of
result to SEM_PC. Return vpc.
Wed Sep 29 16:01:52 1999 Dave Brolley <brolley@cygnus.com>
* interrupts.c (frv_interrupt_table): DATA_STORE_ERROR is imprecise.
(frv_queue_interrupt): Don't detect identical interrupts here.
Wed Sep 29 14:49:52 1999 Dave Brolley <brolley@cygnus.com>
* interrupts.c: New file.
* traps.c (sim_engine_invalid_insn): Return PC of next insn.
(frv_software_interrupt): Moved to interrupts.c.
(frv_itrap): New interface. Call frv_queue_software_interrupt.
* mloop.in (@cpu@_parallel_write_init): set previous_vliw_pc.
(@cpu@_perform_writeback): New function.
(main loop): Call frv_process_interrupts.
* frv-sim.h (frvbf_write_next_vliw_addr_to_PCSR): Removed.
(frv_itrap): New interface.
(frv_interrupt_class): New enumeration.
(frv_interrupt_kind): New enumeration.
(struct frv_interrupt): New struct type.
(frv_interrupt_table): New table of interrupt information.
(FRV_INTERRUPT_QUEUE_SIZE): New macro.
(struct frv_interrupt_state): New struct type.
(frv_interrupt_state): New global variable.
(previous_vliw_pc): New global variable.
(frv_queue_software_interrupt): New function.
(frv_queue_program_interrupt): New function.
(frv_queue_interrupt): New function.
(frv_process_interrupts): New function.
(frv_program_interrupt): New function.
(frv_software_interrupt): New function.
(frv_program_or_software_interrupt): New function.
(frv_clear_interrupt_classes): New function.
* frv.c (frvbf_write_next_vliw_addr_to_PCSR): Removed.
* Makefile.in (SIM_OBJS): Add interrupts.o
* sem.c: Rebuild.
1999-09-25 Doug Evans <devans@casey.cygnus.com>
* cpu.h,cpuall.h,decode.c,sem.c: Rebuild.
Tue Sep 21 17:16:47 1999 Dave Brolley <brolley@cygnus.com>
* mloop.in (main loop): Determine last insn from scache entry.
* cpu.h: Rebuild.
* cpuall.h: Rebuild.
Tue Sep 14 14:21:31 1999 Dave Brolley <brolley@cygnus.com>
* frv-sim.h (frvbf_write_next_vliw_addr_to_PCSR): New flag.
(NECR_ELOS): Define as unshifted value.
(NECR_NEN): Define as unshifted value.
(NECR_VALID): Define as unshifted value.
(SET_NESR): Rewite to use post-write queue.
(SET_NESR_VALID): Rewite to operate on argument.
(SET_NESR_EAV): Rewite to operate on argument.
(SET_NESR_FR): Rewite to operate on argument.
(CLEAR_NESR_FR): Rewite to operate on argument.
(SET_NESR_DRN): Rewite to operate on argument.
(SET_NESR_SIZE): Rewite to operate on argument.
(SET_NESR_NEAN): Rewite to operate on argument.
(SET_NEEAR): Rewite to use post-write queue.
(SET_NE_FLAG): Rewite to use post-write queue.
(CLEAR_NE_FLAG): Rewite to use post-write queue.
* traps.c (frv_software_interrupt): Rewite to use post-write queue.
(frv_rett): Rewite to use post-write queue.
(next_available_nesr): Rewrite to use new macro interfaces.
(next_valid_nesr): Ditto.
(frvbf_check_non_excepting_load): Ditto.
(frvbf_check_recovering_store): Ditto.
(clear_nesr_neear): Ditto.
(clear_ne_flags): Ditto.
* mloop.in (main loop): Update PCSR with address of next VLIW insn
when flag is set.
* frv.c (frvbf_h_spr_get_handler): Shift register fields here now.
(frvbf_store_multiple_GR): Rewite to use post-write queue.
(frvbf_store_multiple_FRint): Rewite to use post-write queue.
(frvbf_store_multiple_CPR): Rewite to use post-write queue.
* Makefile.in (frv.o): Depend on cgen-par.h.
Fri Sep 10 17:03:15 1999 Dave Brolley <brolley@cygnus.com>
* frv-sim.h (frvbf_set_write_next_vliw_addr_to_LR): New function.
(frvbf_write_next_vliw_addr_to_LR): New flag.
* frv.c (frvbf_set_write_next_vliw_addr_to_LR): New function.
* mloop.in: Only take the first branch in a VLIW insn. Set LR to the
address of the next VLIW insn if flag is set.
* cpu.h,decode.c,sem.c: Rebuild.
Tue Sep 7 13:44:23 1999 Dave Brolley <brolley@cygnus.com>
* mloop.in: Limit parallel insns to MAX_PARALLEL_INSNS.
* sem.c: Rebuild.
1999-09-02 Doug Evans <devans@casey.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
1999-09-01 Doug Evans <devans@casey.cygnus.com>
* decode.c: Rebuild.
Mon Aug 30 17:54:57 1999 Dave Brolley <brolley@cygnus.com>
* traps.c (frv_rett): New function.
* frv.c (frvbf_h_spr_get_handler): Handle bpsr.
(frvbf_h_spr_set_handler): Handle bpsr.
(frvbf_h_bpsr_get_handler): New function.
(frvbf_h_bpsr_set_handler): New function.
* frv-sim.h (frv_rett): New function.
(frvbf_h_bpsr_get_handler): New function.
(frvbf_h_bpsr_set_handler): New function.
* mloop.in: Read actual packing bit.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
Tue Aug 31 16:04:37 1999 Dave Brolley <brolley@cygnus.com>
* traps.c (WANT_CPU): New macro.
(WANT_CPU_FRVBF): New macro.
(frvbf_check_recovering_store): Use registers for source and queue
writes.
* mloop.in: New main loop for parallel support.
(@cpu@_parallel_write_init): New function.
(@cpu@_parallel_write_queued): New function.
* frv-sim.h (set_icc_for_shift_left): New interface.
(set_icc_for_shift_right): New interface.
(frvbf_check_recovering_store): New interface.
* frv.c (set_icc_for_shift_left): Pass and return icc value.
(set_icc_for_shift_right): Pass and return icc value.
(frvbf_check_recovering_store): New interface.
* Makefile.in (FRV_OBJS): Add cgen-par.o.
(stamp-mloop): Add cgen parallel options.
(stamp-arch): Remove with-profile option.
(stamp-cpu): Add cgen parallel options.
* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
1999-08-28 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,sem.c: Rebuild.
Wed Aug 25 12:25:04 1999 Dave Brolley <brolley@cygnus.com>
* arch.h,cpu.h,decode.h,model.c,sem.c: Rebuild.
Thu Aug 19 17:59:00 1999 Dave Brolley <brolley@cygnus.com>
* configure.in: fr500 now the default model.
* configure: Regenerate.
* frv.c: Change frv-1 to frv-gen.
(frvbf_model_fr500_u_exec): New function.
* Makefile.in (stamp-cpu): Use 'mach=frv,fr500' to build decoder.
* mloop.in: Fix typos in comments.
* arch.c,arch.h,cpu.h,cpuall.h,decode.h,model.c,sem.c: Rebuild.
1999-08-17 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
1999-08-09 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
1999-08-04 Doug Evans <devans@casey.cygnus.com>
* cpu.h,cpuall.h,decode.c,model.c,sem.c: Rebuild.
Fri Jul 16 14:50:15 1999 Dave Brolley <brolley@cygnus.com>
* frv.c (frvbf_fetch_register): Use GDB register number macros.
(frvbf_store_register): Use GDB register number macros.
(frvbf_cut): New function.
* frv-sim.h (GR_REGNUM_MAX): New macro.
(FR_REGNUM_MAX): New macro.
(PC_REGNUM): New macro.
(LR_REGNUM): New macro.
(frvbf_cut): New function.
* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
1999-07-15 Stan Shebs <shebs@andros.cygnus.com>
* frv.c (frvbf_fetch_register): Add ability to get LR register,
add default for unhandled registers.
(frvbf_store_register): Add ability to set LR register.
1999-07-14 Stan Shebs <shebs@andros.cygnus.com>
* frv.c (frvbf_fetch_register, frvbf_store_register): Fill in.
(decode_gdb_dr_regnum): Remove, not used.
1999-07-13 Michael Meissner <meissner@cygnus.com>
* Makefile.in (SIM_EXTRA_FLAGS): Incorporate @sim_trapdump@.
* configure.in (--enable-sim-trapdump): New switch to make unknown
traps dump the register contents, instead of doing the trap thing.
* configure: Regenerate.
* frv-sim.h (TRAP_BREAKPOINT): Define as 81, so it can be used.
(TRAP_REGDUMP{1,2}): Define to provide register dumping support
temporarily.
* traps.h (toplevel): Include bfd.h, libiberity.h.
(frv_itrap): Add support for --enable-sim-trapdump and traps 2,3
dumping the registers.
Thu Jul 8 10:57:39 1999 Dave Brolley <brolley@cygnus.com>
* Makefile.in (SIM_EXTRA_LIBS): Removed. libm no longer needed.
Wed Jul 7 17:01:12 1999 Dave Brolley <brolley@cygnus.com>
* cpu.c,cpu.h,decode.c,model.c,sem.c: Rebuild.
Tue Jul 6 16:12:18 1999 Dave Brolley <brolley@cygnus.com>
* frv.c (frvbf_square_root_SF): Removed.
(frvbf_square_root_DF): Removed.
(frvbf_h_fr_double_get_handler): Removed.
(frvbf_h_fr_double_set_handler): Removed.
(frvbf_h_fr_int_get_handler): Removed.
(frvbf_h_fr_int_set_handler): Removed.
* frv-sim.h (frvbf_square_root_SF): Removed.
(frvbf_square_root_DF): Removed.
(frvbf_h_fr_double_get_handler): Removed.
(frvbf_h_fr_double_set_handler): Removed.
(frvbf_h_fr_int_get_handler): Removed.
(frvbf_h_fr_int_set_handler): Removed.
* decode.c,decode.h,model.c,sem.c: Rebuild.
1999-07-05 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (SIM_OBJS): Add cgen-fpu.o, cgen-accfp.o.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
* sim-if.c (sim_open): Initialize fpu.
* frv-sim.h (SETMEMSF,SETMEMDF): Delete.
* frv.c (frvbf_store_multiple_FRint): Replace frvbf_h_fr_int_get
with frvbf_h_fr_get.
Wed Jun 30 15:56:56 1999 Dave Brolley <brolley@cygnus.com>
* frv-sim.h (NESR_RANGE): New macro.
(NO_NESR): New macro.
(GET_NESR_VALID): New macro.
(next_ne_index): Removed.
* traps.c (next_available_nesr): New function.
(next_valid_nesr): New function.
(frvbf_check_non_excepting_load): Use next_available_nesr.
(frvbf_check_recovering_store): Use next_available_nesr and
next_valid_nesr.
(clear_nesr_neear): Use next_available_nesr and next_valid_nesr.
(frvbf_check_recovering_store): Only consider one matching register.
* sem.c: Rebuild.
Tue Jun 29 16:54:32 1999 Dave Brolley <brolley@cygnus.com>
* frv.c (frvbf_square_root_SF): New function.
(frvbf_square_root_DF): New function.
(frvbf_h_fr_double_get_handler): New function.
(frvbf_h_fr_double_set_handler): New function.
* frv-sim.h (frvbf_square_root_SF): New function.
(frvbf_square_root_DF): New function.
(frvbf_h_fr_double_get_handler): New function.
(frvbf_h_fr_double_set_handler): New function.
* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c: Rebuild.
1999-06-28 Dave Brolley <brolley@cygnus.com>
* decode.c,decode.h,model.c,sem.c: Regenerate.
Thu Jun 24 17:26:32 1999 Dave Brolley <brolley@cygnus.com>
* Makefile.in (SIM_EXTRA_LIBS): Add -lm.
* frv-sim.h (frvbf_h_fr_int_get_handler): New function.
(frvbf_h_fr_int_set_handler): New function.
(frvbf_store_multiple_FRint): New function.
(frvbf_square_root_SF): New function.
* frv.c (frvbf_h_fr_int_get_handler): New function.
(frvbf_h_fr_int_set_handler): New function.
(frvbf_store_multiple_FRint): New function.
(frvbf_square_root_SF): New function.
* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
1999-06-23 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (stamp-mloop): Delete -fast -pbb -switch args
to genmloop.sh. Pass -scache instead.
(mloop.o): Delete sem-switch.c dependency.
(sem-switch.c): Delete rule.
(stamp-cpu): Don't build sem-switch.c.
* sem-switch.c: Delete.
* mloop.in (xfull-exec-*): Fix call to execute.
* tconfig.in (WITH_SCACHE_PBB): Define as 0.
* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
Tue Jun 22 16:23:57 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,sem.c,sem-switch.c: Regenerate.
Mon Jun 21 17:34:10 1999 Dave Brolley <brolley@cygnus.com>
* mloop.in (execute): Force gr0 to zero before each insn.
* cpu.h,cpu.c,decode.c,sem.c,sem-switch.c: Regenerate.
1999-06-18 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
Fri Jun 18 17:49:23 1999 Dave Brolley <brolley@cygnus.com>
* frv.c (frvbf_h_gr_get_handler): New function.
(frvbf_h_gr_set_handler): New function:
(frvbf_store-multiple_GR): New function:
(frvbf_store-multiple_FR): New function:
(frvbf_store-multiple_CPR): New function:
* frv-sim.h (frvbf_h_gr_get_handler): New function.
(frvbf_h_gr_set_handler): New function:
(frvbf_store-multiple_GR): New function:
(frvbf_store-multiple_FR): New function:
(frvbf_store-multiple_CPR): New function:
* traps.c (frv_itrap): Implement proper syscalls interface.
* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Fri Jun 18 14:36:23 1999 Dave Brolley <brolley@cygnus.com>
* traps.c (frvbf_check_non_excepting_divide): New function.
(frvbf_check_recovering_store): New function.
(clear_nesr_neear): New function.
(clear_ne_flags): New function.
(frvbf_commit): New function.
* frv-sim.h (frvbf_check_non_excepting_divide): New function.
(frvbf_check_recovering_store): New function.
(clear_nesr_neear): New function.
(clear_ne_flags): New function.
(frvbf_commit): New function.
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
1999-06-16 Dave Brolley <brolley@cygnus.com>
* frv.c (frvbf_h_spr_get_handler): Handle SPR_NECR.
(frvbf_h_spr_set_handler): Handle SPR_NECR.
* traps.c (next_ne_index): New variable.
(frvbf_check_non_excepting_load): New function.
* frv-sim.h (NECR_ELOS): New macro.
(NECR_NEN): New macro.
(NECR_VALID): New macro.
(SET_NESR_VALID): New macro.
(SET_NESR_EAV): New macro.
(SET_NESR_FR): New macro.
(CLEAR_NESR_FR): New macro.
(SET_NESR_DRN): New macro.
(SET_NESR_SIZE): New macro.
(SET_NESR_NEAN): New macro.
(SET_NEEAR): New macro.
(GET_NE_FLAG): New macro.
(SET_NE_FLAG): New macro.
(CLEAR_NE_FLAG): New macro.
(frvbf_check_non_excepting_load): New function:
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Wed Jun 9 18:12:49 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
Tue Jun 8 18:13:51 1999 Dave Brolley <brolley@cygnus.com>
* frv.c (cr_logic): Correct andcr, nandcr, andncr and nandncr.
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Mon Jun 7 17:09:15 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
1999-06-07 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Thu Jun 3 17:33:31 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Wed Jun 2 17:50:21 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Tue Jun 1 17:58:53 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
Mon May 31 17:57:25 1999 Dave Brolley <brolley@cygnus.com>
* traps.c (frv_software_interrupt): Pass current_cpu to
frvbf_h_psr_esr_get.
(frv_software_interrupt): Calculate the new PC based on TBR.
* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
1999-05-31 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
Thu May 27 17:42:00 1999 Dave Brolley <brolley@cygnus.com>
* frv-sim.h (frvbf_h_cccr_get_handler): New function.
(frvbf_h_cccr_set_handler): New function.
(frvbf_scan_result): New function.
(frvbf_cr_logic): New function.
* frv.c (frvbf_h_cccr_get_handler): New function.
(frvbf_h_cccr_set_handler): New function.
(frvbf_scan_result): New function.
(frvbf_cr_logic): New function.
(cr_ops,cr_result,cr_logic): New table.
* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
1999-05-25 Dave Brolley <brolley@cygnus.com>
* frv.c (frvbf_h_spr_get_handler): Add support for TBR and PSR.
(frvbf_h_spr_set_handler): Add support for TBR and PSR.
(frv_psr_get_handler): New function.
(frv_psr_set_handler): New function.
(frv_tbr_get_handler): New function.
(frv_tbr_set_handler): New function.
(frvbf_h_ccr_get_handler): Add support for fCC.
(frvbf_h_ccr_set_handler): Add support for fCC.
* frv-sim.h (frv_psr_get_handler): New function.
(frv_psr_set_handler): New function.
(frv_tbr_get_handler): New function.
(frv_tbr_set_handler): New function.
* traps.c (frv_software_interrupt): Implement.
* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Thu May 20 16:39:27 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
1999-05-18 Dave Brolley <brolley@cygnus.com>
* frv.c: (frvbf_set_icc_for_shift_left): New function.
(frvbf_set_icc_for_shift_right): New function.
* frv-sim.h (frvbf_set_icc_for_shift_left): New function.
(frvbf_set_icc_for_shift_right): New function.
(SETMEMSF): New Macro.
(SETMEMDF): New Macro.
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Thu May 13 17:14:49 1999 Dave Brolley <brolley@cygnus.com>
* frv.c (frvbf_h_ccr_get_handler): New function.
(frvbf_h_ccr_set_handler): New function.
* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Tue May 11 16:13:15 1999 Dave Brolley <brolley@cygnus.com>
* frv-sim.h (frvbf_h_spr_get_handler,frvbf_h_spr_set_handler,
frvbf_h_isr_get_handler, frvbf_h_isr_set_handler): New functions.
* frv.c: Likewise.
* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
1999-05-10 Dave Brolley <brolley@cygnus.com>
* cpu.h,cpu.c,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
Thu May 6 16:48:21 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,sem.c,sem-switch.c: Regenerate.
* frv-sim.h (TRAP_SYSCALL): Define as 0x80.
Wed May 5 11:52:24 1999 Dave Brolley <brolley@cygnus.com>
* traps.c (frv_software_interrupt): New function.
(frv_itrap): New function.
* frv-sim.h (TRAP_SYSCALL): define as 0.
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Mon May 3 13:49:21 1999 Dave Brolley <brolley@cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
Thu Apr 29 17:37:06 1999 Dave Brolley <brolley@cygnus.com>
* Directory created.
libgloss/ChangeLog:
2002-06-11 Dave Brolley <brolley@redhat.com>
From Catherine Moore, Michael Meissner, Richard Sandiford:
* configure.in: Support frv*-*-*.
* frv/Makefile.in: New file.
* frv/configure: New file.
* frv/configure.in: New file.
* frv/crt0.S: New file.
* frv/fstat.c: New file.
* frv/getpid.c: New file.
* frv/isatty.c: New file.
* frv/kill.c: New file.
* frv/print.c: New file.
* frv/putnum.c: New file.
* frv/sbrk.c: New file.
* frv/sim-close.S: New file.
* frv/sim-exit.S: New file.
* frv/sim-inbyte.c: New file.
* frv/sim-lseek.S: New file.
* frv/sim-open.S: New file.
* frv/sim-read.S: New file.
* frv/sim-time.c: New file.
* frv/sim-unlink.S: New file.
* frv/sim-write.S: New file.
* frv/stat.c: New file.
[-- Attachment #3: frv.sim.patch.tgz --]
[-- Type: application/x-compressed, Size: 96986 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* [patch] New Target - Fujitsu FRV
@ 2002-06-12 11:55 Dave Brolley
2002-06-20 20:25 ` Andrew Cagney
2002-06-20 20:31 ` Andrew Cagney
0 siblings, 2 replies; 7+ messages in thread
From: Dave Brolley @ 2002-06-12 11:55 UTC (permalink / raw)
To: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 291 bytes --]
Hi,
Attached is a patch which adds gdb support for Fujitsu's FRV
architecture targeting frv-elf, including models for the FR400 and
FR500. This patch is part of a larger submission of bfd, gas, ld,
binutils, sim, gdb and newlib for the FRV by Red Hat.
Seeking approval to commit.
Dave
[-- Attachment #2: frv.gdb.ChangeLog --]
[-- Type: text/plain, Size: 287 bytes --]
gdb/ChangeLog:
2002-06-11 Dave Brolley <brolley@redhat.com>
From Stan Shebs, Jim Blandy, Mark Salter, Kevin Buettner:
* config/frv/frv.mt: New file.
* config/frv/frv.mt: tm-frv.h
* configure.tgt: Support frv-*-*.
* Makefile.in (frv-tdep.o): New target.
* frv-tdep.c: New file.
[-- Attachment #3: frv.gdb.patch.txt --]
[-- Type: text/plain, Size: 41218 bytes --]
Index: gdb/NEWS
===================================================================
RCS file: /cvs/src/src/gdb/NEWS,v
retrieving revision 1.73
diff -c -p -d -u -p -r1.73 NEWS
--- gdb/NEWS 31 May 2002 00:59:13 -0000 1.73
+++ gdb/NEWS 11 Jun 2002 20:44:57 -0000
@@ -35,6 +35,8 @@ National Semiconductor NS32000 (partial)
* New targets.
Atmel AVR avr*-*-*
+Fujitsu FRV architecture added by Red Hat frv*-*-*
+
* New native configurations
Index: gdb/Makefile.in
===================================================================
RCS file: /cvs/src/src/gdb/Makefile.in,v
retrieving revision 1.206
diff -c -p -d -u -p -r1.206 Makefile.in
--- gdb/Makefile.in 9 Jun 2002 15:45:42 -0000 1.206
+++ gdb/Makefile.in 10 Jun 2002 22:02:41 -0000
@@ -1473,6 +1473,9 @@ findvar.o: findvar.c $(defs_h) $(gdbcore
frame.o: frame.c $(defs_h) $(frame_h) $(target_h) $(value_h) $(inferior_h) \
$(regcache_h)
+frv-tdep.o: frv-tdep.c $(defs_h) $(inferior_h) $(symfile_h) $(gdbcore_h) \
+ $(arch_utils_h) $(regcache_h)
+
regcache.o: regcache.c $(defs_h) $(inferior_h) $(target_h) $(regcache_h)
fork-child.o: fork-child.c $(gdb_wait_h) $(defs_h) $(gdbcore_h) \
Index: gdb/configure.tgt
===================================================================
RCS file: /cvs/src/src/gdb/configure.tgt,v
retrieving revision 1.68
diff -c -p -d -u -p -r1.68 configure.tgt
--- gdb/configure.tgt 31 May 2002 00:59:13 -0000 1.68
+++ gdb/configure.tgt 10 Jun 2002 22:02:42 -0000
@@ -74,6 +74,7 @@ h8500-*-*) gdb_target=h8500 ;;
fr30-*-elf*) gdb_target=fr30 ;;
+frv-*-*) gdb_target=frv ;;
hppa*-*-bsd*) gdb_target=hppabsd ;;
hppa*-*-pro*) gdb_target=hppapro ;;
Index: gdb/frv-tdep.c
===================================================================
RCS file: gdb/frv-tdep.c
diff -N gdb/frv-tdep.c
--- gdb/frv-tdep.c 1 Jan 1970 00:00:00 -0000
+++ gdb/frv-tdep.c 10 Jun 2002 22:02:42 -0000
@@ -0,0 +1,1174 @@
+/* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
+ Copyright 1999 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#include "defs.h"
+#include "inferior.h"
+#include "symfile.h" /* for entry_point_address */
+#include "gdbcore.h"
+#include "arch-utils.h"
+#include "regcache.h"
+
+extern void _initialize_frv_tdep (void);
+
+static gdbarch_init_ftype frv_gdbarch_init;
+
+static gdbarch_register_name_ftype frv_register_name;
+static gdbarch_register_raw_size_ftype frv_register_raw_size;
+static gdbarch_register_virtual_size_ftype frv_register_virtual_size;
+static gdbarch_register_virtual_type_ftype frv_register_virtual_type;
+static gdbarch_register_byte_ftype frv_register_byte;
+static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc;
+static gdbarch_frame_chain_ftype frv_frame_chain;
+static gdbarch_frame_saved_pc_ftype frv_frame_saved_pc;
+static gdbarch_skip_prologue_ftype frv_skip_prologue;
+static gdbarch_frame_init_saved_regs_ftype frv_frame_init_saved_regs;
+static gdbarch_extract_return_value_ftype frv_extract_return_value;
+static gdbarch_extract_struct_value_address_ftype frv_extract_struct_value_address;
+static gdbarch_use_struct_convention_ftype frv_use_struct_convention;
+static gdbarch_frameless_function_invocation_ftype frv_frameless_function_invocation;
+static gdbarch_init_extra_frame_info_ftype stupid_useless_init_extra_frame_info;
+static gdbarch_store_return_value_ftype frv_store_return_value;
+static gdbarch_store_struct_return_ftype frv_store_struct_return;
+static gdbarch_push_arguments_ftype frv_push_arguments;
+static gdbarch_push_return_address_ftype frv_push_return_address;
+static gdbarch_pop_frame_ftype frv_pop_frame;
+static gdbarch_saved_pc_after_call_ftype frv_saved_pc_after_call;
+
+static void frv_pop_frame_regular (struct frame_info *frame);
+
+/* Register numbers. You can change these as needed, but don't forget
+ to update the simulator accordingly. */
+enum {
+ /* The total number of registers we know exist. */
+ frv_num_regs = 147,
+
+ /* Register numbers 0 -- 63 are always reserved for general-purpose
+ registers. The chip at hand may have less. */
+ first_gpr_regnum = 0,
+ sp_regnum = 1,
+ fp_regnum = 2,
+ struct_return_regnum = 3,
+ last_gpr_regnum = 63,
+
+ /* Register numbers 64 -- 127 are always reserved for floating-point
+ registers. The chip at hand may have less. */
+ first_fpr_regnum = 64,
+ last_fpr_regnum = 127,
+
+ /* Register numbers 128 on up are always reserved for special-purpose
+ registers. */
+ first_spr_regnum = 128,
+ pc_regnum = 128,
+ psr_regnum = 129,
+ ccr_regnum = 130,
+ cccr_regnum = 131,
+ tbr_regnum = 135,
+ brr_regnum = 136,
+ dbar0_regnum = 137,
+ dbar1_regnum = 138,
+ dbar2_regnum = 139,
+ dbar3_regnum = 140,
+ lr_regnum = 145,
+ lcr_regnum = 146,
+ last_spr_regnum = 146
+};
+
+static LONGEST frv_call_dummy_words[] =
+{0};
+
+
+/* The contents of this structure can only be trusted after we've
+ frv_frame_init_saved_regs on the frame. */
+struct frame_extra_info
+ {
+ /* The offset from our frame pointer to our caller's stack
+ pointer. */
+ int fp_to_callers_sp_offset;
+
+ /* Non-zero if we've saved our return address on the stack yet.
+ Zero if it's still sitting in the link register. */
+ int lr_saved_on_stack;
+ };
+
+
+/* A structure describing a particular variant of the FRV.
+ We allocate and initialize one of these structures when we create
+ the gdbarch object for a variant.
+
+ At the moment, all the FR variants we support differ only in which
+ registers are present; the portable code of GDB knows that
+ registers whose names are the empty string don't exist, so the
+ `register_names' array captures all the per-variant information we
+ need.
+
+ in the future, if we need to have per-variant maps for raw size,
+ virtual type, etc., we should replace register_names with an array
+ of structures, each of which gives all the necessary info for one
+ register. Don't stick parallel arrays in here --- that's so
+ Fortran. */
+struct gdbarch_tdep
+{
+ /* How many general-purpose registers does this variant have? */
+ int num_gprs;
+
+ /* How many floating-point registers does this variant have? */
+ int num_fprs;
+
+ /* How many hardware watchpoints can it support? */
+ int num_hw_watchpoints;
+
+ /* How many hardware breakpoints can it support? */
+ int num_hw_breakpoints;
+
+ /* Register names. */
+ char **register_names;
+};
+
+#define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch))
+
+
+/* Allocate a new variant structure, and set up default values for all
+ the fields. */
+static struct gdbarch_tdep *
+new_variant ()
+{
+ struct gdbarch_tdep *var;
+ int r;
+ char buf[20];
+
+ var = xmalloc (sizeof (*var));
+ memset (var, 0, sizeof (*var));
+
+ var->num_gprs = 64;
+ var->num_fprs = 64;
+ var->num_hw_watchpoints = 0;
+ var->num_hw_breakpoints = 0;
+
+ /* By default, don't supply any general-purpose or floating-point
+ register names. */
+ var->register_names = (char **) xmalloc (frv_num_regs * sizeof (char *));
+ for (r = 0; r < frv_num_regs; r++)
+ var->register_names[r] = "";
+
+ /* Do, however, supply default names for the special-purpose
+ registers. */
+ for (r = first_spr_regnum; r <= last_spr_regnum; ++r)
+ {
+ sprintf (buf, "x%d", r);
+ var->register_names[r] = xstrdup (buf);
+ }
+
+ var->register_names[pc_regnum] = "pc";
+ var->register_names[lr_regnum] = "lr";
+ var->register_names[lcr_regnum] = "lcr";
+
+ var->register_names[psr_regnum] = "psr";
+ var->register_names[ccr_regnum] = "ccr";
+ var->register_names[cccr_regnum] = "cccr";
+ var->register_names[tbr_regnum] = "tbr";
+
+ /* Debug registers. */
+ var->register_names[brr_regnum] = "brr";
+ var->register_names[dbar0_regnum] = "dbar0";
+ var->register_names[dbar1_regnum] = "dbar1";
+ var->register_names[dbar2_regnum] = "dbar2";
+ var->register_names[dbar3_regnum] = "dbar3";
+
+ return var;
+}
+
+
+/* Indicate that the variant VAR has NUM_GPRS general-purpose
+ registers, and fill in the names array appropriately. */
+static void
+set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
+{
+ int r;
+
+ var->num_gprs = num_gprs;
+
+ for (r = 0; r < num_gprs; ++r)
+ {
+ char buf[20];
+
+ sprintf (buf, "gr%d", r);
+ var->register_names[first_gpr_regnum + r] = xstrdup (buf);
+ }
+}
+
+
+/* Indicate that the variant VAR has NUM_FPRS floating-point
+ registers, and fill in the names array appropriately. */
+static void
+set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
+{
+ int r;
+
+ var->num_fprs = num_fprs;
+
+ for (r = 0; r < num_fprs; ++r)
+ {
+ char buf[20];
+
+ sprintf (buf, "fr%d", r);
+ var->register_names[first_fpr_regnum + r] = xstrdup (buf);
+ }
+}
+
+
+static char *
+frv_register_name (int reg)
+{
+ if (reg < 0)
+ return "?toosmall?";
+ if (reg >= frv_num_regs)
+ return "?toolarge?";
+
+ return CURRENT_VARIANT->register_names[reg];
+}
+
+
+static int
+frv_register_raw_size (int reg)
+{
+ return 4;
+}
+
+static int
+frv_register_virtual_size (int reg)
+{
+ return 4;
+}
+
+static struct type *
+frv_register_virtual_type (int reg)
+{
+ if (reg >= 64 && reg <= 127)
+ return builtin_type_float;
+ else
+ return builtin_type_int;
+}
+
+static int
+frv_register_byte (int reg)
+{
+ return (reg * 4);
+}
+
+static const unsigned char *
+frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp)
+{
+ static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
+ *lenp = sizeof (breakpoint);
+ return breakpoint;
+}
+
+static CORE_ADDR
+frv_frame_chain (struct frame_info *frame)
+{
+ CORE_ADDR saved_fp_addr;
+
+ if (frame->saved_regs && frame->saved_regs[fp_regnum] != 0)
+ saved_fp_addr = frame->saved_regs[fp_regnum];
+ else
+ /* Just assume it was saved in the usual place. */
+ saved_fp_addr = frame->frame;
+
+ return read_memory_integer (saved_fp_addr, 4);
+}
+
+static CORE_ADDR
+frv_frame_saved_pc (struct frame_info *frame)
+{
+ frv_frame_init_saved_regs (frame);
+
+ /* Perhaps the prologue analyzer recorded where it was stored.
+ (As of 14 Oct 2001, it never does.) */
+ if (frame->saved_regs && frame->saved_regs[pc_regnum] != 0)
+ return read_memory_integer (frame->saved_regs[pc_regnum], 4);
+
+ /* If the prologue analyzer tells us the link register was saved on
+ the stack, get it from there. */
+ if (frame->extra_info->lr_saved_on_stack)
+ return read_memory_integer (frame->frame + 8, 4);
+
+ /* Otherwise, it's still in LR.
+ However, if FRAME isn't the youngest frame, this is kind of
+ suspicious --- if this frame called somebody else, then its LR
+ has certainly been overwritten. */
+ if (! frame->next)
+ return read_register (lr_regnum);
+
+ /* By default, assume it's saved in the standard place, relative to
+ the frame pointer. */
+ return read_memory_integer (frame->frame + 8, 4);
+}
+
+
+/* Return true if REG is a caller-saves ("scratch") register,
+ false otherwise. */
+static int
+is_caller_saves_reg (int reg)
+{
+ return ((4 <= reg && reg <= 7)
+ || (14 <= reg && reg <= 15)
+ || (32 <= reg && reg <= 47));
+}
+
+
+/* Return true if REG is a callee-saves register, false otherwise. */
+static int
+is_callee_saves_reg (int reg)
+{
+ return ((16 <= reg && reg <= 31)
+ || (48 <= reg && reg <= 63));
+}
+
+
+/* Return true if REG is an argument register, false otherwise. */
+static int
+is_argument_reg (int reg)
+{
+ return (8 <= reg && reg <= 13);
+}
+
+
+/* Scan an FR-V prologue, starting at PC, until frame->PC.
+ If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
+ We assume FRAME's saved_regs array has already been allocated and cleared.
+ Return the first PC value after the prologue.
+
+ Note that, for unoptimized code, we almost don't need this function
+ at all; all arguments and locals live on the stack, so we just need
+ the FP to find everything. The catch: structures passed by value
+ have their addresses living in registers; they're never spilled to
+ the stack. So if you ever want to be able to get to these
+ arguments in any frame but the top, you'll need to do this serious
+ prologue analysis. */
+static CORE_ADDR
+frv_analyze_prologue (CORE_ADDR pc, struct frame_info *frame)
+{
+ /* When writing out instruction bitpatterns, we use the following
+ letters to label instruction fields:
+ P - The parallel bit. We don't use this.
+ J - The register number of GRj in the instruction description.
+ K - The register number of GRk in the instruction description.
+ I - The register number of GRi.
+ S - a signed imediate offset.
+ U - an unsigned immediate offset.
+
+ The dots below the numbers indicate where hex digit boundaries
+ fall, to make it easier to check the numbers. */
+
+ /* Non-zero iff we've seen the instruction that initializes the
+ frame pointer for this function's frame. */
+ int fp_set = 0;
+
+ /* If fp_set is non_zero, then this is the distance from
+ the stack pointer to frame pointer: fp = sp + fp_offset. */
+ int fp_offset = 0;
+
+ /* Total size of frame prior to any alloca operations. */
+ int framesize = 0;
+
+ /* The number of the general-purpose register we saved the return
+ address ("link register") in, or -1 if we haven't moved it yet. */
+ int lr_save_reg = -1;
+
+ /* Non-zero iff we've saved the LR onto the stack. */
+ int lr_saved_on_stack = 0;
+
+ /* If gr_saved[i] is non-zero, then we've noticed that general
+ register i has been saved at gr_sp_offset[i] from the stack
+ pointer. */
+ char gr_saved[64];
+ int gr_sp_offset[64];
+
+ memset (gr_saved, 0, sizeof (gr_saved));
+
+ while (! frame || pc < frame->pc)
+ {
+ LONGEST op = read_memory_integer (pc, 4);
+
+ /* The tests in this chain of ifs should be in order of
+ decreasing selectivity, so that more particular patterns get
+ to fire before less particular patterns. */
+
+ /* Setting the FP from the SP:
+ ori sp, 0, fp
+ P 000010 0100010 000001 000000000000 = 0x04881000
+ 0 111111 1111111 111111 111111111111 = 0x7fffffff
+ . . . . . . . .
+ We treat this as part of the prologue. */
+ if ((op & 0x7fffffff) == 0x04881000)
+ {
+ fp_set = 1;
+ fp_offset = 0;
+ }
+
+ /* Move the link register to the scratch register grJ, before saving:
+ movsg lr, grJ
+ P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
+ 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
+ . . . . . . . .
+ We treat this as part of the prologue. */
+ else if ((op & 0x7fffffc0) == 0x080d01c0)
+ {
+ int gr_j = op & 0x3f;
+
+ /* If we're moving it to a scratch register, that's fine. */
+ if (is_caller_saves_reg (gr_j))
+ lr_save_reg = gr_j;
+ /* Otherwise it's not a prologue instruction that we
+ recognize. */
+ else
+ break;
+ }
+
+ /* To save multiple callee-saves registers on the stack, at
+ offset zero:
+
+ std grK,@(sp,gr0)
+ P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
+ 0 000000 1111111 111111 111111 111111 = 0x01ffffff
+
+ stq grK,@(sp,gr0)
+ P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
+ 0 000000 1111111 111111 111111 111111 = 0x01ffffff
+ . . . . . . . .
+ We treat this as part of the prologue, and record the register's
+ saved address in the frame structure. */
+ else if ((op & 0x01ffffff) == 0x000c10c0
+ || (op & 0x01ffffff) == 0x000c1100)
+ {
+ int gr_k = ((op >> 25) & 0x3f);
+ int ope = ((op >> 6) & 0x3f);
+ int count;
+ int i;
+
+ /* Is it an std or an stq? */
+ if (ope == 0x03)
+ count = 2;
+ else
+ count = 4;
+
+ /* Is it really a callee-saves register? */
+ if (is_callee_saves_reg (gr_k))
+ {
+ for (i = 0; i < count; i++)
+ {
+ gr_saved[gr_k + i] = 1;
+ gr_sp_offset[gr_k + i] = 4 * i;
+ }
+ }
+ else
+ /* It's not a prologue instruction. */
+ break;
+ }
+
+ /* Adjusting the stack pointer. (The stack pointer is GR1.)
+ addi sp, S, sp
+ P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
+ 0 111111 1111111 111111 000000000000 = 0x7ffff000
+ . . . . . . . .
+ We treat this as part of the prologue. */
+ else if ((op & 0x7ffff000) == 0x02401000)
+ {
+ /* Sign-extend the twelve-bit field.
+ (Isn't there a better way to do this?) */
+ int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
+
+ framesize -= s;
+ }
+
+ /* Setting the FP to a constant distance from the SP:
+ addi sp, S, fp
+ P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
+ 0 111111 1111111 111111 000000000000 = 0x7ffff000
+ . . . . . . . .
+ We treat this as part of the prologue. */
+ else if ((op & 0x7ffff000) == 0x04401000)
+ {
+ /* Sign-extend the twelve-bit field.
+ (Isn't there a better way to do this?) */
+ int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
+ fp_set = 1;
+ fp_offset = s;
+ }
+
+ /* To spill an argument register to a scratch register:
+ ori GRi, 0, GRk
+ P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
+ 0 000000 1111111 000000 111111111111 = 0x01fc0fff
+ . . . . . . . .
+ For the time being, we treat this as a prologue instruction,
+ assuming that GRi is an argument register. This one's kind
+ of suspicious, because it seems like it could be part of a
+ legitimate body instruction. But we only come here when the
+ source info wasn't helpful, so we have to do the best we can.
+ Hopefully once GCC and GDB agree on how to emit line number
+ info for prologues, then this code will never come into play. */
+ else if ((op & 0x01fc0fff) == 0x00880000)
+ {
+ int gr_i = ((op >> 12) & 0x3f);
+
+ /* If the source isn't an arg register, then this isn't a
+ prologue instruction. */
+ if (! is_argument_reg (gr_i))
+ break;
+ }
+
+ /* To spill 16-bit values to the stack:
+ sthi GRk, @(fp, s)
+ P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
+ 0 000000 1111111 111111 000000000000 = 0x01fff000
+ . . . . . . . .
+ And for 8-bit values, we use STB instructions.
+ stbi GRk, @(fp, s)
+ P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
+ 0 000000 1111111 111111 000000000000 = 0x01fff000
+ . . . . . . . .
+ We check that GRk is really an argument register, and treat
+ all such as part of the prologue. */
+ else if ( (op & 0x01fff000) == 0x01442000
+ || (op & 0x01fff000) == 0x01402000)
+ {
+ int gr_k = ((op >> 25) & 0x3f);
+
+ if (! is_argument_reg (gr_k))
+ break; /* Source isn't an arg register. */
+ }
+
+ /* To save multiple callee-saves register on the stack, at a
+ non-zero offset:
+
+ stdi GRk, @(sp, s)
+ P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
+ 0 000000 1111111 111111 000000000000 = 0x01fff000
+ . . . . . . . .
+ stqi GRk, @(sp, s)
+ P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
+ 0 000000 1111111 111111 000000000000 = 0x01fff000
+ . . . . . . . .
+ We treat this as part of the prologue, and record the register's
+ saved address in the frame structure. */
+ else if ((op & 0x01fff000) == 0x014c1000
+ || (op & 0x01fff000) == 0x01501000)
+ {
+ int gr_k = ((op >> 25) & 0x3f);
+ int count;
+ int i;
+
+ /* Is it a stdi or a stqi? */
+ if ((op & 0x01fff000) == 0x014c1000)
+ count = 2;
+ else
+ count = 4;
+
+ /* Is it really a callee-saves register? */
+ if (is_callee_saves_reg (gr_k))
+ {
+ /* Sign-extend the twelve-bit field.
+ (Isn't there a better way to do this?) */
+ int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
+
+ for (i = 0; i < count; i++)
+ {
+ gr_saved[gr_k + i] = 1;
+ gr_sp_offset[gr_k + i] = s + (4 * i);
+ }
+ }
+ else
+ /* It's not a prologue instruction. */
+ break;
+ }
+
+ /* Storing any kind of integer register at any constant offset
+ from any other register.
+
+ st GRk, @(GRi, gr0)
+ P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
+ 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
+ . . . . . . . .
+ sti GRk, @(GRi, d12)
+ P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
+ 0 000000 1111111 000000 000000000000 = 0x01fc0000
+ . . . . . . . .
+ These could be almost anything, but a lot of prologue
+ instructions fall into this pattern, so let's decode the
+ instruction once, and then work at a higher level. */
+ else if (((op & 0x01fc0fff) == 0x000c0080)
+ || ((op & 0x01fc0000) == 0x01480000))
+ {
+ int gr_k = ((op >> 25) & 0x3f);
+ int gr_i = ((op >> 12) & 0x3f);
+ int offset;
+
+ /* Are we storing with gr0 as an offset, or using an
+ immediate value? */
+ if ((op & 0x01fc0fff) == 0x000c0080)
+ offset = 0;
+ else
+ offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
+
+ /* If the address isn't relative to the SP or FP, it's not a
+ prologue instruction. */
+ if (gr_i != sp_regnum && gr_i != fp_regnum)
+ break;
+
+ /* Saving the old FP in the new frame (relative to the SP). */
+ if (gr_k == fp_regnum && gr_i == sp_regnum)
+ ;
+
+ /* Saving callee-saves register(s) on the stack, relative to
+ the SP. */
+ else if (gr_i == sp_regnum
+ && is_callee_saves_reg (gr_k))
+ {
+ gr_saved[gr_k] = 1;
+ gr_sp_offset[gr_k] = offset;
+ }
+
+ /* Saving the scratch register holding the return address. */
+ else if (lr_save_reg != -1
+ && gr_k == lr_save_reg)
+ lr_saved_on_stack = 1;
+
+ /* Spilling int-sized arguments to the stack. */
+ else if (is_argument_reg (gr_k))
+ ;
+
+ /* It's not a store instruction we recognize, so this must
+ be the end of the prologue. */
+ else
+ break;
+ }
+
+ /* It's not any instruction we recognize, so this must be the end
+ of the prologue. */
+ else
+ break;
+
+ pc += 4;
+ }
+
+ if (frame)
+ {
+ frame->extra_info->lr_saved_on_stack = lr_saved_on_stack;
+
+ /* If we know the relationship between the stack and frame
+ pointers, record the addresses of the registers we noticed.
+ Note that we have to do this as a separate step at the end,
+ because instructions may save relative to the SP, but we need
+ their addresses relative to the FP. */
+ if (fp_set)
+ {
+ int i;
+
+ for (i = 0; i < 64; i++)
+ if (gr_saved[i])
+ frame->saved_regs[i] = (frame->frame
+ - fp_offset + gr_sp_offset[i]);
+
+ frame->extra_info->fp_to_callers_sp_offset = framesize - fp_offset;
+ }
+ }
+
+ return pc;
+}
+
+
+static CORE_ADDR
+frv_skip_prologue (CORE_ADDR pc)
+{
+ CORE_ADDR func_addr, func_end, new_pc;
+
+ new_pc = pc;
+
+ /* If the line table has entry for a line *within* the function
+ (i.e., not in the prologue, and not past the end), then that's
+ our location. */
+ if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
+ {
+ struct symtab_and_line sal;
+
+ sal = find_pc_line (func_addr, 0);
+
+ if (sal.line != 0 && sal.end < func_end)
+ {
+ new_pc = sal.end;
+ }
+ }
+
+ /* The FR-V prologue is at least five instructions long (twenty bytes).
+ If we didn't find a real source location past that, then
+ do a full analysis of the prologue. */
+ if (new_pc < pc + 20)
+ new_pc = frv_analyze_prologue (pc, 0);
+
+ return new_pc;
+}
+
+static void
+frv_frame_init_saved_regs (struct frame_info *frame)
+{
+ if (frame->saved_regs)
+ return;
+
+ frame_saved_regs_zalloc (frame);
+ frame->saved_regs[fp_regnum] = frame->frame;
+
+ /* Find the beginning of this function, so we can analyze its
+ prologue. */
+ {
+ CORE_ADDR func_addr, func_end;
+
+ if (find_pc_partial_function (frame->pc, NULL, &func_addr, &func_end))
+ frv_analyze_prologue (func_addr, frame);
+ }
+}
+
+/* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
+ EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
+ and TYPE is the type (which is known to be struct, union or array).
+
+ The frv returns all structs in memory. */
+
+static int
+frv_use_struct_convention (int gcc_p, struct type *type)
+{
+ return 1;
+}
+
+static void
+frv_extract_return_value (struct type *type, char *regbuf, char *valbuf)
+{
+ memcpy (valbuf, (regbuf
+ + frv_register_byte (8)
+ + (TYPE_LENGTH (type) < 4 ? 4 - TYPE_LENGTH (type) : 0)),
+ TYPE_LENGTH (type));
+}
+
+static CORE_ADDR
+frv_extract_struct_value_address (char *regbuf)
+{
+ return extract_address (regbuf + frv_register_byte (struct_return_regnum),
+ 4);
+}
+
+static void
+frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
+{
+ write_register (struct_return_regnum, addr);
+}
+
+static int
+frv_frameless_function_invocation (struct frame_info *frame)
+{
+ return frameless_look_for_prologue (frame);
+}
+
+static CORE_ADDR
+frv_saved_pc_after_call (struct frame_info *frame)
+{
+ return read_register (lr_regnum);
+}
+
+static void
+frv_init_extra_frame_info (int fromleaf, struct frame_info *frame)
+{
+ frame->extra_info = (struct frame_extra_info *)
+ frame_obstack_alloc (sizeof (struct frame_extra_info));
+ frame->extra_info->fp_to_callers_sp_offset = 0;
+ frame->extra_info->lr_saved_on_stack = 0;
+}
+
+#define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
+#define ROUND_DOWN(n,a) ((n) & ~((a)-1))
+
+static CORE_ADDR
+frv_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
+{
+ int argreg;
+ int argnum;
+ char *val;
+ char valbuf[4];
+ struct value *arg;
+ struct type *arg_type;
+ int len;
+ enum type_code typecode;
+ CORE_ADDR regval;
+ int stack_space;
+ int stack_offset;
+
+#if 0
+ printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
+ nargs, (int) sp, struct_return, struct_addr);
+#endif
+
+ stack_space = 0;
+ for (argnum = 0; argnum < nargs; ++argnum)
+ stack_space += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4);
+
+ stack_space -= (6 * 4);
+ if (stack_space > 0)
+ sp -= stack_space;
+
+ /* Make sure stack is dword aligned. */
+ sp = ROUND_DOWN (sp, 8);
+
+ stack_offset = 0;
+
+ argreg = 8;
+
+ if (struct_return)
+ write_register (struct_return_regnum, struct_addr);
+
+ for (argnum = 0; argnum < nargs; ++argnum)
+ {
+ arg = args[argnum];
+ arg_type = check_typedef (VALUE_TYPE (arg));
+ len = TYPE_LENGTH (arg_type);
+ typecode = TYPE_CODE (arg_type);
+
+ if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
+ {
+ store_address (valbuf, 4, VALUE_ADDRESS (arg));
+ typecode = TYPE_CODE_PTR;
+ len = 4;
+ val = valbuf;
+ }
+ else
+ {
+ val = (char *) VALUE_CONTENTS (arg);
+ }
+
+ while (len > 0)
+ {
+ int partial_len = (len < 4 ? len : 4);
+
+ if (argreg < 14)
+ {
+ regval = extract_address (val, partial_len);
+#if 0
+ printf(" Argnum %d data %x -> reg %d\n",
+ argnum, (int) regval, argreg);
+#endif
+ write_register (argreg, regval);
+ ++argreg;
+ }
+ else
+ {
+#if 0
+ printf(" Argnum %d data %x -> offset %d (%x)\n",
+ argnum, *((int *)val), stack_offset, (int) (sp + stack_offset));
+#endif
+ write_memory (sp + stack_offset, val, partial_len);
+ stack_offset += ROUND_UP(partial_len, 4);
+ }
+ len -= partial_len;
+ val += partial_len;
+ }
+ }
+ return sp;
+}
+
+static CORE_ADDR
+frv_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
+{
+ write_register (lr_regnum, CALL_DUMMY_ADDRESS ());
+ return sp;
+}
+
+static void
+frv_store_return_value (struct type *type, char *valbuf)
+{
+ int length = TYPE_LENGTH (type);
+ int reg8_offset = frv_register_byte (8);
+
+ if (length <= 4)
+ write_register_bytes (reg8_offset + (4 - length), valbuf, length);
+ else if (length == 8)
+ write_register_bytes (reg8_offset, valbuf, length);
+ else
+ internal_error (__FILE__, __LINE__,
+ "Don't know how to return a %d-byte value.", length);
+}
+
+static void
+frv_pop_frame (void)
+{
+ generic_pop_current_frame (frv_pop_frame_regular);
+}
+
+static void
+frv_pop_frame_regular (struct frame_info *frame)
+{
+ CORE_ADDR fp;
+ int regno;
+
+ fp = frame->frame;
+
+ frv_frame_init_saved_regs (frame);
+
+ write_register (pc_regnum, frv_frame_saved_pc (frame));
+ for (regno = 0; regno < frv_num_regs; ++regno)
+ {
+ if (frame->saved_regs[regno]
+ && regno != pc_regnum
+ && regno != sp_regnum)
+ {
+ write_register (regno,
+ read_memory_integer (frame->saved_regs[regno], 4));
+ }
+ }
+ write_register (sp_regnum, fp + frame->extra_info->fp_to_callers_sp_offset);
+ flush_cached_frames ();
+}
+
+
+static void
+frv_remote_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
+ CORE_ADDR *targ_addr, int *targ_len)
+{
+ *targ_addr = memaddr;
+ *targ_len = nr_bytes;
+}
+
+
+/* Hardware watchpoint / breakpoint support for the Venus (FR500)
+ and Robin (FR400). */
+
+int
+frv_check_watch_resources (int type, int cnt, int ot)
+{
+ struct gdbarch_tdep *var = CURRENT_VARIANT;
+
+ /* Watchpoints not supported on simulator. */
+ if (strcmp (target_shortname, "sim") == 0)
+ return 0;
+
+ if (type == bp_hardware_breakpoint)
+ {
+ if (var->num_hw_breakpoints == 0)
+ return 0;
+ else if (cnt <= var->num_hw_breakpoints)
+ return 1;
+ }
+ else
+ {
+ if (var->num_hw_watchpoints == 0)
+ return 0;
+ else if (ot)
+ return -1;
+ else if (cnt <= var->num_hw_watchpoints)
+ return 1;
+ }
+ return -1;
+}
+
+
+CORE_ADDR
+frv_stopped_data_address ()
+{
+ CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3;
+
+ brr = read_register (brr_regnum);
+ dbar0 = read_register (dbar0_regnum);
+ dbar1 = read_register (dbar1_regnum);
+ dbar2 = read_register (dbar2_regnum);
+ dbar3 = read_register (dbar3_regnum);
+
+ if (brr & (1<<11))
+ return dbar0;
+ else if (brr & (1<<10))
+ return dbar1;
+ else if (brr & (1<<9))
+ return dbar2;
+ else if (brr & (1<<8))
+ return dbar3;
+ else
+ return 0;
+}
+
+static struct gdbarch *
+frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+{
+ struct gdbarch *gdbarch;
+ struct gdbarch_tdep *var;
+
+ /* Check to see if we've already built an appropriate architecture
+ object for this executable. */
+ arches = gdbarch_list_lookup_by_info (arches, &info);
+ if (arches)
+ return arches->gdbarch;
+
+ /* Select the right tdep structure for this variant. */
+ var = new_variant ();
+ switch (info.bfd_arch_info->mach)
+ {
+ case bfd_mach_frv:
+ case bfd_mach_frvsimple:
+ case bfd_mach_fr500:
+ case bfd_mach_frvtomcat:
+ set_variant_num_gprs (var, 64);
+ set_variant_num_fprs (var, 64);
+ break;
+
+ case bfd_mach_fr400:
+ set_variant_num_gprs (var, 32);
+ set_variant_num_fprs (var, 32);
+ break;
+
+ default:
+ /* Never heard of this variant. */
+ return 0;
+ }
+
+ gdbarch = gdbarch_alloc (&info, var);
+
+ set_gdbarch_short_bit (gdbarch, 16);
+ set_gdbarch_int_bit (gdbarch, 32);
+ set_gdbarch_long_bit (gdbarch, 32);
+ set_gdbarch_long_long_bit (gdbarch, 64);
+ set_gdbarch_float_bit (gdbarch, 32);
+ set_gdbarch_double_bit (gdbarch, 64);
+ set_gdbarch_long_double_bit (gdbarch, 64);
+ set_gdbarch_ptr_bit (gdbarch, 32);
+
+ set_gdbarch_num_regs (gdbarch, frv_num_regs);
+ set_gdbarch_sp_regnum (gdbarch, sp_regnum);
+ set_gdbarch_fp_regnum (gdbarch, fp_regnum);
+ set_gdbarch_pc_regnum (gdbarch, pc_regnum);
+
+ set_gdbarch_register_name (gdbarch, frv_register_name);
+ set_gdbarch_register_size (gdbarch, 4);
+ set_gdbarch_register_bytes (gdbarch, frv_num_regs * 4);
+ set_gdbarch_register_byte (gdbarch, frv_register_byte);
+ set_gdbarch_register_raw_size (gdbarch, frv_register_raw_size);
+ set_gdbarch_max_register_raw_size (gdbarch, 4);
+ set_gdbarch_register_virtual_size (gdbarch, frv_register_virtual_size);
+ set_gdbarch_max_register_virtual_size (gdbarch, 4);
+ set_gdbarch_register_virtual_type (gdbarch, frv_register_virtual_type);
+
+ set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
+ set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
+
+ set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
+ set_gdbarch_frame_args_skip (gdbarch, 0);
+ set_gdbarch_frameless_function_invocation (gdbarch, frv_frameless_function_invocation);
+
+ set_gdbarch_saved_pc_after_call (gdbarch, frv_saved_pc_after_call);
+
+ set_gdbarch_frame_chain (gdbarch, frv_frame_chain);
+ set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
+ set_gdbarch_frame_saved_pc (gdbarch, frv_frame_saved_pc);
+ set_gdbarch_frame_args_address (gdbarch, default_frame_address);
+ set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
+
+ set_gdbarch_frame_init_saved_regs (gdbarch, frv_frame_init_saved_regs);
+
+ set_gdbarch_use_struct_convention (gdbarch, frv_use_struct_convention);
+ set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value);
+
+ set_gdbarch_store_struct_return (gdbarch, frv_store_struct_return);
+ set_gdbarch_store_return_value (gdbarch, frv_store_return_value);
+ set_gdbarch_extract_struct_value_address (gdbarch, frv_extract_struct_value_address);
+
+ /* Settings for calling functions in the inferior. */
+ set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
+ set_gdbarch_call_dummy_length (gdbarch, 0);
+ set_gdbarch_coerce_float_to_double (gdbarch,
+ standard_coerce_float_to_double);
+ set_gdbarch_push_arguments (gdbarch, frv_push_arguments);
+ set_gdbarch_push_return_address (gdbarch, frv_push_return_address);
+ set_gdbarch_pop_frame (gdbarch, frv_pop_frame);
+
+ set_gdbarch_call_dummy_p (gdbarch, 1);
+ set_gdbarch_call_dummy_words (gdbarch, frv_call_dummy_words);
+ set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (frv_call_dummy_words));
+ set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
+ set_gdbarch_init_extra_frame_info (gdbarch, frv_init_extra_frame_info);
+
+ /* Settings that should be unnecessary. */
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+
+ set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
+ set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
+ set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
+ set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
+ set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
+
+ set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
+ set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
+ set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
+ set_gdbarch_call_dummy_start_offset (gdbarch, 0);
+ set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
+ set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
+ set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
+ set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
+
+ set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
+
+ set_gdbarch_decr_pc_after_break (gdbarch, 0);
+ set_gdbarch_function_start_offset (gdbarch, 0);
+ set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not);
+
+ set_gdbarch_remote_translate_xfer_address
+ (gdbarch, frv_remote_translate_xfer_address);
+
+ /* Hardware watchpoint / breakpoint support. */
+ switch (info.bfd_arch_info->mach)
+ {
+ case bfd_mach_frv:
+ case bfd_mach_frvsimple:
+ case bfd_mach_fr500:
+ case bfd_mach_frvtomcat:
+ /* Venus-style hardware debugging support. */
+ var->num_hw_watchpoints = 4;
+ var->num_hw_breakpoints = 4;
+ break;
+
+ case bfd_mach_fr400:
+ /* Robin-style hardware debugging support. */
+ var->num_hw_watchpoints = 2;
+ var->num_hw_breakpoints = 4;
+ break;
+
+ default:
+ /* Otherwise, assume we don't have hardware debugging support. */
+ var->num_hw_watchpoints = 0;
+ var->num_hw_breakpoints = 0;
+ break;
+ }
+
+ return gdbarch;
+}
+
+void
+_initialize_frv_tdep (void)
+{
+ register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);
+
+ tm_print_insn = print_insn_frv;
+}
+
+\f
Index: gdb/config/frv/frv.mt
===================================================================
RCS file: gdb/config/frv/frv.mt
diff -N gdb/config/frv/frv.mt
--- gdb/config/frv/frv.mt 1 Jan 1970 00:00:00 -0000
+++ gdb/config/frv/frv.mt 10 Jun 2002 22:02:42 -0000
@@ -0,0 +1,5 @@
+# Target: Fujitsu FRV processor
+TDEPFILES= frv-tdep.o
+TM_FILE= tm-frv.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/frv/libsim.a
Index: gdb/config/frv/tm-frv.h
===================================================================
RCS file: gdb/config/frv/tm-frv.h
diff -N gdb/config/frv/tm-frv.h
--- gdb/config/frv/tm-frv.h 1 Jan 1970 00:00:00 -0000
+++ gdb/config/frv/tm-frv.h 10 Jun 2002 22:02:42 -0000
@@ -0,0 +1,62 @@
+/* Target definitions for the Fujitsu FR-V, for GDB, the GNU Debugger.
+ Copyright 1999 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+/* This target uses an architecture vector for most architecture methods. */
+
+#define GDB_MULTI_ARCH GDB_MULTI_ARCH_PARTIAL
+
+
+#define TARGET_HW_BREAK_LIMIT 4
+#define TARGET_HW_WATCH_LIMIT 4
+
+#define TARGET_HAS_HARDWARE_WATCHPOINTS
+
+#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
+ frv_check_watch_resources (type, cnt, ot)
+extern int frv_check_watch_resources (int type, int cnt, int ot);
+
+/* When a hardware watchpoint fires off the PC will be left at the
+ instruction which caused the watchpoint. It will be necessary for
+ GDB to step over the watchpoint. */
+
+/*#define HAVE_STEPPABLE_WATCHPOINT 1*/
+
+#define STOPPED_BY_WATCHPOINT(W) \
+ ((W).kind == TARGET_WAITKIND_STOPPED \
+ && (W).value.sig == TARGET_SIGNAL_TRAP \
+ && (frv_stopped_data_address() != ((CORE_ADDR)0)))
+extern CORE_ADDR frv_stopped_data_address(void);
+
+/* Use these macros for watchpoint insertion/deletion. */
+#define target_insert_watchpoint(addr, len, type) \
+ remote_insert_watchpoint (addr, len, type)
+#define target_remove_watchpoint(addr, len, type) \
+ remote_remove_watchpoint (addr, len, type)
+#define target_insert_hw_breakpoint(addr, shadow) \
+ remote_insert_hw_breakpoint (addr, 1)
+#define target_remove_hw_breakpoint(addr, shadow) \
+ remote_remove_hw_breakpoint (addr, 1)
+#define target_stopped_data_address() frv_stopped_data_address()
+
+/* These declarations should be in remote.h, no? */
+extern int remote_insert_watchpoint (CORE_ADDR addr, int len, int type);
+extern int remote_remove_watchpoint (CORE_ADDR addr, int len, int type);
+extern int remote_insert_hw_breakpoint (CORE_ADDR addr, int len);
+extern int remote_remove_hw_breakpoint (CORE_ADDR addr, int len);
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [patch] New Target - Fujitsu FRV
2002-06-12 11:55 Dave Brolley
@ 2002-06-20 20:25 ` Andrew Cagney
2002-06-21 13:27 ` Dave Brolley
2002-06-20 20:31 ` Andrew Cagney
1 sibling, 1 reply; 7+ messages in thread
From: Andrew Cagney @ 2002-06-20 20:25 UTC (permalink / raw)
To: Dave Brolley; +Cc: gdb-patches
Can I suggest adding yourself to the maintainers file (under write after
approval). Don't forget to post a changelog/patch of the change.
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [patch] New Target - Fujitsu FRV
2002-06-12 11:55 Dave Brolley
2002-06-20 20:25 ` Andrew Cagney
@ 2002-06-20 20:31 ` Andrew Cagney
2002-06-21 14:36 ` Dave Brolley
1 sibling, 1 reply; 7+ messages in thread
From: Andrew Cagney @ 2002-06-20 20:31 UTC (permalink / raw)
To: Dave Brolley; +Cc: gdb-patches
> +/*#define HAVE_STEPPABLE_WATCHPOINT 1*/
> +
> +#define STOPPED_BY_WATCHPOINT(W) \
> + ((W).kind == TARGET_WAITKIND_STOPPED \
> + && (W).value.sig == TARGET_SIGNAL_TRAP \
> + && (frv_stopped_data_address() != ((CORE_ADDR)0)))
> +extern CORE_ADDR frv_stopped_data_address(void);
> +
> +/* Use these macros for watchpoint insertion/deletion. */
> +#define target_insert_watchpoint(addr, len, type) \
> + remote_insert_watchpoint (addr, len, type)
> +#define target_remove_watchpoint(addr, len, type) \
> + remote_remove_watchpoint (addr, len, type)
> +#define target_insert_hw_breakpoint(addr, shadow) \
> + remote_insert_hw_breakpoint (addr, 1)
> +#define target_remove_hw_breakpoint(addr, shadow) \
> + remote_remove_hw_breakpoint (addr, 1)
> +#define target_stopped_data_address() frv_stopped_data_address()
> +
> +/* These declarations should be in remote.h, no? */
> +extern int remote_insert_watchpoint (CORE_ADDR addr, int len, int type);
> +extern int remote_remove_watchpoint (CORE_ADDR addr, int len, int type);
> +extern int remote_insert_hw_breakpoint (CORE_ADDR addr, int len);
> +extern int remote_remove_hw_breakpoint (CORE_ADDR addr, int len);
Sigh! Another target and still the hardware breakpoint problem isn't
fixed. I did some digging and I note you are not the author here :-)
> +SIM_OBS = remote-sim.o
> +SIM = ../sim/frv/libsim.a
For the moment leave these out, but otherwize approved.
Once committed, can you please check
http://sources.redhat.com/gdb/current/ari/ for anything identifed (at
the page top) from these new files.
Can you also try building with --enable-gdb-build-warnings=,-Werror.
Fixes related to both of these are considered obvious.
enjoy,
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [patch] New Target - Fujitsu FRV
2002-06-20 20:31 ` Andrew Cagney
@ 2002-06-21 14:36 ` Dave Brolley
2002-06-21 14:48 ` Andrew Cagney
0 siblings, 1 reply; 7+ messages in thread
From: Dave Brolley @ 2002-06-21 14:36 UTC (permalink / raw)
To: Andrew Cagney; +Cc: gdb-patches
Andrew Cagney wrote:
> >
> > +SIM_OBS = remote-sim.o
> > +SIM = ../sim/frv/libsim.a
>
> For the moment leave these out, but otherwize approved.
ok -- it's committed.
> Once committed, can you please check
> http://sources.redhat.com/gdb/current/ari/ for anything identifed (at
> the page top) from these new files.
Nothing showed up (yet). Does it take some period of time for possible
problems to show up?
> Can you also try building with --enable-gdb-build-warnings=,-Werror.
No additional warnings/errors generated.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [patch] New Target - Fujitsu FRV
2002-06-21 14:36 ` Dave Brolley
@ 2002-06-21 14:48 ` Andrew Cagney
0 siblings, 0 replies; 7+ messages in thread
From: Andrew Cagney @ 2002-06-21 14:48 UTC (permalink / raw)
To: Dave Brolley; +Cc: gdb-patches
> Andrew Cagney wrote:
>
>
>> >
>> > +SIM_OBS = remote-sim.o
>> > +SIM = ../sim/frv/libsim.a
>
>>
>> For the moment leave these out, but otherwize approved.
>
>
> ok -- it's committed.
>
>
>> Once committed, can you please check
>> http://sources.redhat.com/gdb/current/ari/ for anything identifed (at
>> the page top) from these new files.
>
>
> Nothing showed up (yet). Does it take some period of time for possible
> problems to show up?
Unfortunatly it takes 24 hours, if something does show up, I'll soon let
you know. (Things to do today includes proposing a gdb_style.sh script
that did the equivalent checks to the ARI.)
>> Can you also try building with --enable-gdb-build-warnings=,-Werror.
>
>
> No additional warnings/errors generated.
ok!
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2002-06-21 21:48 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2002-06-12 12:31 [patch] New Target - Fujitsu FRV Dave Brolley
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2002-06-12 11:55 Dave Brolley
2002-06-20 20:25 ` Andrew Cagney
2002-06-21 13:27 ` Dave Brolley
2002-06-20 20:31 ` Andrew Cagney
2002-06-21 14:36 ` Dave Brolley
2002-06-21 14:48 ` Andrew Cagney
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