Re: [PATCH] sim: riscv: fix build breakage with rvv changes

[Vineet Gupta <vineetg@rivosinc.com>]

On 10/28/21 7:59 PM, Nelson Chu wrote:
> Also send this patch to gdb mailing since there should be the right
> place for the issues of gdb and sim.

Ok will do.

> I'm going to move the rvv stuff from the integration branch back to
> the mainline, so we should need this in the mainline later.  But
> neither am I the developer or the maintainer of gdb, so we need the
> gdb experts' help.

Technically this change is simply matching the function prototype that 
got changed as part of that rvv update. Since this is not mainline I 
think gdb guys might hand wave as not their problem. Anyhow I'll send it 
over and see what comes back. I presume riscv binutils/gdb still work 
out of unified tree and branches ? So it should build off of integration 
branch too.

-Vineet

>
> Thanks
> Nelson
>
> On Fri, Oct 29, 2021 at 4:54 AM Vineet Gupta <vineetg@rivosinc.com> wrote:
>> The vector changes on binutils-integration-branch missed updates
>> to sim causing build failure when build sim/gdb.
>>
>> This patch is only for user/riscv/binutils-integration-branch
>>
>> Fixes: 144cceb058e "(RISC-V/rvv: Add rvv v0.10 instructions.)"
>> Reported-by: Dylan Reid <dylan@rivosinc.com>
>> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
>> ---
>>   sim/riscv/ChangeLog-2021 | 4 ++++
>>   sim/riscv/sim-main.c     | 3 ++-
>>   2 files changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/sim/riscv/ChangeLog-2021 b/sim/riscv/ChangeLog-2021
>> index e9aa74490f12..420b1867913c 100644
>> --- a/sim/riscv/ChangeLog-2021
>> +++ b/sim/riscv/ChangeLog-2021
>> @@ -1,3 +1,7 @@
>> +2021-20-28  Vineet Gupta  <vineetg@revosinc.com>
>> +
>> +       * sim-main.c (step_once): Fix match_func call per gas changes.
>> +
>>   2021-07-01  Mike Frysinger  <vapier@gentoo.org>
>>
>>          * configure: Regenerate.
>> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
>> index 0faf9395ae52..9b4f7c6c5aad 100644
>> --- a/sim/riscv/sim-main.c
>> +++ b/sim/riscv/sim-main.c
>> @@ -956,6 +956,7 @@ void step_once (SIM_CPU *cpu)
>>     sim_cia pc = cpu->pc;
>>     const struct riscv_opcode *op;
>>     int xlen = RISCV_XLEN (cpu);
>> +  const char *error = NULL;
>>
>>     if (TRACE_ANY_P (cpu))
>>       trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
>> @@ -985,7 +986,7 @@ void step_once (SIM_CPU *cpu)
>>     for (; op->name; op++)
>>       {
>>         /* Does the opcode match?  */
>> -      if (! op->match_func (op, iw))
>> +      if (! op->match_func (op, iw, 0, /* check_constraints */ &error))
>>          continue;
>>         /* Is this a pseudo-instruction and may we print it as such?  */
>>         if (op->pinfo & INSN_ALIAS)
>> --
>> 2.30.2
>>