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[24.4.73.83]) by smtp.gmail.com with ESMTPSA id g4sm2774169pfv.195.2021.10.28.20.19.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Oct 2021 20:19:41 -0700 (PDT) Subject: Re: [PATCH] sim: riscv: fix build breakage with rvv changes To: Nelson Chu , gdb-patches@sourceware.org References: <20211028205408.2228904-1-vineetg@rivosinc.com> From: Vineet Gupta Message-ID: <394713e5-9501-74a9-1e99-f8467ede2135@rivosinc.com> Date: Thu, 28 Oct 2021 20:19:39 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng , Dylan Reid , Binutils Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" On 10/28/21 7:59 PM, Nelson Chu wrote: > Also send this patch to gdb mailing since there should be the right > place for the issues of gdb and sim. Ok will do. > I'm going to move the rvv stuff from the integration branch back to > the mainline, so we should need this in the mainline later. But > neither am I the developer or the maintainer of gdb, so we need the > gdb experts' help. Technically this change is simply matching the function prototype that got changed as part of that rvv update. Since this is not mainline I think gdb guys might hand wave as not their problem. Anyhow I'll send it over and see what comes back. I presume riscv binutils/gdb still work out of unified tree and branches ? So it should build off of integration branch too. -Vineet > > Thanks > Nelson > > On Fri, Oct 29, 2021 at 4:54 AM Vineet Gupta wrote: >> The vector changes on binutils-integration-branch missed updates >> to sim causing build failure when build sim/gdb. >> >> This patch is only for user/riscv/binutils-integration-branch >> >> Fixes: 144cceb058e "(RISC-V/rvv: Add rvv v0.10 instructions.)" >> Reported-by: Dylan Reid >> Signed-off-by: Vineet Gupta >> --- >> sim/riscv/ChangeLog-2021 | 4 ++++ >> sim/riscv/sim-main.c | 3 ++- >> 2 files changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/sim/riscv/ChangeLog-2021 b/sim/riscv/ChangeLog-2021 >> index e9aa74490f12..420b1867913c 100644 >> --- a/sim/riscv/ChangeLog-2021 >> +++ b/sim/riscv/ChangeLog-2021 >> @@ -1,3 +1,7 @@ >> +2021-20-28 Vineet Gupta >> + >> + * sim-main.c (step_once): Fix match_func call per gas changes. >> + >> 2021-07-01 Mike Frysinger >> >> * configure: Regenerate. >> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c >> index 0faf9395ae52..9b4f7c6c5aad 100644 >> --- a/sim/riscv/sim-main.c >> +++ b/sim/riscv/sim-main.c >> @@ -956,6 +956,7 @@ void step_once (SIM_CPU *cpu) >> sim_cia pc = cpu->pc; >> const struct riscv_opcode *op; >> int xlen = RISCV_XLEN (cpu); >> + const char *error = NULL; >> >> if (TRACE_ANY_P (cpu)) >> trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu), >> @@ -985,7 +986,7 @@ void step_once (SIM_CPU *cpu) >> for (; op->name; op++) >> { >> /* Does the opcode match? */ >> - if (! op->match_func (op, iw)) >> + if (! op->match_func (op, iw, 0, /* check_constraints */ &error)) >> continue; >> /* Is this a pseudo-instruction and may we print it as such? */ >> if (op->pinfo & INSN_ALIAS) >> -- >> 2.30.2 >>