Re: [PATCH] sim: riscv: fix build breakage with rvv changes

[Vineet Gupta <vineetg@rivosinc.com>]

ping

On 10/29/21 12:28 PM, Vineet Gupta wrote:
> changes to gas for riscv vector extensions need to be propagated to sim
> otherwise gdb fails to build on users/riscv/binutils-integration-branch
> 
> This patch currently applies to that branch.
> 
> Fixes: 144cceb058e "(RISC-V/rvv: Add rvv v0.10 instructions.)"
> Reported-by: Dylan Reid <dylan@rivosinc.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> ---
>   sim/riscv/ChangeLog-2021 | 4 ++++
>   sim/riscv/sim-main.c     | 3 ++-
>   2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/sim/riscv/ChangeLog-2021 b/sim/riscv/ChangeLog-2021
> index e9aa74490f12..9ced6773bdd6 100644
> --- a/sim/riscv/ChangeLog-2021
> +++ b/sim/riscv/ChangeLog-2021
> @@ -1,3 +1,7 @@
> +2021-20-28  Vineet Gupta  <vineetg@rivosinc.com>
> +
> +	* sim-main.c (step_once): Fix match_func call per gas changes.
> +
>   2021-07-01  Mike Frysinger  <vapier@gentoo.org>
>   
>   	* configure: Regenerate.
> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
> index 0faf9395ae52..9b4f7c6c5aad 100644
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
> @@ -956,6 +956,7 @@ void step_once (SIM_CPU *cpu)
>     sim_cia pc = cpu->pc;
>     const struct riscv_opcode *op;
>     int xlen = RISCV_XLEN (cpu);
> +  const char *error = NULL;
>   
>     if (TRACE_ANY_P (cpu))
>       trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
> @@ -985,7 +986,7 @@ void step_once (SIM_CPU *cpu)
>     for (; op->name; op++)
>       {
>         /* Does the opcode match?  */
> -      if (! op->match_func (op, iw))
> +      if (! op->match_func (op, iw, 0, /* check_constraints */ &error))
>   	continue;
>         /* Is this a pseudo-instruction and may we print it as such?  */
>         if (op->pinfo & INSN_ALIAS)
>