[PATCH 3/4] sim/mips: Deliver the reserved instruction exception

[Sebastian Huber <sebastian.huber@embedded-brains.de>]

The ReservedInstruction and CoProcessorUnusable cases of
signal_exception() compute CAUSE, SR and EPC and set PC to the exception
handler address, and then assign PC = EPC, which discards all of it.
The client resumes on the faulting instruction rather than in its
handler, so it raises the same exception again and never advances.  The
address error cases immediately above deliberately do not do this and
say so in a comment.

The consequence is that a target which handles the exception never runs.
A compiler emits rdhwr to read the thread pointer for every access to a
thread-local object on every MIPS target, because the instruction exists
since MIPS32r2 and the operating system is expected to emulate it where
the processor lacks it.  The R3900 lacks it.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 sim/mips/interp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index a2757ec5ef7..5dbd1482b99 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1992,7 +1992,8 @@ signal_exception (SIM_DESC sd,
 
        case ReservedInstruction:
        case CoProcessorUnusable:
-	 PC = EPC;
+	 /* Leave PC at the exception handler address.  This allows emulating
+	    an instruction the CPU lacks.  */
 	 sim_engine_halt (SD, CPU, NULL, PC,
 			  sim_stopped, SIM_SIGILL);
 
-- 
2.51.0