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h=From:To:Date:Message-ID:MIME-Version; b=VG/hRaInPoUOVPo+cGGcWMgFjrwha4p6udZ84rjs3od7M2ApcyS0IPgWwUbij3IPC En9tFt3WgL395hNh79RAX2XnURK/AUZqkGBz5UUwThgwpI5D1jyO4VRRcldSz+kyHi B8IzhIDW7dawTvMRiORfv7/3Kqj01CwbBdGex/seWKRS43S7rDd0TBRTA7/BeT6GIB HG3sKxMpSjUkb1QjU76Wk5hjm0Swv3N5/mw6JCyItshbkc3XsJEVFtwtaqyC/q3F/x YrMlkvVjQIDqR8H+V/tImvW4eZ6RRuc7qiqMEtE98vvwxXIeX6OZNjm8Z8R4uR3Z0V gmo6Vd0dSwncg== X-Virus-Scanned: amavis at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id lIsUTMZgZCfH for ; Mon, 17 Aug 2026 01:44:06 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [10.10.171.14]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 4C554480074 for ; Mon, 17 Aug 2026 01:44:06 +0200 (CEST) From: Sebastian Huber To: gdb-patches@sourceware.org Subject: [PATCH 3/4] sim/mips: Deliver the reserved instruction exception Date: Mon, 17 Aug 2026 01:43:55 +0200 Message-ID: <20260816234357.278358-4-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260816234357.278358-1-sebastian.huber@embedded-brains.de> References: <20260816234357.278358-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.46.172.3] X-Virus-Scanned: Clear (ClamAV 1.4.3/28094/Sun Aug 16 08:26:19 2026) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org The ReservedInstruction and CoProcessorUnusable cases of signal_exception() compute CAUSE, SR and EPC and set PC to the exception handler address, and then assign PC =3D EPC, which discards all of it. The client resumes on the faulting instruction rather than in its handler, so it raises the same exception again and never advances. The address error cases immediately above deliberately do not do this and say so in a comment. The consequence is that a target which handles the exception never runs. A compiler emits rdhwr to read the thread pointer for every access to a thread-local object on every MIPS target, because the instruction exists since MIPS32r2 and the operating system is expected to emulate it where the processor lacks it. The R3900 lacks it. Signed-off-by: Sebastian Huber --- sim/mips/interp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sim/mips/interp.c b/sim/mips/interp.c index a2757ec5ef7..5dbd1482b99 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -1992,7 +1992,8 @@ signal_exception (SIM_DESC sd, =20 case ReservedInstruction: case CoProcessorUnusable: - PC =3D EPC; + /* Leave PC at the exception handler address. This allows emulating + an instruction the CPU lacks. */ sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGILL); =20 --=20 2.51.0