* [PATCH v13 1/2] gdb: mips: Apply coding guidelines
2025-06-04 12:38 [PATCH v13 0/2] gdb: mips: Add MIPSR6 support Jovan Dmitrovic
@ 2025-06-04 12:39 ` Jovan Dmitrovic
2026-09-17 11:21 ` Maciej W. Rozycki
2025-06-04 12:39 ` [PATCH v13 2/2] gdb: mips: Add MIPSR6 support Jovan Dmitrovic
1 sibling, 1 reply; 5+ messages in thread
From: Jovan Dmitrovic @ 2025-06-04 12:39 UTC (permalink / raw)
To: gdb-patches
Cc: Djordje Todorovic, Milica Matic, Maciej W . Rozycki, Jovan Dmitrovic
From: Milica Matic <milica.matic@htecgroup.com>
Format mips-tdep.c code as described on links:
https://sourceware.org/gdb/wiki/Internals%20GDB-C-Coding-Standards
https://www.gnu.org/prep/standards/standards.html#Comments
Signed-off-by: Milica Matic <milica.matic@htecgroup.com>
Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com>
---
gdb/mips-tdep.c | 315 ++++++++++++++++++++++++++++--------------------
1 file changed, 184 insertions(+), 131 deletions(-)
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index c64cd47c8b6..48284abdd73 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -76,8 +76,8 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
static void mips_print_float_info (struct gdbarch *, struct ui_file *,
const frame_info_ptr &, const char *);
-/* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
-/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
+/* A useful bit in the CP0 status register (MIPS_PS_REGNUM).
+ This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
#define ST0_FR (1 << 26)
/* The sizes of floating point registers. */
@@ -1076,21 +1076,29 @@ mips_register_type (struct gdbarch *gdbarch, int regnum)
else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
&& rawnum >= MIPS_FIRST_EMBED_REGNUM
&& rawnum <= MIPS_LAST_EMBED_REGNUM)
- /* The pseudo/cooked view of the embedded registers is always
- 32-bit. The raw view is handled below. */
- return builtin_type (gdbarch)->builtin_int32;
+ {
+ /* The pseudo/cooked view of the embedded registers is always
+ 32-bit. The raw view is handled below. */
+ return builtin_type (gdbarch)->builtin_int32;
+ }
else if (tdep->mips64_transfers_32bit_regs_p)
- /* The target, while possibly using a 64-bit register buffer,
- is only transferring 32-bits of each integer register.
- Reflect this in the cooked/pseudo (ABI) register value. */
- return builtin_type (gdbarch)->builtin_int32;
+ {
+ /* The target, while possibly using a 64-bit register buffer,
+ is only transferring 32-bits of each integer register.
+ Reflect this in the cooked/pseudo (ABI) register value. */
+ return builtin_type (gdbarch)->builtin_int32;
+ }
else if (mips_abi_regsize (gdbarch) == 4)
- /* The ABI is restricted to 32-bit registers (the ISA could be
- 32- or 64-bit). */
- return builtin_type (gdbarch)->builtin_int32;
+ {
+ /* The ABI is restricted to 32-bit registers (the ISA could be
+ 32- or 64-bit). */
+ return builtin_type (gdbarch)->builtin_int32;
+ }
else
- /* 64-bit ABI. */
- return builtin_type (gdbarch)->builtin_int64;
+ {
+ /* 64-bit ABI. */
+ return builtin_type (gdbarch)->builtin_int64;
+ }
}
}
@@ -1598,8 +1606,10 @@ mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
int cond;
if (fcsr == -1)
- /* No way to handle; it'll most likely trap anyway. */
- return pc;
+ {
+ /* No way to handle; it'll most likely trap anyway. */
+ return pc;
+ }
fcs = regcache_raw_get_unsigned (regcache, fcsr);
cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
@@ -1631,10 +1641,10 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
{
if (!is_octeon (gdbarch))
return 0;
- /* BBIT0 is encoded as LWC2: 110 010. */
- /* BBIT032 is encoded as LDC2: 110 110. */
- /* BBIT1 is encoded as SWC2: 111 010. */
- /* BBIT132 is encoded as SDC2: 111 110. */
+ /* BBIT0 is encoded as LWC2: 110 010.
+ BBIT032 is encoded as LDC2: 110 110.
+ BBIT1 is encoded as SWC2: 111 010.
+ BBIT132 is encoded as SDC2: 111 110. */
if (op == 50 || op == 54 || op == 58 || op == 62)
return 1;
return 0;
@@ -1652,12 +1662,11 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
int op;
inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
op = itype_op (inst);
- if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch
- instruction. */
+ if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction. */
{
if (op >> 2 == 5)
- /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
{
+ /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
switch (op & 0x03)
{
case 0: /* BEQL */
@@ -1673,20 +1682,26 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
}
}
else if (op == 17 && itype_rs (inst) == 8)
- /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
- pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);
+ {
+ /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
+ pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);
+ }
else if (op == 17 && itype_rs (inst) == 9
&& (itype_rt (inst) & 2) == 0)
- /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
- pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);
+ {
+ /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
+ pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);
+ }
else if (op == 17 && itype_rs (inst) == 10
&& (itype_rt (inst) & 2) == 0)
- /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
- pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);
+ {
+ /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
+ pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);
+ }
else if (op == 29)
- /* JALX: 011101 */
- /* The new PC will be alternate mode. */
{
+ /* JALX: 011101
+ The new PC will be alternate mode. */
unsigned long reg;
reg = jtype_target (inst) << 2;
@@ -1700,27 +1715,33 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
branch_if = op == 58 || op == 62;
bit = itype_rt (inst);
- /* Take into account the *32 instructions. */
if (op == 54 || op == 62)
- bit += 32;
+ {
+ /* Take into account the *32 instructions. */
+ bit += 32;
+ }
if (((regcache_raw_get_signed (regcache,
itype_rs (inst)) >> bit) & 1)
== branch_if)
pc += mips32_relative_offset (inst) + 4;
else
- pc += 8; /* After the delay slot. */
+ {
+ /* After the delay slot. */
+ pc += 8;
+ }
}
+
else
pc += 4; /* Not a branch, next instruction is easy. */
}
else
- { /* This gets way messy. */
-
- /* Further subdivide into SPECIAL, REGIMM and other. */
+ {
+ /* This gets way messy.
+ Further subdivide into SPECIAL, REGIMM and other. */
switch (op & 0x07) /* Extract bits 28,27,26. */
{
- case 0: /* SPECIAL */
+ case 0: /* SPECIAL */
op = rtype_funct (inst);
switch (op)
{
@@ -1729,7 +1750,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
/* Set PC to that address. */
pc = regcache_raw_get_signed (regcache, rtype_rs (inst));
break;
- case 12: /* SYSCALL */
+ case 12: /* SYSCALL */
{
mips_gdbarch_tdep *tdep
= gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
@@ -1744,10 +1765,10 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
pc += 4;
}
- break; /* end SPECIAL */
- case 1: /* REGIMM */
+ break; /* end SPECIAL */
+ case 1: /* REGIMM */
{
- op = itype_rt (inst); /* Branch condition. */
+ op = itype_rt (inst); /* branch condition */
switch (op)
{
case 0: /* BLTZ */
@@ -1758,7 +1779,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)
pc += mips32_relative_offset (inst) + 4;
else
- pc += 8; /* After the delay slot. */
+ pc += 8; /* after the delay slot */
break;
case 1: /* BGEZ */
case 3: /* BGEZL */
@@ -1767,7 +1788,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0)
pc += mips32_relative_offset (inst) + 4;
else
- pc += 8; /* After the delay slot. */
+ pc += 8; /* after the delay slot */
break;
case 0x1c: /* BPOSGE32 */
case 0x1e: /* BPOSGE64 */
@@ -1778,8 +1799,10 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
int dspctl = mips_regnum (gdbarch)->dspctl;
if (dspctl == -1)
- /* No way to handle; it'll most likely trap anyway. */
- break;
+ {
+ /* No way to handle; it'll most likely trap anyway. */
+ break;
+ }
if ((regcache_raw_get_unsigned (regcache,
dspctl) & 0x7f) >= pos)
@@ -1793,7 +1816,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
pc += 4;
}
}
- break; /* end REGIMM */
+ break; /* end REGIMM */
case 2: /* J */
case 3: /* JAL */
{
@@ -1827,7 +1850,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
break;
case 7:
default:
- greater_branch: /* BGTZ, BGTZL */
+ greater_branch: /* BGTZ, BGTZL */
if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)
pc += mips32_relative_offset (inst) + 4;
else
@@ -1893,8 +1916,10 @@ micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
int cond;
if (fcsr == -1)
- /* No way to handle; it'll most likely trap anyway. */
- return pc;
+ {
+ /* No way to handle; it'll most likely trap anyway. */
+ return pc;
+ }
fcs = regcache_raw_get_unsigned (regcache, fcsr);
cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
@@ -2008,8 +2033,10 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
case 0x14: /* BC2F: bits 010000 10100 xxx00 */
case 0x15: /* BC2T: bits 010000 10101 xxx00 */
if (((insn >> 16) & 0x3) == 0x0)
- /* BC2F, BC2T: don't know how to handle these. */
- break;
+ {
+ /* BC2F, BC2T: don't know how to handle these. */
+ break;
+ }
break;
case 0x1a: /* BPOSGE64: bits 010000 11010 */
@@ -2019,8 +2046,10 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
int dspctl = mips_regnum (gdbarch)->dspctl;
if (dspctl == -1)
- /* No way to handle; it'll most likely trap anyway. */
- break;
+ {
+ /* No way to handle; it'll most likely trap anyway. */
+ break;
+ }
if ((regcache_raw_get_unsigned (regcache,
dspctl) & 0x7f) >= pos)
@@ -2055,7 +2084,7 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
case 0x25: /* BEQ: bits 100101 */
if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
- == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
+ == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
pc += micromips_relative_offset16 (insn);
else
pc += micromips_pc_insn_size (gdbarch, pc);
@@ -2063,7 +2092,7 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
case 0x2d: /* BNE: bits 101101 */
if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
- != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
+ != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
pc += micromips_relative_offset16 (insn);
else
pc += micromips_pc_insn_size (gdbarch, pc);
@@ -2081,11 +2110,15 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
{
case 0x11: /* POOL16C: bits 010001 */
if ((b5s5_op (insn) & 0x1c) == 0xc)
- /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
- pc = regcache_raw_get_signed (regcache, b0s5_reg (insn));
+ {
+ /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
+ pc = regcache_raw_get_signed (regcache, b0s5_reg (insn));
+ }
else if (b5s5_op (insn) == 0x18)
- /* JRADDIUSP: bits 010001 11000 */
- pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM);
+ {
+ /* JRADDIUSP: bits 010001 11000 */
+ pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM);
+ }
break;
case 0x23: /* BEQZ16: bits 100011 */
@@ -2540,10 +2573,10 @@ mips16_scan_prologue (struct gdbarch *gdbarch,
long frame_offset = 0; /* Size of stack frame. */
long frame_adjust = 0; /* Offset of FP from SP. */
int frame_reg = MIPS_SP_REGNUM;
- unsigned short prev_inst = 0; /* Saved copy of previous instruction. */
- unsigned inst = 0; /* Current instruction. */
- unsigned entry_inst = 0; /* The entry instruction. */
- unsigned save_inst = 0; /* The save instruction. */
+ unsigned short prev_inst = 0; /* saved copy of previous instruction. */
+ unsigned inst = 0; /* current instruction */
+ unsigned entry_inst = 0; /* the entry instruction */
+ unsigned save_inst = 0; /* the save instruction */
int prev_delay_slot = 0;
int in_delay_slot;
int reg, offset;
@@ -2602,10 +2635,12 @@ mips16_scan_prologue (struct gdbarch *gdbarch,
if (offset < 0) /* Negative stack adjustment? */
frame_offset -= offset;
else
- /* Exit loop if a positive stack adjustment is found, which
- usually means that the stack cleanup code in the function
- epilogue is reached. */
- break;
+ {
+ /* Exit loop if a positive stack adjustment is found, which
+ usually means that the stack cleanup code in the function
+ epilogue is reached. */
+ break;
+ }
}
else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
{
@@ -3501,10 +3536,12 @@ mips32_scan_prologue (struct gdbarch *gdbarch,
if (offset < 0) /* Negative stack adjustment? */
frame_offset -= offset;
else
- /* Exit loop if a positive stack adjustment is found, which
- usually means that the stack cleanup code in the function
- epilogue is reached. */
- break;
+ {
+ /* Exit loop if a positive stack adjustment is found, which
+ usually means that the stack cleanup code in the function
+ epilogue is reached. */
+ break;
+ }
seen_sp_adjust = 1;
}
else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
@@ -3578,7 +3615,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch,
}
}
}
- else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
+ else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
&& !regsize_is_64_bits)
{
set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
@@ -3906,22 +3943,24 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
- /* This hack is a work-around for existing boards using PMON, the
- simulator, and any other 64-bit targets that doesn't have true
- 64-bit addressing. On these targets, the upper 32 bits of
- addresses are ignored by the hardware. Thus, the PC or SP are
- likely to have been sign extended to all 1s by instruction
- sequences that load 32-bit addresses. For example, a typical
- piece of code that loads an address is this:
-
- lui $r2, <upper 16 bits>
- ori $r2, <lower 16 bits>
-
- But the lui sign-extends the value such that the upper 32 bits
- may be all 1s. The workaround is simply to mask off these
- bits. In the future, gcc may be changed to support true 64-bit
- addressing, and this masking will have to be disabled. */
- return addr &= 0xffffffffUL;
+ {
+ /* This hack is a work-around for existing boards using PMON, the
+ simulator, and any other 64-bit targets that doesn't have true
+ 64-bit addressing. On these targets, the upper 32 bits of
+ addresses are ignored by the hardware. Thus, the PC or SP are
+ likely to have been sign extended to all 1s by instruction
+ sequences that load 32-bit addresses. For example, a typical
+ piece of code that loads an address is this:
+
+ lui $r2, <upper 16 bits>
+ ori $r2, <lower 16 bits>
+
+ But the lui sign-extends the value such that the upper 32 bits
+ may be all 1s. The workaround is simply to mask off these
+ bits. In the future, gcc may be changed to support true 64-bit
+ addressing, and this masking will have to be disabled. */
+ return addr &= 0xffffffffUL;
+ }
else
return addr;
}
@@ -6722,7 +6761,7 @@ mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
that bound, then use an arbitrary large number as the upper bound. */
limit_pc = skip_prologue_using_sal (gdbarch, pc);
if (limit_pc == 0)
- limit_pc = pc + 100; /* Magic. */
+ limit_pc = pc + 100; /* Magic. */
if (mips_pc_is_mips16 (gdbarch, pc))
return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
@@ -7027,7 +7066,7 @@ gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
/* FIXME: cagney/2003-06-26: Is this even necessary? The
disassembler needs to be able to locally determine the ISA, and
- not rely on GDB. Otherwise the stand-alone 'objdump -d' will not
+ not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
work. */
if (mips_pc_is_mips16 (gdbarch, memaddr))
info->mach = bfd_mach_mips16;
@@ -7435,36 +7474,42 @@ mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
break;
addr -= MIPS_INSN16_SIZE;
if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0))
- /* Looks like a JR/JALR at [target-1], but it could be
- the second word of a previous JAL/JALX, so record it
- and check back one more. */
- jmpaddr = addr;
+ {
+ /* Looks like a JR/JALR at [target-1], but it could be
+ the second word of a previous JAL/JALX, so record it
+ and check back one more. */
+ jmpaddr = addr;
+ }
else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1))
{
if (i == 2)
- /* Looks like a JAL/JALX at [target-2], but it could also
- be the second word of a previous JAL/JALX, record it,
- and check back one more. */
- jmpaddr = addr;
+ {
+ /* Looks like a JAL/JALX at [target-2], but it could also
+ be the second word of a previous JAL/JALX, record it,
+ and check back one more. */
+ jmpaddr = addr;
+ }
else
- /* Looks like a JAL/JALX at [target-3], so any previously
- recorded JAL/JALX or JR/JALR must be wrong, because:
-
- >-3: JAL
- -2: JAL-ext (can't be JAL/JALX)
- -1: bdslot (can't be JR/JALR)
- 0: target insn
-
- Of course it could be another JAL-ext which looks
- like a JAL, but in that case we'd have broken out
- of this loop at [target-2]:
-
- -4: JAL
- >-3: JAL-ext
- -2: bdslot (can't be jmp)
- -1: JR/JALR
- 0: target insn */
- jmpaddr = 0;
+ {
+ /* Looks like a JAL/JALX at [target-3], so any previously
+ recorded JAL/JALX or JR/JALR must be wrong, because:
+
+ >-3: JAL
+ -2: JAL-ext (can't be JAL/JALX)
+ -1: bdslot (can't be JR/JALR)
+ 0: target insn
+
+ Of course it could be another JAL-ext which looks
+ like a JAL, but in that case we'd have broken out
+ of this loop at [target-2]:
+
+ -4: JAL
+ >-3: JAL-ext
+ -2: bdslot (can't be jmp)
+ -1: JR/JALR
+ 0: target insn */
+ jmpaddr = 0;
+ }
}
else
{
@@ -7731,15 +7776,19 @@ mips_skip_mips16_trampoline_code (const frame_info_ptr &frame, CORE_ADDR pc)
&& mips_is_stub_suffix (name + prefixlen + 3, 0))
{
if (pc == start_addr)
- /* This is the 'call' part of a call stub. The return
- address is in $2. */
- return get_frame_register_signed
+ {
+ /* This is the 'call' part of a call stub. The return
+ address is in $2. */
+ return get_frame_register_signed
(frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
+ }
else
- /* This is the 'return' part of a call stub. The return
- address is in $18. */
- return get_frame_register_signed
+ {
+ /* This is the 'return' part of a call stub. The return
+ address is in $18. */
+ return get_frame_register_signed
(frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
+ }
}
else
return 0; /* Not a stub. */
@@ -7751,15 +7800,19 @@ mips_skip_mips16_trampoline_code (const frame_info_ptr &frame, CORE_ADDR pc)
|| startswith (name, mips_str_call_stub))
{
if (pc == start_addr)
- /* This is the 'call' part of a call stub. Call this helper
- to scan through this code for interesting instructions
- and determine the final PC. */
- return mips_get_mips16_fn_stub_pc (frame, pc);
+ {
+ /* This is the 'call' part of a call stub. Call this helper
+ to scan through this code for interesting instructions
+ and determine the final PC. */
+ return mips_get_mips16_fn_stub_pc (frame, pc);
+ }
else
- /* This is the 'return' part of a call stub. The return address
- is in $18. */
- return get_frame_register_signed
+ {
+ /* This is the 'return' part of a call stub. The return address
+ is in $18. */
+ return get_frame_register_signed
(frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
+ }
}
return 0; /* Not a stub. */
@@ -7974,7 +8027,7 @@ mips_integer_to_address (struct gdbarch *gdbarch,
an assertion failure. */
static void
-mips_virtual_frame_pointer (struct gdbarch *gdbarch,
+mips_virtual_frame_pointer (struct gdbarch *gdbarch,
CORE_ADDR pc, int *reg, LONGEST *offset)
{
*reg = MIPS_SP_REGNUM;
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v13 2/2] gdb: mips: Add MIPSR6 support
2025-06-04 12:38 [PATCH v13 0/2] gdb: mips: Add MIPSR6 support Jovan Dmitrovic
2025-06-04 12:39 ` [PATCH v13 1/2] gdb: mips: Apply coding guidelines Jovan Dmitrovic
@ 2025-06-04 12:39 ` Jovan Dmitrovic
2026-09-17 11:22 ` Maciej W. Rozycki
1 sibling, 1 reply; 5+ messages in thread
From: Jovan Dmitrovic @ 2025-06-04 12:39 UTC (permalink / raw)
To: gdb-patches
Cc: Djordje Todorovic, Milica Matic, Maciej W . Rozycki, Jovan Dmitrovic
From: Milica Matic <milica.matic@htecgroup.com>
Introduce new instruction encodings from Release 6 of the MIPS
architecture [1]. Support breakpoints and single stepping with
compact branches, forbidden slots, new branch instruction and
new atomic load-store instruction encodings.
Signed-off-by: Milica Matic <milica.matic@htecgroup.com>
Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com>
---
gdb/mips-tdep.c | 548 +++++++++++++--
gdb/testsuite/gdb.arch/mips-64-r6.c | 916 ++++++++++++++++++++++++++
gdb/testsuite/gdb.arch/mips-64-r6.exp | 74 +++
3 files changed, 1496 insertions(+), 42 deletions(-)
create mode 100644 gdb/testsuite/gdb.arch/mips-64-r6.c
create mode 100644 gdb/testsuite/gdb.arch/mips-64-r6.exp
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index 48284abdd73..9cf73e30540 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -76,6 +76,10 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
static void mips_print_float_info (struct gdbarch *, struct ui_file *,
const frame_info_ptr &, const char *);
+static void
+mips_read_fp_register_single (const frame_info_ptr &frame, int regno,
+ gdb::array_view<gdb_byte> rare_buffer);
+
/* A useful bit in the CP0 status register (MIPS_PS_REGNUM).
This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
#define ST0_FR (1 << 26)
@@ -326,6 +330,17 @@ mips_abi_regsize (struct gdbarch *gdbarch)
}
}
+/* Return true if the gdbarch is based on MIPS Release 6. */
+
+static bool
+is_mipsr6_isa (struct gdbarch *gdbarch)
+{
+ const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
+
+ return (info->mach == bfd_mach_mipsisa32r6
+ || info->mach == bfd_mach_mipsisa64r6);
+}
+
/* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
are some functions to handle addresses associated with compressed
code including but not limited to testing, setting, or clearing
@@ -1554,6 +1569,7 @@ mips_fetch_instruction (struct gdbarch *gdbarch,
#define b0s11_op(x) ((x) & 0x7ff)
#define b0s12_imm(x) ((x) & 0xfff)
#define b0s16_imm(x) ((x) & 0xffff)
+#define b0s21_imm(x) ((x) & 0x1fffff)
#define b0s26_imm(x) ((x) & 0x3ffffff)
#define b6s10_ext(x) (((x) >> 6) & 0x3ff)
#define b11s5_reg(x) (((x) >> 11) & 0x1f)
@@ -1590,6 +1606,24 @@ mips32_relative_offset (ULONGEST inst)
return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
}
+/* Calculates pc-relative offset from lower 21 bits of instruction.
+ Used by BEQZC, BNEZC. */
+
+static LONGEST
+mips32_relative_offset21 (ULONGEST insn)
+{
+ return ((b0s21_imm (insn) ^ 0x100000) - 0x100000) << 2;
+}
+
+/* Calculates pc-relative offset from lower 26 bits of an instruction.
+ Used by BC, BALC. */
+
+static LONGEST
+mips32_relative_offset26 (ULONGEST insn)
+{
+ return ((b0s26_imm (insn) ^ 0x2000000) - 0x2000000) << 2;
+}
+
/* Determine the address of the next instruction executed after the INST
floating condition branch instruction at PC. COUNT specifies the
number of the floating condition bits tested by the branch. */
@@ -1650,6 +1684,77 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
return 0;
}
+/* Detects whether overflow occurs when adding two 32-bit integers. */
+
+static bool
+is_add32bit_overflow (int32_t a, int32_t b)
+{
+ int32_t r = (uint32_t) a + (uint32_t) b;
+ return (a < 0 && b < 0 && r >= 0) || (a > 0 && b > 0 && r <= 0);
+}
+
+/* Helper function for BOVC and BNVC instructions which are introduced in
+ MIPS Release 6.
+
+ BOVC performs a signed 32-bit addition of two registers. BOVC discards the
+ sum, but detects signed 32-bit integer overflow of the sum (and the inputs,
+ in MIPS64), and branches if such overflow is detected.
+
+ BNVC does the opposite, i.e. branches if such overflow is not detected. */
+
+static bool
+is_add64bit_overflow (int64_t a, int64_t b)
+{
+ if (a != (int32_t) a)
+ return true;
+ if (b != (int32_t) b)
+ return true;
+ return is_add32bit_overflow ((int32_t) a, (int32_t) b);
+}
+
+#define DELAY_SLOT_SIZE 4
+
+/* Calculate address of next instruction after BLEZ. */
+
+static CORE_ADDR
+mips32_blez_pc (struct gdbarch *gdbarch, struct regcache *regcache,
+ ULONGEST inst, CORE_ADDR pc, int invert)
+{
+ int rs = itype_rs (inst);
+ int rt = itype_rt (inst);
+ LONGEST val_rs = regcache_raw_get_signed (regcache, rs);
+ LONGEST val_rt = regcache_raw_get_signed (regcache, rt);
+ ULONGEST uval_rs = regcache_raw_get_unsigned (regcache, rs);
+ ULONGEST uval_rt = regcache_raw_get_unsigned (regcache, rt);
+ bool taken = false;
+
+ /* BLEZ, BLEZL, BGTZ, BGTZL */
+ if (rt == 0)
+ taken = (val_rs <= 0);
+ else if (is_mipsr6_isa (gdbarch))
+ {
+ /* BLEZALC, BGTZALC */
+ if (rs == 0 && rt != 0)
+ taken = (val_rt <= 0);
+ /* BGEZALC, BLTZALC */
+ else if (rs == rt && rt != 0)
+ taken = (val_rt >= 0);
+ /* BGEUC, BLTUC */
+ else if (rs != rt && rs != 0 && rt != 0)
+ taken = (uval_rs >= uval_rt);
+ }
+
+ if (invert)
+ taken = !taken;
+
+ /* Calculate branch target. */
+ if (taken)
+ pc += mips32_relative_offset (inst);
+ else
+ pc += DELAY_SLOT_SIZE;
+
+ return pc;
+}
/* Determine where to set a single step breakpoint while considering
branch prediction. */
@@ -1660,11 +1765,16 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
struct gdbarch *gdbarch = regcache->arch ();
unsigned long inst;
int op;
+ bool mips64bitreg = false;
+
+ if (mips_isa_regsize (gdbarch) == 8)
+ mips64bitreg = true;
+
inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
op = itype_op (inst);
if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction. */
{
- if (op >> 2 == 5)
+ if (op >> 2 == 5 && ((op & 0x02) == 0 || itype_rt (inst) == 0))
{
/* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
switch (op & 0x03)
@@ -1674,7 +1784,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
case 1: /* BNEL */
goto neq_branch;
case 2: /* BLEZL */
- goto less_branch;
+ goto lez_branch;
case 3: /* BGTZL */
goto greater_branch;
default:
@@ -1686,19 +1796,23 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
/* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);
}
- else if (op == 17 && itype_rs (inst) == 9
+ else if (!is_mipsr6_isa (gdbarch)
+ && op == 17
+ && itype_rs (inst) == 9
&& (itype_rt (inst) & 2) == 0)
{
/* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);
}
- else if (op == 17 && itype_rs (inst) == 10
+ else if (!is_mipsr6_isa (gdbarch)
+ && op == 17
+ && itype_rs (inst) == 10
&& (itype_rt (inst) & 2) == 0)
{
/* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);
}
- else if (op == 29)
+ else if (!is_mipsr6_isa (gdbarch) && op == 29)
{
/* JALX: 011101
The new PC will be alternate mode. */
@@ -1731,7 +1845,148 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
pc += 8;
}
}
+ else if (is_mipsr6_isa (gdbarch))
+ {
+ if (op == 8 || op == 24)
+ {
+ /* BOVC, BEQZALC, BEQC and BNVC, BNEZALC, BNEC */
+ int rs = rtype_rs (inst);
+ int rt = rtype_rt (inst);
+ LONGEST val_rs = regcache_raw_get_signed (regcache, rs);
+ LONGEST val_rt = regcache_raw_get_signed (regcache, rt);
+ bool taken = false;
+ if (rs >= rt)
+ {
+ /* BOVC (BNVC) */
+ if (mips64bitreg)
+ taken = is_add64bit_overflow (val_rs, val_rt);
+ else
+ taken = is_add32bit_overflow (val_rs, val_rt);
+ }
+ else if (rs < rt && rs == 0)
+ {
+ /* BEQZALC (BNEZALC) */
+ taken = (val_rt == 0);
+ }
+ else
+ {
+ /* BEQC (BNEC) */
+ taken = (val_rs == val_rt);
+ }
+ if (op == 24)
+ {
+ /* BNVC, BNEZALC, BNEC */
+ taken = !taken;
+ }
+
+ if (taken)
+ pc += mips32_relative_offset (inst) + 4;
+ else
+ {
+ /* Step through the forbidden slot to avoid repeated
+ exceptions.
+ We do not currently have access to the BD bit when hitting
+ a breakpoint and therefore cannot tell if the breakpoint
+ hit on the branch or the forbidden slot. */
+ pc += 8;
+ }
+ }
+ else if (op == 17 && (itype_rs (inst) == 9 || itype_rs (inst) == 13))
+ {
+ /* BC1EQZ, BC1NEZ */
+ gdb_byte status;
+ gdb_byte true_val = 0;
+ unsigned int fp = (gdbarch_num_regs (gdbarch)
+ + mips_regnum (gdbarch)->fp0
+ + itype_rt (inst));
+ struct frame_info_ptr frame = get_current_frame ();
+ gdb_byte *buf_tmp = (gdb_byte *) alloca (sizeof (gdb_byte) * 4);
+ gdb::array_view<gdb_byte> raw_buffer = gdb::make_array_view (buf_tmp, sizeof (gdb_byte) * 4);
+ mips_read_fp_register_single (frame, fp, raw_buffer);
+
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ status = raw_buffer[3];
+ else
+ status = raw_buffer[0];
+
+ if (itype_rs (inst) == 13)
+ true_val = 1;
+
+ if ((status & 0x1) == true_val)
+ pc += mips32_relative_offset (inst) + 4;
+ else
+ pc += 8;
+ }
+ else if (op == 22 || op == 23)
+ {
+ /* BLEZC, BGEZC, BGEC, BGTZC, BLTZC, BLTC */
+ int rs = rtype_rs (inst);
+ int rt = rtype_rt (inst);
+ LONGEST val_rs = regcache_raw_get_signed (regcache, rs);
+ LONGEST val_rt = regcache_raw_get_signed (regcache, rt);
+ bool taken = false;
+ /* The R5 rt == 0 case is handled above so we treat it as
+ an unknown instruction here for future ISA usage. */
+ if (rs == 0 && rt != 0)
+ taken = (val_rt <= 0);
+ else if (rs == rt && rt != 0)
+ taken = (val_rt >= 0);
+ else if (rs != rt && rs != 0 && rt != 0)
+ taken = (val_rs >= val_rt);
+
+ if (op == 23)
+ taken = !taken;
+
+ if (taken)
+ pc += mips32_relative_offset (inst) + 4;
+ else
+ {
+ /* Step through the forbidden slot to avoid repeated
+ exceptions.
+ We do not currently have access to the BD bit when hitting
+ a breakpoint and therefore cannot tell if the breakpoint
+ hit on the branch or the forbidden slot. */
+ pc += 8;
+ }
+ }
+ else if (op == 50 || op == 58)
+ {
+ /* BC, BALC */
+ pc += mips32_relative_offset26 (inst) + 4;
+ }
+ else if ((op == 54 || op == 62)
+ && rtype_rs (inst) == 0)
+ {
+ /* JIC, JIALC */
+ pc = regcache_raw_get_signed (regcache, itype_rt (inst));
+ pc += (itype_immediate (inst) ^ 0x8000) - 0x8000;
+ }
+ else if (op == 54 || op == 62)
+ {
+ /* BEQZC, BNEZC */
+ int rs = itype_rs (inst);
+ LONGEST rs_val = regcache_raw_get_signed (regcache, rs);
+ bool taken = (rs_val == 0);
+ if (op == 62)
+ taken = !taken;
+ if (taken)
+ pc += mips32_relative_offset21 (inst) + 4;
+ else
+ {
+ /* Step through the forbidden slot to avoid repeated exceptions
+ we do not currently have access to the BD bit when hitting a
+ breakpoint and therefore cannot tell if the breakpoint
+ hit on the branch or the forbidden slot. */
+ pc += 8;
+ }
+ }
+ else
+ {
+ /* Not a branch, next instruction is easy. */
+ pc += 4;
+ }
+ }
else
pc += 4; /* Not a branch, next instruction is easy. */
}
@@ -1775,7 +2030,6 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
case 2: /* BLTZL */
case 16: /* BLTZAL */
case 18: /* BLTZALL */
- less_branch:
if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)
pc += mips32_relative_offset (inst) + 4;
else
@@ -1791,6 +2045,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
pc += 8; /* after the delay slot */
break;
case 0x1c: /* BPOSGE32 */
+ case 0x1d: /* BPOSGE32C */
case 0x1e: /* BPOSGE64 */
pc += 4;
if (itype_rs (inst) == 0)
@@ -1804,11 +2059,18 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
break;
}
+ /* BPOSGE32C */
+ if (op == 0x1d)
+ {
+ if (!is_mipsr6_isa (gdbarch))
+ break;
+ }
+
if ((regcache_raw_get_unsigned (regcache,
dspctl) & 0x7f) >= pos)
pc += mips32_relative_offset (inst);
else
- pc += 4;
+ pc += DELAY_SLOT_SIZE;
}
break;
/* All of the other instructions in the REGIMM category */
@@ -1842,19 +2104,14 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
else
pc += 8;
break;
- case 6: /* BLEZ, BLEZL */
- if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0)
- pc += mips32_relative_offset (inst) + 4;
- else
- pc += 8;
+ case 6: /* BLEZ, BLEZL, BLEZALC, BGEZALC, BGEUC */
+ lez_branch:
+ pc = mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 0);
break;
case 7:
default:
- greater_branch: /* BGTZ, BGTZL */
- if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)
- pc += mips32_relative_offset (inst) + 4;
- else
- pc += 8;
+ greater_branch: /* BGTZ, BGTZL, BGTZALC, BLTZALC, BLTUC */
+ pc = mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 1);
break;
} /* switch */
} /* else */
@@ -2487,6 +2744,63 @@ micromips_instruction_is_compact_branch (unsigned short insn)
}
}
+/* Return non-zero if the MIPS instruction INSN is a compact branch
+ or jump. A value of 1 indicates an unconditional compact branch
+ and a value of 2 indicates a conditional compact branch. */
+
+static int
+mips32_instruction_is_compact_branch (struct gdbarch *gdbarch, ULONGEST insn)
+{
+ switch (itype_op (insn))
+ {
+ case 50: /* BC */
+ case 58: /* BALC */
+ if (is_mipsr6_isa (gdbarch))
+ return 1;
+ break;
+ case 8: /* BOVC, BEQZALC, BEQC */
+ case 24: /* BNVC, BNEZALC, BNEC */
+ if (is_mipsr6_isa (gdbarch))
+ return 2;
+ break;
+ case 54: /* BEQZC, JIC */
+ case 62: /* BNEZC, JIALC */
+ if (is_mipsr6_isa (gdbarch))
+ {
+ /* JIC, JIALC are unconditional */
+ return (itype_rs (insn) == 0) ? 1 : 2;
+ }
+ break;
+ case 22: /* BLEZC, BGEZC, BGEC */
+ case 23: /* BGTZC, BLTZC, BLTC */
+ case 6: /* BLEZALC, BGEZALC, BGEUC */
+ case 7: /* BGTZALC, BLTZALC, BLTUC */
+ if (is_mipsr6_isa (gdbarch)
+ && itype_rt (insn) != 0)
+ return 2;
+ break;
+ case 1: /* BPOSGE32C */
+ if (is_mipsr6_isa (gdbarch)
+ && itype_rt (insn) == 0x1d && itype_rs (insn) == 0)
+ return 2;
+ }
+ return 0;
+}
+
+/* Return true if a standard MIPS instruction at ADDR has a branch
+ forbidden slot (i.e. it is a conditional compact branch instruction). */
+
+static bool
+mips32_insn_at_pc_has_forbidden_slot (struct gdbarch *gdbarch, CORE_ADDR addr)
+{
+ int status;
+ ULONGEST insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status);
+ if (status)
+ return false;
+
+ return mips32_instruction_is_compact_branch (gdbarch, insn) == 2;
+}
+
struct mips_frame_cache
{
CORE_ADDR base;
@@ -3530,7 +3844,8 @@ mips32_scan_prologue (struct gdbarch *gdbarch,
reg = high_word & 0x1f;
if (high_word == 0x27bd /* addiu $sp,$sp,-i */
- || high_word == 0x23bd /* addi $sp,$sp,-i */
+ || (high_word == 0x23bd /* addi $sp,$sp,-i */
+ && !is_mipsr6_isa (gdbarch))
|| high_word == 0x67bd) /* daddiu $sp,$sp,-i */
{
if (offset < 0) /* Negative stack adjustment? */
@@ -3670,7 +3985,9 @@ mips32_scan_prologue (struct gdbarch *gdbarch,
/* A jump or branch, or enough non-prologue insns seen? If so,
then we must have reached the end of the prologue by now. */
- if (prev_delay_slot || non_prologue_insns > 1)
+ if (prev_delay_slot
+ || non_prologue_insns > 1
+ || mips32_instruction_is_compact_branch (gdbarch, inst))
break;
prev_non_prologue_insn = this_non_prologue_insn;
@@ -3976,6 +4293,70 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
#define LLD_OPCODE 0x34
#define SC_OPCODE 0x38
#define SCD_OPCODE 0x3c
+#define LLSC_R6_OPCODE 0x1f
+#define LL_R6_FUNCT 0x36
+#define LLE_FUNCT 0x2e
+#define LLD_R6_FUNCT 0x37
+#define SC_R6_FUNCT 0x26
+#define SCE_FUNCT 0x1e
+#define SCD_R6_FUNCT 0x27
+
+/* Determine whether instruction 'insn' is of 'load linked X' type.
+ LL/SC instructions provide primitives to implement atomic
+ read-modify-write operations for synchronizable memory locations. */
+
+static bool
+is_ll_insn (struct gdbarch *gdbarch, ULONGEST insn)
+{
+ if (itype_op (insn) == LL_OPCODE
+ || itype_op (insn) == LLD_OPCODE)
+ return true;
+
+ if (rtype_op (insn) == LLSC_R6_OPCODE
+ && rtype_funct (insn) == LLE_FUNCT
+ && (insn & 0x40) == 0)
+ return true;
+
+ /* Handle LL and LLP varieties. */
+ if (is_mipsr6_isa (gdbarch)
+ && rtype_op (insn) == LLSC_R6_OPCODE
+ && (rtype_funct (insn) == LL_R6_FUNCT
+ || rtype_funct (insn) == LLD_R6_FUNCT
+ || rtype_funct (insn) == LLE_FUNCT))
+ return true;
+
+ return false;
+}
+
+/* Determine whether instruction 'insn' is of 'store conditional X' type.
+ SC instructions and varieties perform completion of read-modify-write
+ atomic sequence. */
+
+static bool
+is_sc_insn (struct gdbarch *gdbarch, ULONGEST insn)
+{
+ if (itype_op (insn) == SC_OPCODE
+ || itype_op (insn) == SCD_OPCODE)
+ return true;
+
+ if (rtype_op (insn) == LLSC_R6_OPCODE
+ && rtype_funct (insn) == SCE_FUNCT
+ && (insn & 0x40) == 0)
+ return true;
+
+ /* Handle SC and SCP varieties. */
+ if (is_mipsr6_isa (gdbarch)
+ && rtype_op (insn) == LLSC_R6_OPCODE
+ && (rtype_funct (insn) == SC_R6_FUNCT
+ || rtype_funct (insn) == SCD_R6_FUNCT
+ || rtype_funct (insn) == SCE_FUNCT))
+ return true;
+
+ return false;
+}
+
+/* Handle mips atomic sequence which starts with LL/LLD and ends with
+ SC/SCD instruction. */
static std::vector<CORE_ADDR>
mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
@@ -3988,10 +4369,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
int index;
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
+ bool is_mipsr6 = is_mipsr6_isa (gdbarch);
insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
/* Assume all atomic sequences start with a ll/lld instruction. */
- if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
+ if (!is_ll_insn (gdbarch, insn))
return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
@@ -4021,28 +4403,72 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
return {}; /* fallback to the standard single-step code. */
case 4: /* BEQ */
case 5: /* BNE */
- case 6: /* BLEZ */
- case 7: /* BGTZ */
case 20: /* BEQL */
case 21: /* BNEL */
- case 22: /* BLEZL */
- case 23: /* BGTTL */
+ case 22: /* BLEZL (BLEZC, BGEZC, BGEC) */
+ case 23: /* BGTZL (BGTZC, BLTZC, BLTC) */
is_branch = 1;
break;
+ case 6: /* BLEZ (BLEZALC, BGEZALC, BGEUC) */
+ case 7: /* BGTZ (BGTZALC, BLTZALC, BLTUC) */
+ if (is_mipsr6)
+ {
+ /* BLEZALC, BGTZALC */
+ if (itype_rs (insn) == 0 && itype_rt (insn) != 0)
+ return {}; /* fallback to the standard single-step code. */
+ /* BGEZALC, BLTZALC */
+ else if (itype_rs (insn) == itype_rt (insn)
+ && itype_rt (insn) != 0)
+ return {}; /* fallback to the standard single-step code. */
+ }
+ is_branch = 1;
+ break;
+ case 8: /* BOVC, BEQZALC, BEQC */
+ case 24: /* BNVC, BNEZALC, BNEC */
+ if (is_mipsr6)
+ is_branch = 1;
+ break;
+ case 50: /* BC */
+ case 58: /* BALC */
+ if (is_mipsr6)
+ return {}; /* fallback to the standard single-step code. */
+ break;
+ case 54: /* BEQZC, JIC */
+ case 62: /* BNEZC, JIALC */
+ if (is_mipsr6)
+ {
+ if (itype_rs (insn) == 0) /* JIC, JIALC */
+ return {}; /* fallback to the standard single-step code. */
+ else
+ is_branch = 2; /* Marker for branches with a 21-bit offset. */
+ }
+ break;
case 17: /* COP1 */
- is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10)
- && (itype_rt (insn) & 0x2) == 0);
- if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
+ is_branch = ((!is_mipsr6
+ /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
+ && (itype_rs (insn) == 9 || itype_rs (insn) == 10)
+ && (itype_rt (insn) & 0x2) == 0)
+ /* BZ.df: 010001 110xx */
+ || (itype_rs (insn) & 0x18) == 0x18);
+ if (is_branch != 0)
break;
[[fallthrough]];
case 18: /* COP2 */
case 19: /* COP3 */
- is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
+ /* BCzF, BCzFL, BCzT, BCzTL, BC*EQZ, BC*NEZ */
+ is_branch = ((itype_rs (insn) == 8)
+ || (is_mipsr6
+ && (itype_rs (insn) == 9
+ || itype_rs (insn) == 13)));
break;
}
- if (is_branch)
+ if (is_branch != 0)
{
- branch_bp = loc + mips32_relative_offset (insn) + 4;
+ /* Is this a special PC21_S2 branch? */
+ if (is_branch == 2)
+ branch_bp = loc + mips32_relative_offset21 (insn) + 4;
+ else
+ branch_bp = loc + mips32_relative_offset (insn) + 4;
if (last_breakpoint >= 1)
return {}; /* More than one branch found, fallback to the
standard single-step code. */
@@ -4050,12 +4476,12 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
last_breakpoint++;
}
- if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
+ if (is_sc_insn (gdbarch, insn))
break;
}
/* Assume that the atomic sequence ends with a sc/scd instruction. */
- if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
+ if (!is_sc_insn (gdbarch, insn))
return {};
loc += MIPS_INSN32_SIZE;
@@ -4204,7 +4630,7 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
}
break;
}
- if (is_branch)
+ if (is_branch != 0)
{
if (last_breakpoint >= 1)
return {}; /* More than one branch found, fallback to the
@@ -4280,8 +4706,14 @@ mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
gdb_assert (mips_pc_is_mips (pc));
insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
- hint = 0x7c0;
- return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */
+ /* Mask the hint and the jalr/jr bit. */
+ hint = 0x7c1;
+
+ if (is_mipsr6_isa (gdbarch) && insn == 0xd81f0000) /* jrc $31 */
+ return 1;
+
+ /* jr(.hb) $ra and "jalr(.hb) $ra" */
+ return ((insn & ~hint) == 0x3e00008);
}
/* This fencepost looks highly suspicious to me. Removing it also
@@ -6799,7 +7231,9 @@ mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
if (high_word != 0x27bd /* addiu $sp,$sp,offset */
&& high_word != 0x67bd /* daddiu $sp,$sp,offset */
- && inst != 0x03e00008 /* jr $ra */
+ && (inst & ~0x1) != 0x03e00008 /* jr $31 or jalr $0, $31 */
+ && (!is_mipsr6_isa (gdbarch)
+ || inst != 0xd81f0000) /* jrc $31 */
&& inst != 0x00000000) /* nop */
return 0;
}
@@ -7177,6 +7611,7 @@ mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst)
int op;
int rs;
int rt;
+ bool is_mipsr6 = is_mipsr6_isa (gdbarch);
op = itype_op (inst);
if ((inst & 0xe0000000) != 0)
@@ -7184,15 +7619,23 @@ mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst)
rs = itype_rs (inst);
rt = itype_rt (inst);
return (is_octeon_bbit_op (op, gdbarch)
- || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
- || op == 29 /* JALX: bits 011101 */
+ || (op >> 1 == 10) /* BEQL, BNEL: bits 01010x */
+ || (op >> 1 == 11 && rt == 0) /* BLEZL, BGTZL: bits 01011x */
+ || (!is_mipsr6 && op == 29) /* JALX: bits 011101 */
|| (op == 17
&& (rs == 8
/* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
- || (rs == 9 && (rt & 0x2) == 0)
+ || (!is_mipsr6 && rs == 9 && (rt & 0x2) == 0)
/* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
- || (rs == 10 && (rt & 0x2) == 0))));
+ || (!is_mipsr6 && rs == 10 && (rt & 0x2) == 0)))
/* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
+ || (is_mipsr6
+ && ((op == 17
+ && (rs == 9 /* BC1EQZ: 010001 01001 */
+ || rs == 13)) /* BC1NEZ: 010001 01101 */
+ || (op == 18
+ && (rs == 9 /* BC2EQZ: 010010 01001 */
+ || rs == 13))))); /* BC2NEZ: 010010 01101 */
}
else
switch (op & 0x07) /* extract bits 28,27,26 */
@@ -7211,7 +7654,11 @@ mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst)
|| ((rt & 0x1e) == 0x1c && rs == 0));
/* BPOSGE32, BPOSGE64: bits 1110x */
break; /* end REGIMM */
- default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
+ case 6: /* BLEZ */
+ case 7: /* BGTZ */
+ return (itype_rt (inst) == 0);
+ break;
+ default: /* J, JAL, BEQ, BNE */
return 1;
break;
}
@@ -7423,7 +7870,18 @@ mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
So, we'll use the second solution. To do this we need to know if
the instruction we're trying to set the breakpoint on is in the
- branch delay slot. */
+ branch delay slot.
+
+ A similar problem occurs for breakpoints on forbidden slots where
+ the trap will be reported for the branch with the BD bit set.
+ In this case it would be ideal to recover using solution 1 from
+ above as there is no problem with the branch being skipped
+ (since the forbidden slot only exists on not-taken branches).
+ However, the BD bit is not available in all scenarios currently
+ so instead we move the breakpoint on to the next instruction.
+ This means that it is not possible to stop on an instruction
+ that can be in a forbidden slot even if that instruction is
+ jumped to directly. */
boundary = mips_segment_boundary (bpaddr);
@@ -7445,6 +7903,12 @@ mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
prev_addr = bpaddr - 4;
if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr))
bpaddr = prev_addr;
+ /* If the previous instruction has a forbidden slot, we have to
+ move the breakpoint to the following instruction to prevent
+ breakpoints in forbidden slots being reported as unknown
+ traps. */
+ else if (mips32_insn_at_pc_has_forbidden_slot (gdbarch, prev_addr))
+ bpaddr += 4;
}
else
{
diff --git a/gdb/testsuite/gdb.arch/mips-64-r6.c b/gdb/testsuite/gdb.arch/mips-64-r6.c
new file mode 100644
index 00000000000..e1a1dd041cc
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/mips-64-r6.c
@@ -0,0 +1,916 @@
+/*
+ Copyright 2023-2025 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+/* ============ macros from sim/testutils/mips/utils-r6.inc ============= */
+
+/* 58 is local label to exit with errcode != 0, indicating error. */
+#define fp_assert(a, b) "beq " xstr (a) ", " xstr (b) ", 1f \n\t" \
+ "nop \n\t" \
+ "b 58f \n\t" \
+ "nop \n\t" \
+ "1: \n\t"
+
+/* Clobbers: $4,$6,$7. */
+#define r6ck_1r(inst, a, ret) \
+ "li $4, " xstr (a) " \n\t" \
+ "li $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $7, $4 \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$6,$7. */
+#define r6ck_1dr(inst, a, ret) \
+ "ld $4, " xstr (a) " \n\t" \
+ "ld $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $7, $4 \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$5,$6,$7. */
+#define r6ck_2r(inst, a, b, ret) \
+ "li $4, " xstr (a) " \n\t" \
+ "li $5, " xstr (b) " \n\t" \
+ "li $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $7, $4, $5 \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$5,$6,$7. */
+#define r6ck_2dr(inst, a, b, ret) \
+ "ld $4, " xstr (a) " \n\t" \
+ "ld $5, " xstr (b) " \n\t" \
+ "ld $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $7, $4, $5 \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$5,$6,$7. */
+#define r6ck_2dr1i(inst, a, b, imm, ret) \
+ "ld $4, " xstr (a) " \n\t" \
+ "ld $5, " xstr (b) " \n\t" \
+ "ld $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $7, $4, $5, " xstr (imm) " \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$6,$7. */
+#define r6ck_1r1i(inst, a, imm, ret) \
+ "li $4, " xstr (a) " \n\t" \
+ "li $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $7, $4, " xstr (imm) " \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$6,$7. */
+#define r6ck_1dr1i(inst, a, imm, ret) \
+ "ld $4, " xstr (a) " \n\t" \
+ "ld $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $7, $4, " xstr (imm) " \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$6. */
+#define r6ck_0dr1i(inst, a, imm, ret) \
+ "ld $4, " xstr (a) " \n\t" \
+ "ld $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $4, $4, " xstr (imm) " \n\t" \
+ fp_assert ($6, $4)
+
+/* Clobbers: $4,$5,$6,$7. */
+#define r6ck_2r1i(inst, a, b, imm, ret) \
+ "li $4, " xstr (a) " \n\t" \
+ "li $5, " xstr (b) " \n\t" \
+ "li $6, " xstr (ret) " \n\t" \
+ xstr (inst) " $7, $4, $5, " xstr (imm) " \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$5,$6,$7,$8,$f2,$f4,$f6. */
+#define r6ck_3s(inst, a, b, c, ret) \
+ "li $4, " xstr (a) " \n\t" \
+ "li $5, " xstr (b) " \n\t" \
+ "li $6, " xstr (c) " \n\t" \
+ "li $7, " xstr (ret) " \n\t" \
+ "mtc1 $4, $f2 \n\t" \
+ "mtc1 $5, $f4 \n\t" \
+ "mtc1 $6, $f6 \n\t" \
+ xstr (inst) " $f2, $f4, $f6 \n\t" \
+ "mfc1 $8, $f2 \n\t" \
+ fp_assert ($7, $8)
+
+/* Clobbers: $4,$5,$6,$7,$f2,$f4. */
+#define r6ck_2s(inst, a, b, ret) \
+ "li $4, " xstr (a) " \n\t" \
+ "li $5, " xstr (b) " \n\t" \
+ "li $6, " xstr (ret) " \n\t" \
+ "mtc1 $4, $f2 \n\t" \
+ "mtc1 $5, $f4 \n\t" \
+ xstr (inst) " $f2, $f4 \n\t" \
+ "mfc1 $7, $f2 \n\t" \
+ fp_assert ($6, $7)
+
+/* Clobbers: $4,$5,$6,$7,$8,$9,$10,$f2,$f4. */
+#define r6ck_2d(inst, a, b, ret) \
+ ".data \n\t" \
+ "1: .dword " xstr (a) " \n\t" \
+ "2: .dword " xstr (b) " \n\t" \
+ "3: .dword " xstr (ret) " \n\t" \
+ ".text \n\t" \
+ "dla $4, 1b \n\t" \
+ "dla $5, 2b \n\t" \
+ "dla $6, 3b \n\t" \
+ "ldc1 $f2, 0($4) \n\t" \
+ "ldc1 $f4, 0($5) \n\t" \
+ "lw $7, 0($6) \n\t" \
+ "lw $8, 4($6) \n\t" \
+ xstr (inst) " $f2, $f4 \n\t" \
+ "mfhc1 $9, $f2 \n\t" \
+ "mfc1 $10, $f2 \n\t" \
+ fp_assert ($7, $9) \
+ fp_assert ($8, $10)
+
+/* Clobbers: $2,$4,$5,$6,$7,$8,$9,$10,$f2,$f4,$f6. */
+#define r6ck_3d(inst, a, b, c, ret) \
+ ".data \n\t" \
+ "1: .dword " xstr (a) " \n\t" \
+ "2: .dword " xstr (b) " \n\t" \
+ "3: .dword " xstr (c) " \n\t" \
+ "4: .dword " xstr (ret) " \n\t" \
+ ".text \n\t" \
+ "dla $4, 1b \n\t" \
+ "dla $5, 2b \n\t" \
+ "dla $6, 3b \n\t" \
+ "dla $2, 4b \n\t" \
+ "ldc1 $f2, 0($4) \n\t" \
+ "ldc1 $f4, 0($5) \n\t" \
+ "ldc1 $f6, 0($6) \n\t" \
+ "lw $7, 0($2) \n\t" \
+ "lw $8, 4($2) \n\t" \
+ xstr (inst) " $f2, $f4, $f6 \n\t" \
+ "mfhc1 $9, $f2 \n\t" \
+ "mfc1 $10, $f2 \n\t" \
+ fp_assert ($7, $9) \
+ fp_assert ($8, $10)
+
+/* ============ macros from sim/testutils/mips/testutils.inc ============= */
+
+/* Put value 'val' into register 'reg'.
+ Clobbers: None. */
+#define load32(reg, val) \
+ "li " xstr (reg) ", " xstr (val) " \n\t"
+
+/* Check whether two registers contain the same value.
+ Clobbers: None. */
+#define checkreg(reg, expreg) \
+ ".set push \n\t" \
+ ".set noat \n\t" \
+ ".set noreorder \n\t" \
+ "beq " xstr (expreg) ", " xstr (reg) ", 901f \n\t" \
+ "nop \n\t" \
+ "b 58f \n\t" \
+ "nop \n\t" \
+ "901: \n\t" \
+ ".set pop \n\t"
+
+/* Check if register 'reg' contains value 'val'.
+ Clobbers: $1. */
+#define check32(reg, val) \
+ ".set push \n\t" \
+ ".set noat \n\t" \
+ load32 ($1, val) \
+ checkreg (reg, $1) \
+ ".set pop \n\t"
+
+/* Checkpair based on endianess
+ Clobbers: $1. */
+#define checkpair_xendian(lo, hi, base, ec, w) \
+ ".set noat \n\t" \
+ "lw $1, " xstr (ec) " \n\t" \
+ "andi $1, $1, 0x1 \n\t" \
+ "beqz $1, 2f \n\t" \
+ ".set at \n\t" \
+ "1: \n\t" \
+ checkpair_be_##w (lo, hi, base) \
+ "b 3f \n\t" \
+ "nop \n\t" \
+ "2: \n\t" \
+ checkpair_le_##w (lo, hi, base) \
+ "3: \n\t"
+
+/* Check hi-lo register pair against data stored at base+o1 and base+o2.
+ Clobbers: $1 - $5. */
+#define checkpair(lo, hi, base, w, o1, o2) \
+ "move $2, " xstr (lo) " \n\t" \
+ "move $3, " xstr (hi) " \n\t" \
+ ".set noat \n\t" \
+ "dla $1, " xstr (base) " \n\t" \
+ "l" xstr (w) " $4, " xstr (o1) "($1) \n\t" \
+ "l" xstr (w) " $5, " xstr (o2) "($1) \n\t" \
+ ".set at \n\t" \
+ checkreg ($2, $4) \
+ checkreg ($3, $5)
+
+#define checkpair_le_d(lo, hi, base) \
+ checkpair (lo, hi, base, w, 0, 4)
+
+#define checkpair_be_d(lo, hi, base) \
+ checkpair (lo, hi, base, w, 4, 0)
+
+#define checkpair_le_q(lo, hi, base) \
+ checkpair (lo, hi, base, d, 0, 8)
+
+#define checkpair_be_q(lo, hi, base) \
+ checkpair (lo, hi, base, d, 8, 0)
+
+#define checkpair_qword(lo, hi, base, oe) \
+ checkpair_xendian (lo, hi, base, oe, q)
+
+#define checkpair_dword(lo, hi, base, oe) \
+ checkpair_xendian (lo, hi, base, oe, d)
+
+void
+abort (void);
+
+/* Tests branch instructions. */
+
+int
+test_r6_branch (void)
+{
+/* Using volatile to prevent certain optimizations which could cause
+ instruction deletion.
+ 'err' identifies instruction which (eventually) caused error.
+ (err == 0) ==> all instructions executed successfully. */
+
+ volatile int err = -1;
+ volatile int a14 = 0xffffffff;
+ volatile int a13 = 0x123;
+ volatile int a12 = 0x45;
+ volatile int a7 = 0x45;
+ volatile int a8 = 0xfffffffe;
+ volatile int a9 = 2147483647;
+ volatile int a11 = 0;
+ volatile int a10 = 0;
+
+ asm (
+ ".set push \n\t" /* Create new scope for asm configuration. */
+ ".set noreorder \n\t" /* Don't allow reordering of instructions. */
+ "li %[err], 1 \n\t"
+ "bovc %[a12], %[a13], Lfail \n\t" /* BOVC */
+ "nop \n\t"
+ "bovc %[a9], %[a13], L2 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L2: \n\t"
+ "li %[err], 2 \n\t"
+ "bnvc %[a9], %[a13], Lfail \n\t" /* BNVC */
+ "nop \n\t"
+ "bnvc %[a12], %[a13], L3 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L3: \n\t"
+ "li %[err], 3 \n\t"
+ "beqc %[a12], %[a13], Lfail \n\t" /* BEQC */
+ "nop \n\t"
+ "beqc %[a12], %[a7], L4 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L4: \n\t"
+ "li %[err], 4 \n\t"
+ "bnec %[a12], %[a7], Lfail \n\t" /* BNEC */
+ "nop \n\t"
+ "bnec %[a12], %[a13], L5 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L5: \n\t"
+ "li %[err], 5 \n\t"
+ "bltc %[a13], %[a12], Lfail \n\t" /* BLTC */
+ "nop \n\t"
+ "bltc %[a12], %[a13], L6 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L6: \n\t"
+ "L7: \n\t"
+ "li %[err], 7 \n\t"
+ "bgec %[a12], %[a13], Lfail \n\t" /* BGEC */
+ "nop \n\t"
+ "bgec %[a13], %[a12], L8 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L8: \n\t"
+ "L9: \n\t"
+ "li %[err], 9 \n\t"
+ "bltuc %[a14], %[a13], Lfail \n\t" /* BLTUC */
+ "nop \n\t"
+ "bltuc %[a8], %[a14], L10 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L10: \n\t"
+ "L11: \n\t"
+ "li %[err], 11 \n\t"
+ "bgeuc %[a13], %[a14], Lfail \n\t" /* BGEUC */
+ "nop \n\t"
+ "bgeuc %[a14], %[a8], L12 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L12: \n\t"
+ "L13: \n\t"
+ "li %[err], 13 \n\t"
+ "bltzc %[a13], Lfail \n\t" /* BLTZC */
+ "nop \n\t"
+ "bltzc %[a11], Lfail \n\t"
+ "nop \n\t"
+ "bltzc %[a14], L14 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L14: \n\t"
+ "li %[err], 14 \n\t"
+ "blezc %[a13], Lfail \n\t" /* BLEZC */
+ "nop \n\t"
+ "blezc %[a11], L145 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L145: \n\t"
+ "blezc %[a14], L15 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L15: \n\t"
+ "li %[err], 15 \n\t"
+ "bgezc %[a8], Lfail \n\t" /* BGEZC */
+ "nop \n\t"
+ "bgezc %[a11], L155 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L155: \n\t"
+ "bgezc %[a13], L16 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L16: \n\t"
+ "li %[err], 16 \n\t"
+ "bgtzc %[a8], Lfail \n\t" /* BGTZC */
+ "nop \n\t"
+ "bgtzc %[a11], Lfail \n\t"
+ "nop \n\t"
+ "bgtzc %[a13], L17 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "li %[a10], 0 \n\t"
+ "L17: \n\t"
+ "li %[err], 17 \n\t"
+ "blezalc %[a12], Lfail \n\t" /* BLEZALC */
+ "nop \n\t"
+ "blezalc %[a11], Lret \n\t"
+ "li %[a10], 1 \n\t"
+ "beqzc %[a10], L175 \n\t" /* BEQZC */
+ "nop \n\t"
+ "li %[err], 8531 \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L175: \n\t"
+ "li %[err], 23531 \n\t"
+ "blezalc %[a14], Lret \n\t"
+ "li %[a10], 1 \n\t"
+ "beqzc %[a10], L18 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L18: \n\t"
+ "li %[err], 18 \n\t"
+ "bgezalc %[a14], Lfail \n\t" /* BGEZALC */
+ "nop \n\t"
+ "bgezalc %[a11], Lret \n\t"
+ "li %[a10], 1 \n\t"
+ "beqzc %[a10], L185 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L185: \n\t"
+ "bgezalc %[a12], Lret \n\t"
+ "li %[a10], 1 \n\t"
+ "beqzc %[a10], L19 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L19: \n\t"
+ "li %[err], 19 \n\t"
+ "bgtzalc %[a14], Lfail \n\t" /* BGTZALC */
+ "nop \n\t"
+ "bgtzalc %[a11], Lfail \n\t"
+ "nop \n\t"
+ "bgtzalc %[a12], Lret \n\t"
+ "li %[a10], 1 \n\t"
+ "beqzc %[a10], L20 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L20: \n\t"
+ "li %[err], 20 \n\t"
+ "bltzalc %[a12], Lfail \n\t" /* BLTZALC */
+ "nop \n\t"
+ "bltzalc %[a11], Lfail \n\t"
+ "nop \n\t"
+ "bltzalc %[a14], Lret \n\t"
+ "li %[a10], 1 \n\t"
+ "beqzc %[a10], L21 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L21: \n\t"
+ "li %[err], 21 \n\t"
+ "bc L22 \n\t" /* BC */
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L22: \n\t"
+ "li %[err], 22 \n\t"
+ "balc Lret \n\t" /* BALC */
+ "li %[a10], 1 \n\t"
+ "beqzc %[a10], L23 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L23: \n\t"
+ "li %[err], 23 \n\t"
+ "jal GetPC \n\t" /* JAL */
+ "nop \n\t"
+ "jic $6, 4 \n\t" /* JIC */
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L24: \n\t"
+ "li %[err], 24 \n\t"
+ "li %[a10], 1 \n\t"
+ "jal GetPC \n\t"
+ "nop \n\t"
+ "jialc $6, 20 \n\t" /* JIALC */
+ "nop \n\t"
+ "beqzc %[a10], L25 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "LJIALCRET: \n\t"
+ "li %[a10], 0 \n\t"
+ "jr $31 \n\t" /* JR */
+ "nop \n\t"
+ "L25: \n\t"
+ "li %[err], 25 \n\t"
+ "jal GetPC \n\t"
+ "nop \n\t"
+ "move %[a11], $6 \n\t"
+ "nal \n\t"
+ "nop \n\t"
+ "addiu %[a11], 12 \n\t" /* ADDIU */
+ "beqc %[a11], $31, L26 \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "L26: \n\t"
+ "li %[err], 26 \n\t"
+ "balc Lret \n\t"
+ "li %[a10], 1 \n\t"
+ "beqzc %[a10], Lend \n\t"
+ "nop \n\t"
+ "b Lfail \n\t"
+ "nop \n\t"
+ "Lret: \n\t"
+ "li %[a10], 0 \n\t"
+ "daddiu $31, 4 \n\t" /* DADDIU */
+ "jrc $31 \n\t" /* JRC */
+ "nop \n\t"
+ "GetPC: \n\t"
+ "move $6, $31 \n\t"
+ "jr $31 \n\t"
+ "Lend: \n\t"
+ "li %[err], 0 \n\t"
+ "Lfail: \n\t"
+ ".set pop \n\t" /* Restore previous config */
+ : [err] "+r"(err), [a14] "+r"(a14), [a13] "+r"(a13), [a12] "+r"(a12),
+ [a7] "+r"(a7), [a8] "+r"(a8), [a9] "+r"(a9), [a10] "+r"(a10),
+ [a11] "+r"(a11)
+ : /* inputs */
+ : "$31", "$6" /* clobbers */
+ );
+
+ return err;
+}
+
+/* Tests forbidden slot branching i.e. conditional compact branch
+ instructions. */
+
+int
+test_r6_forbidden (void)
+{
+ volatile int err = -1;
+ volatile int a4 = 0;
+ volatile int a2 = 0;
+ volatile int a1 = 0;
+
+ asm (
+ ".set push \n\t"
+ ".set noreorder \n\t"
+/* Test if FS is ignored when branch is taken */
+ "li %[err], 1 \n\t"
+ "li %[a4], 0 \n\t"
+ "beqzalc %[a4], L41 \n\t"
+ "li %[err], -85 \n\t"
+ "L42: \n\t"
+ "b Lfail2 \n\t"
+ "nop \n\t"
+ "L41: \n\t"
+ "blez %[err], Lfail2 \n\t"
+/* Test if FS is used when branch is not taken */
+ "li %[err], 2 \n\t"
+ "li %[a4], 1 \n\t"
+ "blezc %[a4], L43 \n\t"
+ "addiu %[a4], %[a4], 1 \n\t"
+ "li %[a2], 2 \n\t"
+ "beq %[a4], %[a2], L44 \n\t"
+ "nop \n\t"
+ "L43: \n\t"
+ "nop \n\t"
+ "b Lfail2 \n\t"
+ "nop \n\t"
+ "L44: \n\t"
+ "li %[err], 3 \n\t"
+ "li %[a4], 3 \n\t"
+ "beqzalc %[a4], Lfail2 \n\t"
+/* Note: 'bc L45' instead nop would cause SegFault: Illegal instruction:
+ Forbidden slot causes an error when it contains a branch. */
+ "nop \n\t"
+ "b Lend2 \n\t"
+ "nop \n\t"
+ "L45: \n\t"
+ "nop \n\t"
+ "b Lfail2 \n\t"
+ "nop \n\t"
+ "Lend2: \n\t"
+ "li %[err], 0 \n\t"
+ "Lfail2: \n\t"
+ "nop \n\t"
+ ".set pop \n\t"
+ : [err] "+r" (err), [a4] "+r"(a4), [a2] "+r"(a2), [a1] "+r"(a1) /* outputs */
+ : /* inputs */
+ : "$31" /* clobbers */
+ );
+
+ return err;
+}
+
+int
+test_r6_64 (void)
+{
+ volatile int err = 0;
+
+ asm (
+ ".set push \n\t"
+ ".set noreorder \n\t"
+ ".data \n\t"
+ "dval: .dword 0xaa55bb66cc77dd88 \n\t"
+ "d1: .dword 0xaaaabbbbccccdddd \n\t"
+ "d5: .dword 0x00000000000000dd \n\t"
+ "d7: .dword 0xeeeeffff00001111 \n\t"
+ "d8: .dword 0xbbccccddddeeeeff \n\t"
+ "d9: .dword 0x000000ddaaaabbbb \n\t"
+ "dval1: .word 0x1234abcd \n\t"
+ "dval2: .word 0xffee0000 \n\t"
+ "dval3: .dword 0xffffffffffffffff \n\t"
+ " .fill 240,1,0 \n\t"
+ "dval4: .dword 0x5555555555555555 \n\t"
+ " .fill 264,1,0 \n\t"
+
+/* Register $11 stores instruction currently being tested and hence
+ * identifies error if it occurs. */
+ ".text \n\t"
+
+ "li $11, 1 \n\t" /* Test DALIGN */
+ r6ck_2dr1i (dalign, d7, d1, 3, d8)
+ r6ck_2dr1i (dalign, d1, d5, 4, d9)
+
+ "li $11, 2 \n\t" /* Test LDPC */
+ "ld $5, dval \n\t"
+ "nop \n\t"
+ "ldpc $4, dval \n\t"
+ fp_assert ($4, $5)
+
+ "li $11, 3 \n\t" /* Test LWUPC */
+ "lwu $5, dval1 \n\t"
+ "lwupc $4, dval1 \n\t"
+ fp_assert ($4, $5)
+ "lwu $5, dval2 \n\t"
+ "lwupc $4, dval2 \n\t"
+ fp_assert ($4, $5)
+
+ "li $11, 4 \n\t" /* Test LLD */
+ "ld $5, dval3 \n\t"
+ "dla $3, dval4 \n\t"
+ "lld $4, -248($3) \n\t"
+ fp_assert ($4, $5)
+
+ "li $11, 5 \n\t" /* Test SCD */
+ "lld $4, -248($3) \n\t"
+ "dli $4, 0xafaf \n\t"
+ "scd $4, -248($3) \n\t"
+ "ld $5, dval3 \n\t"
+ "dli $4, 0xafaf \n\t"
+ fp_assert ($4, $5)
+
+ "Lend3: \n\t"
+ "li $11, 0 \n\t"
+ "58: \n\t"
+ "move %[err], $11 \n\t"
+ ".set pop \n\t"
+ : [err] "+r" (err) /* outputs */
+ : /* inputs */
+ : "$3", "$4", "$5", "$6", "$7", "$11" /* clobbers */
+ );
+
+ return err;
+}
+
+int
+test_r6 (void)
+{
+ volatile int err = 0;
+
+ asm (
+ ".set push \n\t"
+ ".set noreorder \n\t"
+ ".data \n\t"
+ "dval_1: .word 0xabcd1234 \n\t"
+ "dval_2: .word 0x1234eeff \n\t"
+ ".fill 248,1,0 \n\t"
+ "dval_3: .word 0x55555555 \n\t"
+ ".fill 260,1,0 \n\t"
+ "dval_4: .word 0xaaaaaaaa \n\t"
+ ".text \n\t"
+ "li $11, 1 \n\t" /* ADDIUPC */
+ "jal GetPC_2 \n\t"
+ "nop \n\t"
+ "addiu $4, $6, 8 \n\t"
+ "addiupc $5, 4 \n\t"
+ fp_assert ($4, $5)
+
+ "li $11, 2 \n\t" /* AUIPC */
+ "jal GetPC_2 \n\t"
+ "nop \n\t"
+ "addiu $4, $6, 8 \n\t"
+ "aui $4, $4, 8 \n\t"
+ "auipc $5, 8 \n\t"
+ fp_assert ($4, $5)
+
+ "li $11, 3 \n\t" /* ALUIPC */
+ "jal GetPC_2 \n\t"
+ "nop \n\t"
+ "addiu $4, $6, 16 \n\t"
+ "aui $4, $4, 8 \n\t"
+ "li $7, 0xffff0000 \n\t"
+ "and $4, $4, $7 \n\t"
+ "aluipc $5, 8 \n\t"
+ fp_assert ($4, $5)
+
+ "li $11, 4 \n\t" /* LWPC */
+ "lw $5, dval_1 \n\t"
+ "lwpc $4, dval_1 \n\t"
+ fp_assert ($4, $5)
+ "lw $5, dval_2 \n\t"
+ "lwpc $4, dval_2 \n\t"
+ fp_assert ($4, $5)
+
+/* Testing LL follows.
+ * NOTE: May be redundant because SC already contains LL in its test. */
+ "li $11, 5 \n\t"
+ "lw $5, dval_2 \n\t"
+ "dla $3, dval_3 \n\t"
+ "ll $4, -252($3) \n\t"
+ fp_assert ($4, $5)
+
+ "li $11, 6 \n\t" /* LL-SC sequence */
+ "ll $4, -252($3) \n\t"
+ "li $4, 0xafaf \n\t"
+ "sc $4, -252($3) \n\t"
+ "lw $5, dval_2 \n\t"
+ "li $4, 0xafaf \n\t"
+ fp_assert ($4, $5)
+ "b Lend4 \n\t"
+ "nop \n\t"
+ "GetPC_2: \n\t"
+ "move $6, $31 \n\t"
+ "jr $31 \n\t"
+ "Lend4: \n\t"
+ "li $11, 0 \n\t"
+ "58: \n\t"
+ "move %[err], $11 \n\t"
+ ".set pop \n\t"
+ : [err] "+r"(err) /* outputs */
+ : /* inputs */
+ : "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
+ "$11", "$31" /* clobbers */
+ );
+
+ return err;
+}
+
+/* For fpu-branching testing, bc1eq/eqz are enough. */
+
+int
+test_r6_fpu (void)
+{
+ volatile int err = 0;
+
+ asm (
+ ".set push \n\t"
+ ".set noreorder \n\t"
+/* Test qNaN format is 754-2008 */
+ "li $11, 1 \n\t"
+ "li $4, 0x0 \n\t"
+ "li $5, 0x0 \n\t"
+ "li $6, 0x7fc00000 \n\t"
+ "mtc1 $4, $f2 \n\t"
+ "mtc1 $5, $f4 \n\t"
+ "div.s $f6, $f2, $f4 \n\t"
+ "mfc1 $8, $f6 \n\t"
+ fp_assert ($6, $8)
+
+ "li $11, 2 \n\t" /* bc1eqz */
+ "li $10, 0x01 \n\t"
+ "mtc1 $10, $f2 \n\t"
+ "mtc1 $0, $f4 \n\t"
+ "bc1eqz $f2, 58f \n\t"
+ "nop \n\t"
+ "bc1eqz $f4, L62 \n\t"
+ "nop \n\t"
+ "b 58f \n\t"
+ "nop \n\t"
+"L62: \n\t"
+ "li $11, 3 \n\t" /* bc1nez */
+ "bc1nez $f4, 58f \n\t"
+ "nop \n\t"
+ "bc1nez $f2, Lend8 \n\t"
+ "nop \n\t"
+ "b 58f \n\t"
+ "nop \n\t"
+"Lend8: \n\t"
+ "li $11, 0 \n\t"
+ "58: \n\t"
+ "move %[err], $11 \n\t"
+ ".set pop \n\t"
+ : [err] "+r"(err) /* outputs */
+ : /* inputs */
+ : "$4", "$5", "$6", "$8", "$10", "$11", "$31",
+ "$f2", "$f4", "$f6" /* clobbers */
+ );
+
+ return err;
+}
+
+/* R6 specific tests for mips64 (64-bit). */
+
+int
+test_r6_llsc_dp (void)
+{
+ volatile int err = 0;
+
+ asm (
+ ".set push \n\t"
+ ".set noreorder \n\t"
+ ".data \n\t"
+ ".align 16 \n\t"
+ "test_data: \n\t"
+ ".word 0xaaaaaaaa \n\t"
+ ".word 0xbbbbbbbb \n\t"
+ ".word 0xcccccccc \n\t"
+ ".word 0xdddddddd \n\t"
+ ".align 16 \n\t"
+ "end_check: \n\t"
+ ".byte 0 \n\t"
+ ".byte 0 \n\t"
+ ".byte 0 \n\t"
+ ".byte 0x1 \n\t"
+ ".text \n\t"
+ "li $11, 1 \n\t" /* LLWP */
+ "llwp $2, $3, test_data \n\t"
+ checkpair_dword ($2, $3, test_data, end_check)
+ "sll $2, $2, 1 \n\t"
+ "srl $3, $3, 1 \n\t"
+ "move $s0, $2 \n\t"
+ "scwp $2, $3, test_data \n\t"
+ check32 ($2, 1)
+ checkpair_dword ($s0, $3, test_data, end_check)
+ /* Test SCWP, done */
+ "li $11, 2 \n\t"
+ "li $11, 3 \n\t" /* LLDP */
+ "lldp $2, $3, test_data \n\t"
+ checkpair_qword ($2, $3, test_data, end_check)
+ "dsll $2, $2, 1 \n\t"
+ "dsrl $3, $3, 1 \n\t"
+ "move $s0, $2 \n\t"
+ "scdp $2, $3, test_data \n\t"
+ check32 ($2, 1)
+ checkpair_qword ($s0, $3, test_data, end_check)
+ "li $11, 4 \n\t" /* SCDP done */
+ "Lend5: \n\t"
+ "li $11, 0 \n\t"
+ "58: \n\t"
+ "move %[err], $11 \n\t"
+ ".set pop \n\t"
+ : [err] "+r"(err) /* outputs */
+ : /* inputs */
+ : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11",
+ "$31", "$s0" /* clobbers */
+ );
+
+ return err;
+}
+
+/* R6 specific tests for mips32 (32-bit). */
+
+int
+test_r6_llsc_wp (void)
+{
+ volatile int err = 0;
+
+ asm (
+ ".set push \n\t"
+ ".set noreorder \n\t"
+ ".data \n\t"
+ ".align 8 \n\t"
+ "test_data_2: \n\t"
+ ".word 0xaaaaaaaa \n\t"
+ ".word 0xbbbbbbbb \n\t"
+ ".align 8 \n\t"
+ "end_check_2: \n\t"
+ ".byte 0 \n\t"
+ ".byte 0 \n\t"
+ ".byte 0 \n\t"
+ ".byte 0x1 \n\t"
+ ".text \n\t"
+ "li $11, 1 \n\t" /* Test LLWP */
+ "llwp $2, $3, test_data_2 \n\t"
+ checkpair_dword ($2, $3, test_data_2, end_check_2)
+ "sll $2, $2, 1 \n\t"
+ "srl $3, $3, 1 \n\t"
+ "move $s0, $2 \n\t"
+ "scwp $2, $3, test_data_2 \n\t"
+ check32 ($2, 1)
+ checkpair_dword ($s0, $3, test_data_2, end_check_2)
+/* Test SCWP, done. */
+ "li $11, 2 \n\t"
+ "Lend6: \n\t"
+ "li $11, 0 \n\t"
+ "58: \n\t"
+ "move %[err], $11 \n\t"
+ ".set pop \n\t"
+ : [err] "+r"(err) /* outputs */
+ : /* inputs */
+ : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
+ "$11", "$31", "$s0" /* clobbers */
+ );
+
+ return err;
+}
+
+/* If any test_r6_* function returns non-zero, it's a failure. */
+#define EXPECT(X) if ((X)) abort ();
+
+int
+main (void)
+{
+ EXPECT (test_r6_branch ());
+
+ EXPECT (test_r6_forbidden ());
+
+ EXPECT (test_r6_64 ());
+
+ EXPECT (test_r6 ());
+
+ EXPECT (test_r6_fpu ());
+
+ EXPECT (test_r6_llsc_dp ());
+
+ EXPECT (test_r6_llsc_wp ());
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/mips-64-r6.exp b/gdb/testsuite/gdb.arch/mips-64-r6.exp
new file mode 100644
index 00000000000..fe5d6f58252
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/mips-64-r6.exp
@@ -0,0 +1,74 @@
+# Copyright (C) 2023-2025 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, see <http://www.gnu.org/licenses/>.
+
+################################################################
+################## MIPS Release 6 patch tests ##################
+################################################################
+
+# Send 'si' to gdb until inferior exits.
+proc stepi {} {
+ global gdb_prompt
+ set timeout [get_largest_timeout]
+ set start [timestamp]
+ while { [timestamp] - $start < 3*$timeout } {
+ gdb_test_multiple "stepi" "" {
+ -re ".*exited normally.*" {
+ pass "success"
+ return
+ }
+ -re ".*The program is not being run.*" {
+ fail "failure"
+ return
+ }
+ -re ".*Breakpoint.*test_.*$gdb_prompt $" {
+ }
+ -re "$gdb_prompt.*" {
+ }
+ }
+ }
+ fail "test failed"
+ return
+}
+
+require {istarget "mips*"}
+
+standard_testfile
+
+if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile} {debug nowarnings}] } {
+ untested "failed to prepare"
+ return
+}
+
+# Native needs run.
+if { ![runto_main] } {
+ untested "couldn't run to main"
+ return
+}
+
+set tests ""
+foreach n [list "r6_branch" "r6_forbidden" "r6_64" "r6" "r6_fpu" "r6_llsc_dp" "r6_llsc_wp"] {
+ lappend tests "test_$n"
+}
+
+# Put breakpoint on each test-function
+foreach func $tests {
+ if {![gdb_breakpoint "$func"]} {
+ untested "couldn't put breakpoint to $func"
+ return
+ }
+}
+
+# Step through the binary
+stepi
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread