[PATCH v13 1/2] gdb: mips: Apply coding guidelines

[Jovan Dmitrovic <jovan.dmitrovic@htecgroup.com>]

From: Milica Matic <milica.matic@htecgroup.com>

Format mips-tdep.c code as described on links:
https://sourceware.org/gdb/wiki/Internals%20GDB-C-Coding-Standards
https://www.gnu.org/prep/standards/standards.html#Comments

Signed-off-by: Milica Matic <milica.matic@htecgroup.com>
Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com>
---
 gdb/mips-tdep.c | 315 ++++++++++++++++++++++++++++--------------------
 1 file changed, 184 insertions(+), 131 deletions(-)

diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index c64cd47c8b6..48284abdd73 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -76,8 +76,8 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
 static void mips_print_float_info (struct gdbarch *, struct ui_file *,
 				   const frame_info_ptr &, const char *);
 
-/* A useful bit in the CP0 status register (MIPS_PS_REGNUM).  */
-/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip.  */
+/* A useful bit in the CP0 status register (MIPS_PS_REGNUM).
+   This bit is set if we are emulating 32-bit FPRs on a 64-bit chip.  */
 #define ST0_FR (1 << 26)
 
 /* The sizes of floating point registers.  */
@@ -1076,21 +1076,29 @@ mips_register_type (struct gdbarch *gdbarch, int regnum)
       else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
 	       && rawnum >= MIPS_FIRST_EMBED_REGNUM
 	       && rawnum <= MIPS_LAST_EMBED_REGNUM)
-	/* The pseudo/cooked view of the embedded registers is always
-	   32-bit.  The raw view is handled below.  */
-	return builtin_type (gdbarch)->builtin_int32;
+	{
+	  /* The pseudo/cooked view of the embedded registers is always
+	     32-bit.  The raw view is handled below.  */
+	  return builtin_type (gdbarch)->builtin_int32;
+	}
       else if (tdep->mips64_transfers_32bit_regs_p)
-	/* The target, while possibly using a 64-bit register buffer,
-	   is only transferring 32-bits of each integer register.
-	   Reflect this in the cooked/pseudo (ABI) register value.  */
-	return builtin_type (gdbarch)->builtin_int32;
+	{
+	  /* The target, while possibly using a 64-bit register buffer,
+	     is only transferring 32-bits of each integer register.
+	     Reflect this in the cooked/pseudo (ABI) register value.  */
+	  return builtin_type (gdbarch)->builtin_int32;
+	}
       else if (mips_abi_regsize (gdbarch) == 4)
-	/* The ABI is restricted to 32-bit registers (the ISA could be
-	   32- or 64-bit).  */
-	return builtin_type (gdbarch)->builtin_int32;
+	{
+	  /* The ABI is restricted to 32-bit registers (the ISA could be
+	     32- or 64-bit).  */
+	  return builtin_type (gdbarch)->builtin_int32;
+	}
       else
-	/* 64-bit ABI.  */
-	return builtin_type (gdbarch)->builtin_int64;
+	{
+	  /* 64-bit ABI.  */
+	  return builtin_type (gdbarch)->builtin_int64;
+	}
     }
 }
 
@@ -1598,8 +1606,10 @@ mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
   int cond;
 
   if (fcsr == -1)
-    /* No way to handle; it'll most likely trap anyway.  */
-    return pc;
+    {
+      /* No way to handle; it'll most likely trap anyway.  */
+      return pc;
+    }
 
   fcs = regcache_raw_get_unsigned (regcache, fcsr);
   cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
@@ -1631,10 +1641,10 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
 {
   if (!is_octeon (gdbarch))
     return 0;
-  /* BBIT0 is encoded as LWC2: 110 010.  */
-  /* BBIT032 is encoded as LDC2: 110 110.  */
-  /* BBIT1 is encoded as SWC2: 111 010.  */
-  /* BBIT132 is encoded as SDC2: 111 110.  */
+  /* BBIT0 is encoded as LWC2: 110 010.
+     BBIT032 is encoded as LDC2: 110 110.
+     BBIT1 is encoded as SWC2: 111 010.
+     BBIT132 is encoded as SDC2: 111 110.  */
   if (op == 50 || op == 54 || op == 58 || op == 62)
     return 1;
   return 0;
@@ -1652,12 +1662,11 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
   int op;
   inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
   op = itype_op (inst);
-  if ((inst & 0xe0000000) != 0)		/* Not a special, jump or branch
-					   instruction.  */
+  if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction.  */
     {
       if (op >> 2 == 5)
-	/* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
 	{
+	  /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
 	  switch (op & 0x03)
 	    {
 	    case 0:		/* BEQL */
@@ -1673,20 +1682,26 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 	    }
 	}
       else if (op == 17 && itype_rs (inst) == 8)
-	/* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
-	pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);
+	{
+	  /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
+	  pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);
+	}
       else if (op == 17 && itype_rs (inst) == 9
 	       && (itype_rt (inst) & 2) == 0)
-	/* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
-	pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);
+	{
+	  /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
+	  pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);
+	}
       else if (op == 17 && itype_rs (inst) == 10
 	       && (itype_rt (inst) & 2) == 0)
-	/* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
-	pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);
+	{
+	  /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
+	  pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);
+	}
       else if (op == 29)
-	/* JALX: 011101 */
-	/* The new PC will be alternate mode.  */
 	{
+	  /* JALX: 011101
+	     The new PC will be alternate mode.  */
 	  unsigned long reg;
 
 	  reg = jtype_target (inst) << 2;
@@ -1700,27 +1715,33 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 	  branch_if = op == 58 || op == 62;
 	  bit = itype_rt (inst);
 
-	  /* Take into account the *32 instructions.  */
 	  if (op == 54 || op == 62)
-	    bit += 32;
+	    {
+	      /* Take into account the *32 instructions.  */
+	      bit += 32;
+	    }
 
 	  if (((regcache_raw_get_signed (regcache,
 					 itype_rs (inst)) >> bit) & 1)
 	      == branch_if)
 	    pc += mips32_relative_offset (inst) + 4;
 	  else
-	    pc += 8;		/* After the delay slot.  */
+	    {
+	      /* After the delay slot.  */
+	      pc += 8;
+	    }
 	}
+
       else
 	pc += 4;		/* Not a branch, next instruction is easy.  */
     }
   else
-    {				/* This gets way messy.  */
-
-      /* Further subdivide into SPECIAL, REGIMM and other.  */
+    {
+      /* This gets way messy.
+	 Further subdivide into SPECIAL, REGIMM and other.  */
       switch (op & 0x07)	/* Extract bits 28,27,26.  */
 	{
-	case 0:		/* SPECIAL */
+	case 0:  /* SPECIAL */
 	  op = rtype_funct (inst);
 	  switch (op)
 	    {
@@ -1729,7 +1750,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 	      /* Set PC to that address.  */
 	      pc = regcache_raw_get_signed (regcache, rtype_rs (inst));
 	      break;
-	    case 12:		/* SYSCALL */
+	    case 12:	    /* SYSCALL */
 	      {
 		mips_gdbarch_tdep *tdep
 		  = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
@@ -1744,10 +1765,10 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 	      pc += 4;
 	    }
 
-	  break;	/* end SPECIAL */
-	case 1:		/* REGIMM */
+	  break;  /* end SPECIAL */
+	case 1:  /* REGIMM */
 	  {
-	    op = itype_rt (inst);	/* Branch condition.  */
+	    op = itype_rt (inst);  /* branch condition */
 	    switch (op)
 	      {
 	      case 0:		/* BLTZ */
@@ -1758,7 +1779,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 		if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)
 		  pc += mips32_relative_offset (inst) + 4;
 		else
-		  pc += 8;	/* After the delay slot.  */
+		  pc += 8;	/* after the delay slot */
 		break;
 	      case 1:		/* BGEZ */
 	      case 3:		/* BGEZL */
@@ -1767,7 +1788,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 		if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0)
 		  pc += mips32_relative_offset (inst) + 4;
 		else
-		  pc += 8;	/* After the delay slot.  */
+		  pc += 8;	/* after the delay slot */
 		break;
 	      case 0x1c:	/* BPOSGE32 */
 	      case 0x1e:	/* BPOSGE64 */
@@ -1778,8 +1799,10 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 		    int dspctl = mips_regnum (gdbarch)->dspctl;
 
 		    if (dspctl == -1)
-		      /* No way to handle; it'll most likely trap anyway.  */
-		      break;
+		      {
+			/* No way to handle; it'll most likely trap anyway.  */
+			break;
+		      }
 
 		    if ((regcache_raw_get_unsigned (regcache,
 						    dspctl) & 0x7f) >= pos)
@@ -1793,7 +1816,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 		pc += 4;
 	      }
 	  }
-	  break;	/* end REGIMM */
+	  break;  /* end REGIMM */
 	case 2:		/* J */
 	case 3:		/* JAL */
 	  {
@@ -1827,7 +1850,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
 	  break;
 	case 7:
 	default:
-	greater_branch:	/* BGTZ, BGTZL */
+	greater_branch: /* BGTZ, BGTZL */
 	  if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)
 	    pc += mips32_relative_offset (inst) + 4;
 	  else
@@ -1893,8 +1916,10 @@ micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
   int cond;
 
   if (fcsr == -1)
-    /* No way to handle; it'll most likely trap anyway.  */
-    return pc;
+    {
+      /* No way to handle; it'll most likely trap anyway.  */
+      return pc;
+    }
 
   fcs = regcache_raw_get_unsigned (regcache, fcsr);
   cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
@@ -2008,8 +2033,10 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
 	    case 0x14: /* BC2F: bits 010000 10100 xxx00 */
 	    case 0x15: /* BC2T: bits 010000 10101 xxx00 */
 	      if (((insn >> 16) & 0x3) == 0x0)
-		/* BC2F, BC2T: don't know how to handle these.  */
-		break;
+		{
+		  /* BC2F, BC2T: don't know how to handle these.  */
+		  break;
+		}
 	      break;
 
 	    case 0x1a: /* BPOSGE64: bits 010000 11010 */
@@ -2019,8 +2046,10 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
 		int dspctl = mips_regnum (gdbarch)->dspctl;
 
 		if (dspctl == -1)
-		  /* No way to handle; it'll most likely trap anyway.  */
-		  break;
+		  {
+		    /* No way to handle; it'll most likely trap anyway.  */
+		    break;
+		  }
 
 		if ((regcache_raw_get_unsigned (regcache,
 						dspctl) & 0x7f) >= pos)
@@ -2055,7 +2084,7 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
 
 	case 0x25: /* BEQ: bits 100101 */
 	  if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
-	      == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
+		== regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
 	    pc += micromips_relative_offset16 (insn);
 	  else
 	    pc += micromips_pc_insn_size (gdbarch, pc);
@@ -2063,7 +2092,7 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
 
 	case 0x2d: /* BNE: bits 101101 */
 	  if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
-	      != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
+		!= regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
 	    pc += micromips_relative_offset16 (insn);
 	  else
 	    pc += micromips_pc_insn_size (gdbarch, pc);
@@ -2081,11 +2110,15 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
 	{
 	case 0x11: /* POOL16C: bits 010001 */
 	  if ((b5s5_op (insn) & 0x1c) == 0xc)
-	    /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
-	    pc = regcache_raw_get_signed (regcache, b0s5_reg (insn));
+	    {
+	      /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
+	      pc = regcache_raw_get_signed (regcache, b0s5_reg (insn));
+	    }
 	  else if (b5s5_op (insn) == 0x18)
-	    /* JRADDIUSP: bits 010001 11000 */
-	    pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM);
+	    {
+	      /* JRADDIUSP: bits 010001 11000 */
+	      pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM);
+	    }
 	  break;
 
 	case 0x23: /* BEQZ16: bits 100011 */
@@ -2540,10 +2573,10 @@ mips16_scan_prologue (struct gdbarch *gdbarch,
   long frame_offset = 0;	/* Size of stack frame.  */
   long frame_adjust = 0;	/* Offset of FP from SP.  */
   int frame_reg = MIPS_SP_REGNUM;
-  unsigned short prev_inst = 0;	/* Saved copy of previous instruction.  */
-  unsigned inst = 0;		/* Current instruction.  */
-  unsigned entry_inst = 0;	/* The entry instruction.  */
-  unsigned save_inst = 0;	/* The save instruction.  */
+  unsigned short prev_inst = 0;	/* saved copy of previous instruction.  */
+  unsigned inst = 0;		/* current instruction */
+  unsigned entry_inst = 0;	/* the entry instruction */
+  unsigned save_inst = 0;	/* the save instruction */
   int prev_delay_slot = 0;
   int in_delay_slot;
   int reg, offset;
@@ -2602,10 +2635,12 @@ mips16_scan_prologue (struct gdbarch *gdbarch,
 	  if (offset < 0)	/* Negative stack adjustment?  */
 	    frame_offset -= offset;
 	  else
-	    /* Exit loop if a positive stack adjustment is found, which
-	       usually means that the stack cleanup code in the function
-	       epilogue is reached.  */
-	    break;
+	    {
+	      /* Exit loop if a positive stack adjustment is found, which
+		 usually means that the stack cleanup code in the function
+		 epilogue is reached.  */
+	      break;
+	    }
 	}
       else if ((inst & 0xf800) == 0xd000)	/* sw reg,n($sp) */
 	{
@@ -3501,10 +3536,12 @@ mips32_scan_prologue (struct gdbarch *gdbarch,
 	  if (offset < 0)		/* Negative stack adjustment?  */
 	    frame_offset -= offset;
 	  else
-	    /* Exit loop if a positive stack adjustment is found, which
-	       usually means that the stack cleanup code in the function
-	       epilogue is reached.  */
-	    break;
+	    {
+	      /* Exit loop if a positive stack adjustment is found, which
+		 usually means that the stack cleanup code in the function
+		 epilogue is reached.  */
+	      break;
+	    }
 	  seen_sp_adjust = 1;
 	}
       else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
@@ -3578,7 +3615,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch,
 		}
 	    }
 	}
-      else if ((high_word & 0xFFE0) == 0xafc0	/* sw reg,offset($30) */
+      else if ((high_word & 0xFFE0) == 0xafc0		/* sw reg,offset($30) */
 	       && !regsize_is_64_bits)
 	{
 	  set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
@@ -3906,22 +3943,24 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
   mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
 
   if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
-    /* This hack is a work-around for existing boards using PMON, the
-       simulator, and any other 64-bit targets that doesn't have true
-       64-bit addressing.  On these targets, the upper 32 bits of
-       addresses are ignored by the hardware.  Thus, the PC or SP are
-       likely to have been sign extended to all 1s by instruction
-       sequences that load 32-bit addresses.  For example, a typical
-       piece of code that loads an address is this:
-
-       lui $r2, <upper 16 bits>
-       ori $r2, <lower 16 bits>
-
-       But the lui sign-extends the value such that the upper 32 bits
-       may be all 1s.  The workaround is simply to mask off these
-       bits.  In the future, gcc may be changed to support true 64-bit
-       addressing, and this masking will have to be disabled.  */
-    return addr &= 0xffffffffUL;
+    {
+      /* This hack is a work-around for existing boards using PMON, the
+	 simulator, and any other 64-bit targets that doesn't have true
+	 64-bit addressing.  On these targets, the upper 32 bits of
+	 addresses are ignored by the hardware.  Thus, the PC or SP are
+	 likely to have been sign extended to all 1s by instruction
+	 sequences that load 32-bit addresses.  For example, a typical
+	 piece of code that loads an address is this:
+
+	 lui $r2, <upper 16 bits>
+	 ori $r2, <lower 16 bits>
+
+	 But the lui sign-extends the value such that the upper 32 bits
+	 may be all 1s.  The workaround is simply to mask off these
+	 bits.  In the future, gcc may be changed to support true 64-bit
+	 addressing, and this masking will have to be disabled.  */
+      return addr &= 0xffffffffUL;
+    }
   else
     return addr;
 }
@@ -6722,7 +6761,7 @@ mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
      that bound, then use an arbitrary large number as the upper bound.  */
   limit_pc = skip_prologue_using_sal (gdbarch, pc);
   if (limit_pc == 0)
-    limit_pc = pc + 100;	/* Magic.  */
+    limit_pc = pc + 100;	  /* Magic.  */
 
   if (mips_pc_is_mips16 (gdbarch, pc))
     return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
@@ -7027,7 +7066,7 @@ gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
 
   /* FIXME: cagney/2003-06-26: Is this even necessary?  The
      disassembler needs to be able to locally determine the ISA, and
-     not rely on GDB.  Otherwise the stand-alone 'objdump -d' will not
+     not rely on GDB.  Otherwize the stand-alone 'objdump -d' will not
      work.  */
   if (mips_pc_is_mips16 (gdbarch, memaddr))
     info->mach = bfd_mach_mips16;
@@ -7435,36 +7474,42 @@ mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
 	    break;
 	  addr -= MIPS_INSN16_SIZE;
 	  if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0))
-	    /* Looks like a JR/JALR at [target-1], but it could be
-	       the second word of a previous JAL/JALX, so record it
-	       and check back one more.  */
-	    jmpaddr = addr;
+	    {
+	      /* Looks like a JR/JALR at [target-1], but it could be
+		 the second word of a previous JAL/JALX, so record it
+		 and check back one more.  */
+	      jmpaddr = addr;
+	    }
 	  else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1))
 	    {
 	      if (i == 2)
-		/* Looks like a JAL/JALX at [target-2], but it could also
-		   be the second word of a previous JAL/JALX, record it,
-		   and check back one more.  */
-		jmpaddr = addr;
+		{
+		  /* Looks like a JAL/JALX at [target-2], but it could also
+		     be the second word of a previous JAL/JALX, record it,
+		     and check back one more.  */
+		  jmpaddr = addr;
+		}
 	      else
-		/* Looks like a JAL/JALX at [target-3], so any previously
-		   recorded JAL/JALX or JR/JALR must be wrong, because:
-
-		   >-3: JAL
-		    -2: JAL-ext (can't be JAL/JALX)
-		    -1: bdslot (can't be JR/JALR)
-		     0: target insn
-
-		   Of course it could be another JAL-ext which looks
-		   like a JAL, but in that case we'd have broken out
-		   of this loop at [target-2]:
-
-		    -4: JAL
-		   >-3: JAL-ext
-		    -2: bdslot (can't be jmp)
-		    -1: JR/JALR
-		     0: target insn  */
-		jmpaddr = 0;
+		{
+		  /* Looks like a JAL/JALX at [target-3], so any previously
+		     recorded JAL/JALX or JR/JALR must be wrong, because:
+
+		       >-3: JAL
+			-2: JAL-ext (can't be JAL/JALX)
+			-1: bdslot (can't be JR/JALR)
+			 0: target insn
+
+		     Of course it could be another JAL-ext which looks
+		     like a JAL, but in that case we'd have broken out
+		     of this loop at [target-2]:
+
+			-4: JAL
+		       >-3: JAL-ext
+			-2: bdslot (can't be jmp)
+			-1: JR/JALR
+			 0: target insn  */
+		  jmpaddr = 0;
+		}
 	    }
 	  else
 	    {
@@ -7731,15 +7776,19 @@ mips_skip_mips16_trampoline_code (const frame_info_ptr &frame, CORE_ADDR pc)
 	       && mips_is_stub_suffix (name + prefixlen + 3, 0))
 	{
 	  if (pc == start_addr)
-	    /* This is the 'call' part of a call stub.  The return
-	       address is in $2.  */
-	    return get_frame_register_signed
+	    {
+	      /* This is the 'call' part of a call stub.  The return
+		 address is in $2.  */
+	      return get_frame_register_signed
 		     (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
+	    }
 	  else
-	    /* This is the 'return' part of a call stub.  The return
-	       address is in $18.  */
-	    return get_frame_register_signed
+	    {
+	      /* This is the 'return' part of a call stub.  The return
+		 address is in $18.  */
+	      return get_frame_register_signed
 		     (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
+	    }
 	}
       else
 	return 0;		/* Not a stub.  */
@@ -7751,15 +7800,19 @@ mips_skip_mips16_trampoline_code (const frame_info_ptr &frame, CORE_ADDR pc)
       || startswith (name, mips_str_call_stub))
     {
       if (pc == start_addr)
-	/* This is the 'call' part of a call stub.  Call this helper
-	   to scan through this code for interesting instructions
-	   and determine the final PC.  */
-	return mips_get_mips16_fn_stub_pc (frame, pc);
+	{
+	  /* This is the 'call' part of a call stub.  Call this helper
+	     to scan through this code for interesting instructions
+	     and determine the final PC.  */
+	  return mips_get_mips16_fn_stub_pc (frame, pc);
+	}
       else
-	/* This is the 'return' part of a call stub.  The return address
-	   is in $18.  */
-	return get_frame_register_signed
+	{
+	  /* This is the 'return' part of a call stub.  The return address
+	     is in $18.  */
+	  return get_frame_register_signed
 		 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
+	}
     }
 
   return 0;			/* Not a stub.  */
@@ -7974,7 +8027,7 @@ mips_integer_to_address (struct gdbarch *gdbarch,
    an assertion failure.  */
 
 static void
-mips_virtual_frame_pointer (struct gdbarch *gdbarch,
+mips_virtual_frame_pointer (struct gdbarch *gdbarch, 
 			    CORE_ADDR pc, int *reg, LONGEST *offset)
 {
   *reg = MIPS_SP_REGNUM;
-- 
2.34.1