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From: Mike Frysinger via Gdb-patches <gdb-patches@sourceware.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 3/6] sim: sh: fix various parentheses warnings
Date: Sat,  6 Nov 2021 20:32:51 -0400	[thread overview]
Message-ID: <20211107003254.4298-3-vapier@gentoo.org> (raw)
In-Reply-To: <20211107003254.4298-1-vapier@gentoo.org>

Add parentheses to a bunch of places where the compiler suggests we
do to avoid confusion to most readers.
---
 sim/sh/gencode.c | 18 +++++++++---------
 sim/sh/interp.c  |  4 ++--
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index ae44bc8825b8..28b483208f3a 100644
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -1863,7 +1863,7 @@ op ppi_tab[] =
     "if (i <= 16)",
     "  res = Sz << i;",
     "else if (i >= 128 - 16)",
-    "  res = (unsigned) Sz >> 128 - i;	/* no sign extension */",
+    "  res = (unsigned) Sz >> (128 - i);	/* no sign extension */",
     "else",
     "  {",
     "    RAISE_EXCEPTION (SIGILL);",
@@ -1887,7 +1887,7 @@ op ppi_tab[] =
     "    else",
     "      {",
     "        res = Sz << i;",
-    "        res_grd = Sz_grd << i | (unsigned) Sz >> 32 - i;",
+    "        res_grd = Sz_grd << i | (unsigned) Sz >> (32 - i);",
     "      }",
     "    res_grd = SEXT (res_grd);",
     "    carry = res_grd & 1;",
@@ -1902,7 +1902,7 @@ op ppi_tab[] =
     "      }",
     "    else",
     "      {",
-    "        res = Sz >> i | Sz_grd << 32 - i;",
+    "        res = Sz >> i | Sz_grd << (32 - i);",
     "        res_grd = Sz_grd >> i;",
     "      }",
     "    carry = Sz >> (i - 1) & 1;",
@@ -1973,7 +1973,7 @@ op ppi_tab[] =
     "ADD_SUB_GE;",
     "DSR &= ~0xf1;\n",
     "if (res || res_grd)\n",
-    "  DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n",
+    "  DSR |= greater_equal | (res_grd >> 2 & DSR_MASK_N) | overflow;\n",
     "else\n",
     "  DSR |= DSR_MASK_Z | overflow;\n",
     "DSR |= carry;\n",
@@ -1992,7 +1992,7 @@ op ppi_tab[] =
     "ADD_SUB_GE;",
     "DSR &= ~0xf1;\n",
     "if (res || res_grd)\n",
-    "  DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n",
+    "  DSR |= greater_equal | (res_grd >> 2 & DSR_MASK_N) | overflow;\n",
     "else\n",
     "  DSR |= DSR_MASK_Z | overflow;\n",
     "DSR |= carry;\n",
@@ -2148,7 +2148,7 @@ op ppi_tab[] =
     "if (Sy <= 16)",
     "  res = Sx << Sy;",
     "else if (Sy >= 128 - 16)",
-    "  res = (unsigned) Sx >> 128 - Sy;	/* no sign extension */",
+    "  res = (unsigned) Sx >> (128 - Sy);	/* no sign extension */",
     "else",
     "  {",
     "    RAISE_EXCEPTION (SIGILL);",
@@ -2171,7 +2171,7 @@ op ppi_tab[] =
     "    else",
     "      {",
     "        res = Sx << Sy;",
-    "        res_grd = Sx_grd << Sy | (unsigned) Sx >> 32 - Sy;",
+    "        res_grd = Sx_grd << Sy | (unsigned) Sx >> (32 - Sy);",
     "      }",
     "    res_grd = SEXT (res_grd);",
     "    carry = res_grd & 1;",
@@ -2186,7 +2186,7 @@ op ppi_tab[] =
     "      }",
     "    else",
     "      {",
-    "        res = Sx >> Sy | Sx_grd << 32 - Sy;",
+    "        res = Sx >> Sy | Sx_grd << (32 - Sy);",
     "        res_grd = Sx_grd >> Sy;",
     "      }",
     "    carry = Sx >> (Sy - 1) & 1;",
@@ -3347,7 +3347,7 @@ ppi_gensim (void)
   printf ("  }\n");
   printf ("  DSR &= ~0xf1;\n");
   printf ("  if (res || res_grd)\n");
-  printf ("    DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n");
+  printf ("    DSR |= greater_equal | (res_grd >> 2 & DSR_MASK_N) | overflow;\n");
   printf ("  else\n");
   printf ("    DSR |= DSR_MASK_Z | overflow;\n");
   printf (" assign_dc:\n");
diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index 4cac8de89d53..2bae4484e349 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -195,11 +195,11 @@ do { \
 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
 #define SET_BANKN(EXP) \
 do { \
-  IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
+  IBNR = (IBNR & 0xfe00) | ((EXP) & 0x1f); \
 } while (0)
 #define SET_ME(EXP) \
 do { \
-  IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
+  IBNR = (IBNR & 0x3fff) | (((EXP) & 0x3) << 14); \
 } while (0)
 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
-- 
2.33.0


  parent reply	other threads:[~2021-11-07  0:34 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-07  0:32 [PATCH 1/6] sim: sh: rework register layout with anonymous unions & structs Mike Frysinger via Gdb-patches
2021-11-07  0:32 ` [PATCH 2/6] sim: sh: fix unused-value warnings Mike Frysinger via Gdb-patches
2021-11-07  0:32 ` Mike Frysinger via Gdb-patches [this message]
2021-11-07  0:32 ` [PATCH 4/6] sim: sh: constify a few read-only lookup tables Mike Frysinger via Gdb-patches
2021-11-07  0:32 ` [PATCH 5/6] sim: sh: fix uninitialized variable usage with pdmsb Mike Frysinger via Gdb-patches
2021-11-07  0:32 ` [PATCH 6/6] sim: sh: enable -Werror everywhere Mike Frysinger via Gdb-patches
2021-11-11 12:41 ` [PATCH 1/6] sim: sh: rework register layout with anonymous unions & structs Luis Machado via Gdb-patches
2021-11-11 22:25   ` Mike Frysinger via Gdb-patches
2021-11-11 22:32     ` Luis Machado via Gdb-patches
2021-11-11 22:38       ` Luis Machado via Gdb-patches
2021-11-11 22:45       ` Mike Frysinger via Gdb-patches
2021-11-12 13:12         ` Luis Machado via Gdb-patches
2021-11-12  0:39   ` [PATCH 1/2] sim: sh: rework carry checks to not rely on integer overflows Mike Frysinger via Gdb-patches
2021-11-12  0:39     ` [PATCH 2/2] sim: sh: fix switch-bool warnings Mike Frysinger via Gdb-patches

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