From: Andrew Burgess <andrew.burgess@embecosm.com>
To: 紀重禕 <demonic@csie.io>
Cc: gdb-patches@sourceware.org
Subject: Re: [PATCH] gdb/riscv: fix recorded insn type
Date: Thu, 17 Sep 2020 09:49:28 +0100 [thread overview]
Message-ID: <20200917084928.GB2697@embecosm.com> (raw)
In-Reply-To: <CA+YVB3RzggCoDf5i8bPdAd2zKN+UkcmC6VzA4DhaGx4LFCpZJQ@mail.gmail.com>
Thanks for catching this.
I have pushed this fix.
Thanks,
Andrew
* 紀重禕 <demonic@csie.io> [2020-09-17 10:14:05 +0800]:
> Hi, I fixed the instruction type in the decoding method.
> ---
> gdb/ChangeLog | 3 +++
> gdb/riscv-tdep.c | 2 +-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/gdb/ChangeLog b/gdb/ChangeLog
> index 84ee292750..5bf0c8ff14 100644
> --- a/gdb/ChangeLog
> +++ b/gdb/ChangeLog
> @@ -1,3 +1,6 @@
> +2020-09-17 Chungyi Chi <demonic@csie.io>
> + * riscv-tdep.c (riscv-insn::decode): Fix recorded insn type.
> +
> 2020-09-16 Simon Marchi <simon.marchi@efficios.com>
>
> * breakpoint.h (init_catchpoint): Change int parameter to bool.
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index a7c25642d0..ac4ac1b6fd 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -1472,7 +1472,7 @@ riscv_insn::decode (struct gdbarch *gdbarch,
> CORE_ADDR pc)
> else if (is_c_swsp_insn (ival))
> decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
> else if (xlen != 4 && is_c_sdsp_insn (ival))
> - decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
> + decode_css_type_insn (SD, ival, EXTRACT_RVC_SDSP_IMM (ival));
> /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a
> C_JR.
> So must try to match C_JR first as it ahs more bits in mask. */
> else if (is_c_jr_insn (ival))
> --
> 2.25.0
prev parent reply other threads:[~2020-09-17 8:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-17 2:14 紀重禕
2020-09-17 8:49 ` Andrew Burgess [this message]
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