From: Victor Collod <vcollod@nvidia.com>
To: <gdb-patches@sourceware.org>
Subject: [PATCH v3 3/7] amd64_analyze_prologue: merge op and buf
Date: Tue, 23 Jun 2020 18:28:53 -0700 [thread overview]
Message-ID: <20200624012857.31849-4-vcollod@nvidia.com> (raw)
In-Reply-To: <20200624012857.31849-1-vcollod@nvidia.com>
Both variables were used to store function code.
2020-06-23 Victor Collod <vcollod@nvidia.com>
* amd64-tdep.c (amd64_analyze_prologue): Merge op and buf.
---
gdb/amd64-tdep.c | 28 +++++++++++-----------------
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
index ff12cb874b8..c1a9b553e20 100644
--- a/gdb/amd64-tdep.c
+++ b/gdb/amd64-tdep.c
@@ -2374,7 +2374,6 @@ amd64_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR pc, CORE_ADDR current_pc,
struct amd64_frame_cache *cache)
{
- enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* The `endbr64` instruction. */
static const gdb_byte endbr64[4] = { 0xf3, 0x0f, 0x1e, 0xfa };
/* There are two variations of movq %rsp, %rbp. */
@@ -2384,8 +2383,7 @@ amd64_analyze_prologue (struct gdbarch *gdbarch,
static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
- gdb_byte buf[3];
- gdb_byte op;
+ gdb_byte buf[4];
/* Analysis must not go past current_pc. */
if (pc >= current_pc)
@@ -2396,24 +2394,20 @@ amd64_analyze_prologue (struct gdbarch *gdbarch,
else
pc = amd64_analyze_stack_align (pc, current_pc, cache);
- op = read_code_unsigned_integer (pc, 1, byte_order);
-
- /* Check for the `endbr64` instruction, skip it if found. */
- if (op == endbr64[0])
+ read_code (pc, buf, 4);
+ /* Check for the `endbr64' instruction and skip it if found. */
+ if (memcmp (buf, endbr64, sizeof (endbr64)) == 0)
{
- read_code (pc + 1, buf, 3);
-
- if (memcmp (buf, &endbr64[1], 3) == 0)
- pc += 4;
+ pc += sizeof (endbr64);
+ /* If we went past the allowed bound, stop. */
+ if (pc >= current_pc)
+ return current_pc;
- op = read_code_unsigned_integer (pc, 1, byte_order);
+ /* Update the code buffer, as pc changed. */
+ read_code (pc, buf, 1);
}
- /* If we went past the allowed bound, stop. */
- if (pc >= current_pc)
- return current_pc;
-
- if (op == 0x55) /* pushq %rbp */
+ if (buf[0] == 0x55) /* pushq %rbp */
{
/* Take into account that we've executed the `pushq %rbp' that
starts this instruction sequence. */
--
2.20.1
next prev parent reply other threads:[~2020-06-24 1:29 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-05 23:23 [PATCH] Improve intel IBT support Victor Collod
2020-06-05 23:55 ` Victor Collod
2020-06-11 3:18 ` Simon Marchi
2020-06-11 22:54 ` [PATCH v2 0/2] " Victor Collod
2020-06-11 22:54 ` [PATCH v2 1/2] Add i386 support for endbr skipping Victor Collod
2020-06-21 11:27 ` Simon Marchi
2020-06-11 22:54 ` [PATCH v2 2/2] Refactor amd64_analyze_prologue Victor Collod
2020-06-21 11:38 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 0/7] Improve intel IBT support Victor Collod
2020-06-24 1:28 ` [PATCH v3 1/7] Add i386 support for endbr skipping Victor Collod
2020-08-06 13:57 ` Simon Marchi
2020-09-19 0:29 ` [PATCH] gdb: Update i386_analyze_prologue to skip endbr32 H.J. Lu
2020-09-19 0:38 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 2/7] amd64_analyze_prologue: swap upper bound check condition operands Victor Collod
2020-08-06 14:41 ` Simon Marchi
2020-06-24 1:28 ` Victor Collod [this message]
2020-08-06 14:55 ` [PATCH v3 3/7] amd64_analyze_prologue: merge op and buf Simon Marchi
2020-06-24 1:28 ` [PATCH v3 4/7] amd64_analyze_prologue: invert a condition for readability Victor Collod
2020-08-06 14:57 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 5/7] amd64_analyze_prologue: gradually update pc Victor Collod
2020-08-06 14:59 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 6/7] amd64_analyze_prologue: fix incorrect comment Victor Collod
2020-08-06 15:05 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 7/7] amd64_analyze_prologue: use target_read_code instead of read_code Victor Collod
2020-08-06 15:01 ` Simon Marchi
2020-08-05 21:44 ` [PATCH v3 0/7] Improve intel IBT support Victor Collod
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